KR102199413B1 - Embedded Printed Circuit Board and Method of Manufacturing the Same - Google Patents

Abstract

The printed circuit board according to an aspect of the present application includes a base insulating layer, a first and second inner circuit pattern layer disposed on the upper and lower surfaces of the base insulating layer, respectively, and on the upper and lower surfaces of the base insulating layer, A cavity exposing the base insulating layer by penetrating at least one of the first and second interlayer insulating layers respectively covering the first and second inner circuit pattern layers, the first and second interlayer insulating layers, and in the cavity A connection pad layer disposed in contact with at least one of the first and second inner circuit pattern layers exposed at the side surface and covering at least a portion of the sidewall surface of the cavity, and a conductive solder material layer disposed inside the cavity And a device chip electrically connected to the connection pad layer through the connection pad layer. The cavity exposes at least one side surface of the first and second inner circuit pattern layers.

Description

Embedded Printed Circuit Board and Method of Manufacturing the Same}

The present application relates to an embedded printed circuit board, and more particularly, to an embedded printed circuit board including a connection pad on a sidewall of a cavity, and a method of manufacturing the same.

Today, the semiconductor industry is developing toward manufacturing light weight, miniaturization, high speed, multifunctional, high performance, and highly reliable semiconductor products at low cost, and one of the important technologies to achieve this is semiconductor package technology. Semiconductor package technology is a technology for mounting a semiconductor chip on a printed circuit board through a wafer process to form a circuit part, a technology for securing an electrical connection between a semiconductor chip and an external electronic device through the printed circuit board, and removing the semiconductor chip from an external environment. It means the technology to protect, etc.

In recent years, in accordance with the trend of light, thin, and short package products, various researches have been conducted on process technologies capable of reducing the thickness of the printed circuit board and miniaturizing the printed circuit pattern. As one of the techniques for reducing the thickness of the printed circuit board, an embedded printed circuit board technology has been proposed in which a cavity is formed in a substrate and a device chip is mounted inside the cavity.

An embodiment of the present application provides a structure of an embedded printed circuit board capable of reducing an overall thickness and a method of manufacturing the same.

The printed circuit board according to an aspect of the present application includes a base insulating layer, a first and second inner circuit pattern layer disposed on the upper and lower surfaces of the base insulating layer, respectively, and on the upper and lower surfaces of the base insulating layer, A cavity exposing the base insulating layer by penetrating at least one of the first and second interlayer insulating layers respectively covering the first and second inner circuit pattern layers, the first and second interlayer insulating layers, and in the cavity A connection pad layer disposed in contact with at least one of the first and second inner circuit pattern layers exposed at the side surface and covering at least a portion of the sidewall surface of the cavity, and a conductive solder material layer disposed inside the cavity And a device chip electrically connected to the connection pad layer through the connection pad layer. The cavity exposes at least one side surface of the first and second inner circuit pattern layers.

In a method of manufacturing a printed circuit board according to another aspect of the present application, a base substrate including a base insulating layer is prepared. First and second inner circuit pattern layers are formed on the upper and lower surfaces of the base insulating layer, respectively. First and second interlayer insulating layers are formed on the upper and lower surfaces of the base insulating layer to cover the first and second inner circuit pattern layers, respectively. A cavity is formed through at least one of the first and second interlayer insulating layers to expose the base insulating layer. In this case, the cavity exposes at least one side surface of the first and second inner circuit pattern layers. In the cavity, a connection pad layer is formed in contact with the exposed first and second inner circuit pattern layers and covers at least a portion of a sidewall surface of the cavity. A device chip is placed in the cavity. A conductive solder material layer electrically connecting the device chip and the connection pad layer is formed.

According to embodiments of the present application, an embedded printed circuit board including a cavity formed inside a base insulating layer and a connection pad layer disposed on a sidewall surface of the cavity may be provided. A device chip mounted in the cavity may be electrically connected to the connection pad layer through a conductive solder material layer disposed in a lateral direction.

As described above, the connection pad layer of the embedded printed circuit board and the electrode layer of the device chip are arranged to be connected to each other in the lateral direction, so that the height from the top surface of the base insulating layer in the cavity to the top surface of the device chip can be reduced. have. That is, compared to the conventional case in which connection structures such as a connection pad layer and a bump are sequentially disposed on the upper surface of the base insulating layer inside the cavity, in the embodiment of the present application, in the embedded printed circuit board, the connection pad The height of the layer and the bump may be reduced. Accordingly, it is possible to provide a thin embedded printed circuit board.

1 is a cross-sectional view schematically showing an embedded printed circuit board 1 according to an exemplary embodiment of the present application.
FIG. 2 is a plan view of a part of the embedded printed circuit board 1 of FIG. 1 as viewed from a'U' direction.
3 to 10 are cross-sectional views schematically illustrating a method of manufacturing an embedded printed circuit board according to an embodiment of the present application.

The terms used in the description of the examples in the present application are terms selected in consideration of functions in the presented embodiments, and the meaning of the terms may vary according to the intention or custom of users or operators in the technical field. The meanings of the terms used are in accordance with the defined definitions when they are specifically defined in the present specification, and may be interpreted as meanings generally recognized by those skilled in the art if there is no specific definition. In the description of the examples of the present application, descriptions such as "first" and "second", "top" and "bottom or lower", "left" and "right" are absent. It is intended to distinguish between, and is not used to limit the member itself or to mean a specific order.

The same reference numerals may refer to the same elements throughout the specification. The same or similar reference numerals may be described with reference to other drawings, even if they are not mentioned or described in the corresponding drawings. Further, even if a reference numeral is not indicated, it may be described with reference to other drawings.

1 is a cross-sectional view schematically showing an embedded printed circuit board 1 according to an exemplary embodiment of the present application. FIG. 2 is a plan view of a part of the embedded printed circuit board 1 of FIG. 1 as viewed from a'U' direction.

Referring to FIG. 1, the embedded printed circuit board 1 includes a base insulating layer 110, first and second inner circuit pattern layers 120a and 120b, first and second interlayer insulating layers 132a and 132b, The connection pad layers 142a1 and 142a2 disposed to cover at least a portion of the cavity 1000 inside the first interlayer insulating layer 132a, the sidewall surface of the cavity 1000, and the connection pad layer disposed inside the cavity 1000 And a device chip 20 electrically connected to the 142a1 and 142a2.

The base insulating layer 110 may include, as an example, a thermosetting resin. The base insulating layer 110 may further include carbon fiber or glass fiber as a structural material, as an example. As an example, the base insulating layer 110 may include a phenol resin, an epoxy resin, or a prepreg (PPG). The base insulating layer 110 may have an upper surface 110S1 and a lower surface 110S2 positioned opposite each other.

The first and second inner circuit pattern layers 120a and 120b may be disposed on the upper surface 110S1 and the lower surface 110S2 of the base insulating layer 110, respectively. The first and second inner circuit pattern layers 120a and 120b may be copper plating layers.

The first and second interlayer insulating layers 132a and 132b cover the first and second inner circuit pattern layers 120a and 120b, respectively, on the upper surface 110S1 and the lower surface 110S2 of the base insulating layer 110. Can be placed. The first and second interlayer insulating layers 132a and 132b may include, for example, a thermosetting resin. As an example, the first and second interlayer insulating layers 132a and 132b may further include carbon fibers or glass fibers as a structural material. As an example, the first and second interlayer insulating layers 132a and 132b may include a phenol resin, an epoxy resin, or a prepreg (PPG).

First and second outer circuit pattern layers 146a and 146b may be disposed on the first and second interlayer insulating layers 132a and 132b, respectively. The first and second outer circuit pattern layers 146a and 146b may be copper pattern layers. In addition, vias 144a and 144b may be disposed inside the first and second interlayer insulating layers 132a and 132b, respectively. Vias 144a and 144b are formed through the first and second interlayer insulating layers 132a and 132b, respectively, corresponding first and second inner circuit pattern layers 120a and 120b and first and second outer layers The circuit layers 146a and 146b may be electrically connected. The vias 144a and 144b may be a copper plating layer.

First and second solder resist pattern layers 160a and 160b may be disposed on the first and second interlayer insulating layers 132a and 132b, respectively. The first and second solder resist pattern layers 160a and 160b may be disposed to selectively cover the first and second outer circuit pattern layers 146a and 146b. The first and second outer circuit pattern layers 146a and 146b exposed by the first and second solder resist pattern layers 160a and 160b may function as pads for connection with other device chips or other packages. have.

Referring back to FIG. 1, a cavity 1000 is formed through the first interlayer insulating layer 132a to expose the base insulating layer 110. The cavity 1000 may expose a side surface of the first inner circuit pattern layer 120a. In addition, connection pad layers 142a1 and 142a2 may be disposed on a sidewall surface of the cavity 1000. The connection pad layers 142a1 and 142a2 may be disposed to be in contact with the first inner circuit pattern layer 120a with the side surfaces exposed and to cover at least a portion of the sidewall surface of the cavity 1000. That is, the connection pad layers 142a1 and 142a2 may be disposed to directly contact side surfaces of the first inner circuit pattern layer 120a and the first interlayer insulating layer 132a.

Referring to FIGS. 1 and 2 together, the connection pad layers 142a1 and 142a2 may be disposed in a pair of conductive patterns facing each other on a sidewall surface of the cavity 1000. The connection pad layers 142a1 and 142a2 may have a first width w1 in the x-direction, a second width w2 in the y-direction, and a height h1 in the z-direction. In particular, as shown in FIG. 2, the cavity 1000 may have a rectangular internal space on a plan view, and the connection pad layers 142a1 and 142a2 are in the sidewall surfaces facing each other, in the height direction of the side surface (for example, As, it may be disposed along the z-direction of FIG. 1). In this case, referring to FIG. 1, the height h1 of the connection pad layers 142a1 and 142a2 may be substantially the same as the height of the first interlayer insulating layer 132a in which the cavity 1000 is formed.

Meanwhile, the device chip 20 may be mounted inside the cavity 1000. The device chip 20 may be, for example, a passive device. As an example, the passive element may include a capacitor, a resistor, or an inductor. The device chip 20 may include a first electrode part 210, a second electrode part 220, and a function part 230. The functional unit 230 may include, for example, a capacitor material layer, a resistive material layer, or a coil material layer. As an embodiment, when the device chip 20 is a multilayer ceramic capacitor (MLCC), the functional unit 230 may be a multilayered unit in which a dielectric layer and an internal electrode layer cross each other, and the first and second layers are stacked. The electrode parts 210 and 220 may be external terminal electrodes electrically connected to the internal electrode layer.

The device chip 20 may be disposed on the upper surface 110S1 of the base insulating layer 110 to face the pair of connection pad layers 142a1 and 142a2. The device chip 20 may be electrically connected to the connection pad layers 142a1 and 142a2 through the conductive solder material layers 150a1 and 150a2. The conductive solder material layers 150a1 and 150a2 adhere to the first electrode part 210 and any one of the pair of connection pad layers 142a1 and 142a2 (142a1), and further, the second electrode part 220 and The remaining one 142a2 of the pair of connection pad layers 142a1 and 142a2 may be adhered. Through this, the conductive solder material layers 150a1 and 150a2 move the connection pad layers 142a1 and 142a2 and the device chip 20 in the lateral direction (for example, the x-direction) on the upper surface 110S1 of the base insulating layer 110. ) Can be joined.

In some embodiments not shown, for stability of the device chip 20, a separate adhesive layer may be disposed between the device chip 20 and the upper surface 110S1 of the base insulating layer 110. The adhesive layer may improve adhesion between the device chip 20 and the base insulating layer 110.

In some other embodiments, the cavity 1000 may be formed in the second interlayer insulating layer 132b. Accordingly, the configuration and arrangement of the connection pad layer and the conductive solder material layer for mounting the device chip in the cavity 1000 formed in the second interlayer insulating layer 132b is described above with reference to FIGS. 1 and 2. The configurations of the connection pad layers 142a1 and 142a2 inside the cavity 1000 formed in the one interlayer insulating layer 132a and the conductive solder material layers 150a1 and 150a2 are substantially the same.

In some other embodiments, the cavity 1000 may be formed in both the first and second interlayer insulating layers 132a and 132b. Accordingly, the configuration and arrangement of the connection pad layer and the conductive solder material layer for mounting the device chip in the cavity 1000 formed in the first and second interlayer insulating layers 132a and 132b is the above-described first interlayer insulating layer The configuration arrangement of the connection pad layers 142a1 and 142a2 inside the cavity 1000 formed in the 132a and the conductive solder material layers 150a1 and 150a2 may be applied in the same manner.

As described above, according to the embodiment of the present application, in the cavity 1000 of the embedded printed circuit board 1, the device chip 20 is a pair of connection pad layers disposed on the sidewalls of the cavity 1000 (142a1, 142a2) and the lateral direction (for example, x-direction) can be made an electrical junction. To this end, conductive solder material layers 150a1 and 150a2 may be disposed in the lateral direction between the first and second electrode portions 210 and 220 of the device chip 20 and the connection pad layers 142a1 and 142a2. In the case of a conventional embedded printed circuit board, after the connection pad layer and the conductive solder material layer are sequentially disposed on the lower surface of the cavity 1000, that is, the upper surface 110S1 of the base insulating layer 110, the conductive solder layer is A structure that bonds to the device chip is applied. In this way, since the device chip is disposed on the conductive solder material layer, the thickness of the embedded printed circuit board may increase as much as the thickness of the connection pad layer and the conductive solder material layer.

On the contrary, according to the exemplary embodiment of the present application, the connection pad layers 142a1 and 142a2 are disposed on the sidewall of the cavity 1000, not on the lower surface of the cavity 1000. In addition, since the conductive solder material layers 150a1 and 150a2 bond the connection pad layers 142a1 and 142a2 and the device chip 20 in the lateral direction (for example, the x-direction), compared to the conventional embedded printed circuit board. Thus, there is an advantage of reducing the thickness of the entire embedded printed circuit board by the thickness of the connection pad layer and the conductive solder material layer.

3 to 10 are cross-sectional views schematically illustrating a method of manufacturing an embedded printed circuit board according to an embodiment of the present application. Referring to FIG. 3, a base substrate 10 is prepared. The base substrate 10 includes a base insulating layer 110 having an upper surface 110S1 and a lower surface 110S2. In addition, the base substrate 10 may include first and second seed copper layers 112a and 112b on the upper surface 110S1 and the lower surface 110S2 of the base insulating layer 110. As an example, the base substrate 10 may be a copper laminated substrate (Copper Clad Laminate).

Referring to FIG. 4, by performing a plating method using the first and second seed copper layers 112a and 112b of the base substrate 10, the upper surface 110S1 and the lower surface 110S2 of the base insulating layer 110 are First and second inner circuit pattern layers 120a and 120b are formed, respectively. The first and second inner circuit pattern layers 120a and 120b may be copper plating layers. The plating method may apply electrolytic plating, electroless plating, or a combination of two or more thereof. Specifically, as the plating method, SAP (Semi-Additive Process) or MSAP (Modified Semi-Additive Process) may be applied.

In an embodiment, the method of forming the first and second inner circuit pattern layers 120a and 120b is to form a dry film pattern on the first and second seed copper layers 112a and 112b. A copper plating layer is formed from the first and second seed copper layers 112a and 112b exposed by the dry film pattern. Subsequently, a copper pattern layer may be formed by removing the dry film pattern and the first and second seed copper layers 112a and 112b positioned directly under the dry film pattern. The copper pattern layer may constitute first and second inner circuit pattern layers 120a and 120b.

Referring to FIG. 5, first and second interlayer stacked structures 130a covering the first and second inner circuit pattern layers 120a and 120b on the upper surface 110S1 and the lower surface 110S2 of the base insulating layer 110, respectively. , 130b). The first and second interlayered structures 130a and 130b are respectively disposed on the first and second interlayer insulating layers 132a and 132b and the first and second interlayer insulating layers 132a and 132b. It includes 2 copper foil layers 134a and 134b, respectively.

In a specific embodiment, the first and second interlayer stacked structures 130a and 130b may be formed through the following process.

First, a first intermediate substrate material 130a including a first interlayer insulating layer 132a and a first copper foil layer 134a disposed on the first interlayer insulating layer 132a is prepared. Similarly, a second intermediate substrate 130b including a second interlayer insulating layer 132b and a second copper foil layer 134b disposed on the second interlayer insulating layer 132b is prepared.

Subsequently, in a direction in which the first interlayer insulating layer 132a of the first intermediate substrate material 130a faces the first inner circuit pattern layer 120a, the first intermediate substrate material 130a is placed over the structure of FIG. 4. And the second intermediate substrate material 130b in a direction in which the second interlayer insulating layer 132b of the second intermediate substrate material 130b faces the second inner circuit pattern layer 120b. It should be placed apart from the bottom of the structure of Subsequently, the first and second intermediate substrate materials 130a and 130b are bonded to the structure of FIG. 4 using heat and pressure. As a result, the first and second intermediate substrate materials 130b may be bonded to the structure of FIG. 4 to be converted into first and second interlayer stacked structures 130a and 130b.

Referring to FIG. 6, a cavity 1000 for selectively exposing the base insulating layer 110 is formed through the first copper foil layer 134a and the first interlayer insulating layer 132a. In this case, the cavity 1000 may expose side surfaces of the first interlayer stacked structure 130a and the first inner circuit pattern layer 120a. In this case, the exposed first inner circuit pattern layers 120a may be positioned in a pair on sidewalls of the cavity 1000 facing each other.

Referring to FIG. 7, via holes are formed through each of the first and second interlayer insulating layers 132a and 132b to expose the first and second inner circuit pattern layers 120a and 120b, respectively. As a method of forming the via hole, laser drilling or mechanical drilling may be applied. Subsequently, first and second vias 144a and 144b filling the via hole are formed. Subsequently, first and second outer circuit pattern layers 146a and 146b electrically connected to the first and second vias 144a and 144b are formed on the first and second interlayer insulating layers 132a and 132b, respectively. do. The method of forming the first and second vias 144a and 144b, and the first and second outer circuit pattern layers 146a and 146b is, as an example, electrolytic plating, electroless plating, or a combination of two or more thereof. Can be applied. Specifically, as the plating method, SAP (Semi-Additive Process) or MSAP (Modified Semi-Additive Process) may be applied. At this time, the copper coil layers 134a and 134b of the first and second interlayer stacked structures 130a and 130b are formed when the first and second outer circuit pattern layers 146a and 146b are formed by plating, a seed copper layer Each can function as.

Referring to FIG. 8, connection pad layers 142a1 and 142a2 that are in contact with the first inner circuit pattern layer 120a with exposed side surfaces of the cavity 1000 and cover at least a portion of the sidewall surface of the cavity 1000 are formed. To form. The connection pad layers 142a1 and 142a2 may be copper pattern layers formed along a sidewall surface of the cavity 1000. As an example, the plating method may be electrolytic plating, electroless plating, or a combination of two or more thereof. Specifically, as the plating method, SAP (Semi-Additive Process) or MSAP (Modified Semi-Additive Process) may be applied.

In an embodiment, the connection pad layers 142a1 and 142a2 may be performed in a process of forming a copper pattern layer along a sidewall surface of the cavity. The connection pad layers 142a1 and 142a2 may have a first width w1 in the x-direction and a height h1 in the z-direction. The height h1 may be greater than the first width w1. The height h1 may be substantially the same as the height of the first interlayer insulating layer 132a.

Referring to FIG. 9, a device chip 20 including first and second electrode units 210 and 220 and a function unit 230 is prepared. As an example, the device chip 20 may be a passive device chip. In an embodiment, the passive component chip may be a multilayer ceramic capacitor (MLCC). The device chip 20 is mounted in the cavity 1000. At this time, the device chip 20 is disposed to be spaced apart from the connection pad layers 142a1 and 142a2 in the lateral direction (ie, x-direction). Although not shown, when the device chip 20 is mounted, the lower surface of the device chip 20 and the upper surface 110S1 of the base insulating layer 110 may be adhered by a separate adhesive layer.

Subsequently, a conductive solder material is prepared, and heat is applied to the conductive solder material so that the conductive solder material has fluidity. The conductive solder material having the fluidity is provided in the space between the first and second electrode portions 210 and 220 and the connection pad layers 142a1 and 142a2. As the conductive solder material filling the space solidifies, the first and second electrode portions 210 and 220 and the connection pad layers 142a1 and 142a2 are adhered. Through this, conductive solder material layers 150a1 and 150a2 may be formed.

Referring to FIG. 10, first and second solder resist pattern layers 160a selectively covering the first and second outer circuit pattern layers 146a and 146b on the first and second interlayer insulating layers 132a and 132b. , 160b). The first and second outer circuit pattern layers 146a and 146b exposed by the first and second solder resist pattern layers 160a and 160b can function as pads for connection with other device chips or other packages. have. Through the above-described process, an embedded printed circuit board according to an embodiment of the present application may be manufactured.

According to some other embodiments, the process of forming the first and second vias 144a and 144b and the first and second outer circuit pattern layers 146a and 146b described above with reference to FIG. This may be performed after the process of forming the connection pad layers 142a1 and 142a2 described above. That is, after first forming the connection pad layers 142a and 142a2 described above with respect to FIG. 8, the first and second vias 144a and 144b described above with respect to FIG. 7, and the first and second outer layer circuits Pattern layers 146a and 146b may be formed. Thereafter, a process of mounting the device chip 20 in the cavity 1000 described above with respect to FIGS. 9 and 10 and forming the first and second solder resist pattern layers 160a and 160b may be subsequently performed. .

According to some other embodiments, the device chip may be mounted in a cavity in the second interlayer insulating layer 132b rather than the cavity 1000 in the first interlayer insulating layer 132a. The process of forming a cavity in the second interlayer insulating layer 132b and the process of mounting a device chip in the cavity include the cavity 1000 in the first interlayer insulating layer 132a described above with reference to FIGS. 6 to 10. It is substantially the same as the forming process and the mounting process of the device chip in the cavity 1000. Further, according to some other embodiments, cavities may be formed in both the first and second interlayer insulating layers 132a and 132b, and device chips may be mounted in the cavities. At this time, the process of forming cavities in the first and second interlayer insulating layers 132a and 132b and mounting the device chip in the cavity may be performed in the first interlayer insulating layer 132a described above with reference to FIGS. 6 to 10. The process of forming the cavity 1000 and mounting the device chip in the cavity 1000 may be substantially the same.

In some other embodiments, in the process of forming the first and second interlayered structures 130a and 130b described above with reference to FIG. 5, the manufactured first and second interlayered structures 130a and 130b are It may be formed of only the first and second interlayer insulating layers 132a and 132b excluding the first and second copper foil layers 134a and 134b. Accordingly, the first and second intermediate substrate materials 130a and 130b used in the manufacturing process do not include the first and second copper foil layers 134a and 134b, respectively, and the first and second interlayer insulating layers It may also consist of only (132a, 132b).

As described above, embodiments of the present application are illustrated and described with the drawings, but this is for explaining what is to be presented in the present application, and is not intended to limit what is to be presented in the present application in a detailed shape. As long as the technical idea presented in the present application is reflected, various other modifications will be possible.

1: embedded printed circuit board, 20: device chip,
110: base insulating layer, 110S1: upper surface, 110S2: lower surface,
120a, 120b: first and second inner circuit pattern layers,
132a, 132b: first and second interlayer insulating layers,
142a1, 142a2: connection pad layer,
144a, 144b: via,
146a, 146b: first and second outer circuit pattern layers,
210, 220: first and second electrode portions, 230: functional portion,
150a1, 150a2: conductive solder material layer,
160a, 160b: first and second solder resist pattern layers.
1000: cavity.

Claims (15)

A base insulating layer;
First and second inner circuit pattern layers disposed on upper and lower surfaces of the base insulating layer, respectively;
First and second interlayer insulating layers covering the first and second inner circuit pattern layers, respectively, on the upper and lower surfaces of the base insulating layer;
A cavity through at least one of the first and second interlayer insulating layers to expose the base insulating layer, the cavity exposing at least one side surface of the first and second inner circuit pattern layers;
A connection pad layer disposed on a sidewall surface of the cavity and in contact with at least one of the first and second inner circuit pattern layers with the side surfaces exposed in the cavity;
A device chip disposed inside the cavity and electrically connected to the connection pad layer through a conductive solder material layer; And
Including an adhesive layer disposed between the device chip and the base insulating layer inside the cavity,
The device chip is electrically connected only to the connection pad layer disposed on the sidewall surface of the cavity.
Embedded printed circuit board.
The method of claim 1,
The connection pad layer
Disposed to directly contact at least one of the first and second inner circuit pattern layers and at least one of the first and second interlayer insulating layers
Embedded printed circuit board.
The method of claim 2,
The connection pad layer
Arranged in a pair of conductive patterns facing each other on the sidewall surface of the cavity
Embedded printed circuit board.
The method of claim 1,
The device chip is
A passive element chip comprising first and second electrode units electrically insulated from each other and a functional unit disposed between the first and second electrode units
Embedded printed circuit board.
The method of claim 4,
The device chip is
It is disposed to face a pair of connection pad layers in a lateral direction on at least one of the upper and lower surfaces of the base insulating layer,
The conductive solder material layer adheres any one of the first electrode portion and the pair of connection pad layers, and also bonds the second electrode portion and the other one of the pair of connection pad layers.
Embedded printed circuit board.
The method of claim 1,
The height of the connection pad layer is
Substantially equal to the height of at least one of the first and second interlayer insulating layers in which the cavity is formed
Embedded printed circuit board. The method of claim 1,
The conductive solder material layer
Bonding the connection pad layer and the device chip in a lateral direction on at least one of the upper and lower surfaces of the base insulating layer
Embedded printed circuit board.
The method of claim 1,
First and second outer circuit pattern layers disposed on the first and second interlayer insulating layers;
First and second vias disposed through the first and second interlayer insulating layers and electrically connecting the corresponding first and second inner circuit pattern layers and the first and second outer circuit layers;
Further comprising first and second solder resist pattern layers selectively covering the first and second outer circuit pattern layers on the first and second interlayer insulating layers
Embedded printed circuit board.
Preparing a base substrate including a base insulating layer;
Forming first and second inner circuit pattern layers on upper and lower surfaces of the base insulating layer, respectively;
Forming first and second interlayer insulating layers covering the first and second inner circuit pattern layers, respectively, on the upper and lower surfaces of the base insulating layer;
A cavity is formed to selectively expose the base insulating layer by penetrating at least one of the first and second interlayer insulating layers, wherein the cavity exposes at least one side surface of the first and second inner circuit pattern layers Letting go;
Forming a connection pad layer on the sidewall surface of the cavity and in contact with at least one of the first and second inner circuit pattern layers exposed at the side surfaces of the cavity;
Placing a device chip in the cavity; And
Including the step of forming a conductive solder material layer electrically connecting the device chip and the connection pad layer,
Arranging the device chip in the cavity includes forming an adhesive layer on the base insulating layer inside the cavity, and bonding the device chip and the base insulating layer by the adhesive layer,
The device chip is configured to electrically connect only with the connection pad layer disposed on the sidewall surface of the cavity.
Manufacturing method of embedded printed circuit board.
The method of claim 9,
The step of forming the cavity
Forming the exposed first and second inner circuit pattern layers to be positioned in a pair on sidewalls of the cavity facing each other
Manufacturing method of embedded printed circuit board.
The method of claim 9,
The step of forming the connection pad layer
Performed by at least one method selected from electrolytic plating and electroless plating
Manufacturing method of embedded printed circuit board.
The method of claim 11,
The step of forming the connection pad layer
Including the step of forming a copper pattern layer along the sidewall surface of the cavity
Manufacturing method of embedded printed circuit board.
The method of claim 9,
The step of forming the connection pad layer
Comprising the step of forming a pair of conductive patterns facing each other on the sidewall surface of the cavity
Manufacturing method of embedded printed circuit board.
The method of claim 9,
Arranging the device chip in the cavity
Preparing a passive element chip including first and second electrode layers electrically insulated from each other and a functional layer disposed between the first and second electrode layers; And
And disposing the passive device chip to be spaced apart from the connection pad layer in a lateral direction.
Manufacturing method of embedded printed circuit board.
The method of claim 14,
Forming the conductive solder material layer
Preparing a conductive solder material;
Applying heat to the conductive solder material to have fluidity, and then providing the conductive solder material in the space between the passive element chip and the connection pad layer; And
Solidifying the conductive solder material to adhere the passive component chip and the connection pad layer
Manufacturing method of embedded printed circuit board.

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