JPH0563000A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing an SOI element, where a SOIFET junction is kept in symmetric property so as to restrain a parasitic bipolar effect, and the SOI element is stabilized in element characteristics and enhanced in reliability. CONSTITUTION:In a process of making an insulated gate FET formed on an element forming film 2 provided onto an insulator 1, a gate 4 is formed on an element forming film 2 through the intermediary of a gate insulating film 3, then a side wall 5 formed of the insulating film 3 is formed on the side face of the gate 4, and a source and a drain 6 are formed on the element forming film 2 located on both the sides of the gate 4, and an additional process where fixed positive charge 7 is generated in the side wall 5 by the irradiation of radiation is added.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an SOI element. SOI (Silicon
On Insulator) The device formed on the substrate has many advantages such as the integrity of device isolation, the high speed when the device is formed on a thin SOI film, and the reduction of parasitic capacitance to the substrate.
On the other hand, since the channel part is in a floating state, the parasitic bipolar operation formed by the drain / channel part / source is likely to occur, which stabilizes the device characteristics and hinders the reliability of the device. .

The present invention can be used as a method to meet this need.

[0003]

2. Description of the Related Art An SOI substrate is usually an insulating film (SO
This is a substrate on which an element forming film (SOI film) is formed via an I insulating film).

Conventionally, in order to suppress the parasitic bipolar effect, it is generally considered that the junction on the source side is destroyed and the source is connected to the substrate so that the channel portion is not brought into a floating state.

Therefore, the following measures have been taken. For example, in the case of an n-channel FET, the high-concentration p-type layer connected to the supporting substrate is connected to the source junction to form a structure below the source junction.

Alternatively, there is a method in which aluminum (Al) of the wiring and silicon (Si) of the substrate are reacted at the interface by heating or the like only at the source junction, and the Al / Si alloy is grown in a spike shape to destroy the junction. is there.

[0007]

In order to short-circuit or destroy the junction to the substrate and eliminate the floating state of the channel portion as in the conventional example, only the source junction needs to be short-circuited or destroyed.

However, since the FET normally self-aligns with the gate electrode to simultaneously form the source and drain,
It is difficult to achieve the asymmetry of the joint. To realize the asymmetry, an additional mask process is required to protect the drain side from damage.

An object of the present invention is to suppress the parasitic bipolar effect, to stabilize the device characteristics and to improve the reliability of the device without increasing the number of steps.

[0010]

The solution to the above problems is a manufacturing process of an insulated gate field effect transistor (FET) formed on the element forming film 2 on the insulator 1. A gate 4 is formed via a gate insulating film 3, and then a side wall 5 made of an insulating film is formed on the side surface of the gate.
Then, after the element formation process including the step of forming the source / drain 6 on the device formation film on both sides of the gate is completed, a fixed positive charge 7 is generated in the side wall by irradiation of radiation by a method of manufacturing a semiconductor device. To be achieved.

[0011]

[Operation] When the electric field strength at the drain junction is high, collisional ionization of carriers at the drain junction (impact ionization)
Ionization occurs. In this case, due to the electric field between the source and the drain, in the case of an n-channel, the electrons of the electron-hole pairs generated in the channel near the drain junction are absorbed in the drain junction, but the holes move from the channel portion toward the source. Electrons are injected into the source junction due to the movement, causing a parasitic bipolar operation in which the source is the emitter, the channel is the base, and the drain is the collector. Therefore, in order to suppress this parasitic bipolar operation, the electric field at the drain junction should be relaxed.

In order to relax the electric field of the drain junction, in the present invention, a side wall made of silicon dioxide (SiO ₂ ) is formed on the side surface of the gate before forming the source and the drain, and after the element is formed, the element is exposed to radiation (γ Beam, X-ray, particle beam, etc.) to generate a fixed positive charge in the oxide film on the side wall (to generate an electric field in the direction opposite to the electric field at the junction) to relax the electric field at the junction. It was done.

According to the present invention, the fixed positive charges generated in the oxide film on the side wall cause the potential on the substrate surface to have a lateral distribution and generate a lateral electric field change to relax the electric field at the junction. I tried to suppress collision ionization.

When the oxide film is irradiated with radiation, the electron-hole pairs generated in the oxide film move according to the electric field in the oxide film. At this time, the mobility of electrons in the oxide film is 20 c.
a m V ^-1 s ^-1, for the mobility of holes is very small and ^{2E-5 cm V -1 s -1} , the result only holes are trapped in the oxide film to the fixed positive charge Occur. In this case, the amount of fixed positive charges generated depends on the amount of radiation and the magnitude of the electric field in the oxide film.

FIG. 2 is a diagram showing a lateral electric field change due to a fixed positive charge. This figure shows the change in electric field due to the fixed positive charge with respect to the lateral distance of the drain junction.

In the figure, (1) is a channel region, (2) is a sidewall region, and (3) is a drain region. According to the present invention, a fixed positive charge is generated in the oxide film, and in the case of an n-channel FET, the threshold voltage of the FET moves (decreases) to the depletion side due to the generation of the fixed positive charge. Since the oxide film thickness on the side wall is not constant, the local threshold voltage has a lateral distribution. In this case, the electric field change in the lateral direction when the power is off has a distribution as shown in FIG.

Since the potential on the surface of the substrate has a lateral distribution in this way, a lateral electric field change due to the fixed positive charges occurs. Since the direction of the generated electric field is opposite to the electric field in the depletion layer of the junction, the electric field at the junction is relaxed.

Further, in the present invention, since the radiation is applied after the device is formed, the fixed positive charges in the oxide film are retained without being extinguished without being subjected to a heat treatment process thereafter. Here, in the side wall region (2) in FIG. 2, the electric field slightly fluctuates on the channel side for the following reason.

The fixed charges accumulated in the side wall are distributed in many places where the side wall is thick and many places where the side wall is thin. Therefore, the potential at the conduction band edge increases from the thicker part to the thinner part. This is because the direction of the electric field change accompanying this is opposite to the direction of the change of the built-in electric field of the drain pn junction.

As described above, in the present invention, the electric field at the drain junction is relaxed to suppress the generation of electron-hole pairs due to the collisional ionization of carriers at the drain junction, so that the parasitic bipolar effect can be achieved without increasing the number of steps. I tried to suppress it.

[0021]

1 (A) to 1 (D) are sectional views for explaining an embodiment of the present invention. In the figure, 1 is an SOI insulating film (base oxide film), a silicon dioxide (SiO ₂ ) film, 2 is an SOI film (element forming film), a silicon (Si) film, 3 is a gate insulating film, a SiO ₂ film, 4
Is a gate and is a polysilicon film, 5 is a vapor phase growth (CVD)
A side wall made of a SiO ₂ film, 6 is a source / drain region, and 7 is a fixed positive charge generated in the side wall.

The SOI substrate used for element formation is the Si of the SOI film.
SIMOX substrate (Si with a film thickness of 2000 Å and underlying oxide film thickness of 3500 Å
A substrate was used in which oxygen ions were implanted into the substrate to form a base insulating film at a position apart from the substrate surface).

In FIG. 1A, a gate SiO ₂ film 3 having a thickness of 150Å is formed on the Si film 2 by thermal oxidation, and a gate 4 made of a polysilicon film having a thickness of 4000Å is formed. Figure 1 (B)
At, a 4000 Å thick CVD SiO ₂ film is deposited on the substrate,
Etch back by anisotropic etching to form side walls 5 on the side surfaces of the gate 4.

In FIG. 1C, the gate 4 and the side wall 5 are formed.
Using the as an implantation mask, arsenic ions (As ⁺ ) are implanted into the Si film 2 and activation annealing (heat treatment) is performed to form the source / drain 6.

In FIG. 1D, the radiation to be applied is
Irradiation is performed under the condition of 1E6 rad (Si) absorption using Co ⁶⁰ γ-rays. FIG. 3 shows subthreshold characteristics (drain voltage 5 V) before and after γ-ray irradiation of the n-channel FET formed according to the embodiment.
Shown in.

FIG. 3 is a diagram for explaining the effect of the embodiment.
This figure shows the rise characteristics of the drain current ID with respect to the gate voltage VG. (1) before γ-ray irradiation, (2) after γ-ray irradiation.

Before γ-ray irradiation (1), the subthreshold swing (VG / logID at the rising edge of ID) was 45E-3 mV / dec
It is extremely small due to ade and the bipolar effect.
After gamma irradiation (2), the subthreshold swing is 75E-
It has a normal value of 3 mV / decade, and no bipolar effect is seen.

[0028]

According to the present invention, in the junction of the SOI FET, the parasitic bipolar effect can be suppressed without requiring a special process as in the conventional example, and the element characteristics can be stabilized and the element can be highly reliable. did it.

[Brief description of drawings]

FIG. 1 is a sectional view illustrating an embodiment of the present invention.

FIG. 2 is a diagram showing a lateral electric field change due to a fixed positive charge.

FIG. 3 is a diagram for explaining the effect of the embodiment.

[Explanation of symbols]

1 SOI insulating film, underlying oxide film 2 SOI film, Si film for element formation 3 Gate insulating film, SiO ₂ film 4 Gate, polysilicon film, 5 side wall made of CVD SiO ₂ film 6 Source / drain region 7 Side wall Fixed positive charge

Claims (1)

[Claims] 1. A process for manufacturing an insulated gate field effect transistor (FET) formed on an element forming film (2) on an insulator (1), comprising a gate insulating film on the element forming film (2). Gate through (3)
An element formation step including the step of forming (4), then forming side walls (5) made of an insulating film on the side surface of the gate, and then forming source drains (6) in the element formation film on both sides of the gate. After completion, fixed positive charge in the side wall due to irradiation of radiation
A method of manufacturing a semiconductor device, comprising the step of generating (7).