KR0161840B1 - Method of manufacturing mosfet - Google Patents

Method of manufacturing mosfet Download PDF

Info

Publication number
KR0161840B1
KR0161840B1 KR1019900002998A KR900002998A KR0161840B1 KR 0161840 B1 KR0161840 B1 KR 0161840B1 KR 1019900002998 A KR1019900002998 A KR 1019900002998A KR 900002998 A KR900002998 A KR 900002998A KR 0161840 B1 KR0161840 B1 KR 0161840B1
Authority
KR
South Korea
Prior art keywords
gate electrode
oxide film
film
forming
substrate
Prior art date
Application number
KR1019900002998A
Other languages
Korean (ko)
Other versions
KR910017672A (en
Inventor
한석우
Original Assignee
구본준
엘지반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 구본준, 엘지반도체주식회사 filed Critical 구본준
Priority to KR1019900002998A priority Critical patent/KR0161840B1/en
Publication of KR910017672A publication Critical patent/KR910017672A/en
Application granted granted Critical
Publication of KR0161840B1 publication Critical patent/KR0161840B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

내용없음.None.

Description

모스패트 제조방법MOSFET manufacturing method

제1도는 종래 공정순서를 나타낸 단면도.1 is a cross-sectional view showing a conventional process sequence.

제2도는 본 발명의 공정순서를 나타낸 단면도.2 is a cross-sectional view showing the process sequence of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1 : 기판 2: 패드산화막1 substrate 2 pad oxide film

3 : 질화막 4 : 연산화막3: nitride film 4: computational film

5 : 게이트산화막 6 : 폴리실리콘5: gate oxide film 6: polysilicon

6,6a : 게이트전극 7 : 저온산화막6,6a: gate electrode 7: low temperature oxide film

7a : 측벽7a: sidewall

본 발명은 모스패트(MOSFET:Metal Oxide Semiconductor Field Effect Transistor)제조방법에 관한 것으로써, 소자의 특성을 개선시키는데 적당하도록 한 것이다.The present invention relates to a method for manufacturing a metal oxide semiconductor field effect transistor (MOSFET), which is suitable for improving the characteristics of the device.

종래의 모스패트 제조방법은 제1도의(a)에 도시된 바와 같이, 기판(1)위에 패드산화막(2)을 형성한 후, 패드산화막(2)상에 질화막(3)을 형성한다. 이후, 선택적으로 필드산화막(Fox:Field Oxide)를 형성한 후, 제1도의(b)에 도시된 바와 같이, 질화막(3)을 선택적으로 제거한 다음, 활성영역의 패드산화막(2)상에 게이트산화막(5)을 형성한다.In the conventional method for manufacturing a MOSFET, as illustrated in FIG. 1A, a pad oxide film 2 is formed on a substrate 1, and then a nitride film 3 is formed on the pad oxide film 2. Thereafter, after selectively forming a field oxide film (Fox: Field Oxide), as shown in FIG. The oxide film 5 is formed.

이후, 제1도(c)와 같이, 채널이온주입을 실시하고, 제1도(d)와 같이, 폴리실리콘을 증착한 후, 선택적으로 제거하여 게이트전극(6)을 형성한다. 이어, 제1도(e)에 도시한 바와 같이, 게이트전극(6)을 포함한 기판(1)전면에 저온산화막(7)을 증착한다.Thereafter, as shown in FIG. 1 (c), channel ion implantation is performed, and as shown in FIG. Next, as shown in FIG. 1E, the low temperature oxide film 7 is deposited on the entire surface of the substrate 1 including the gate electrode 6.

그리고 제1도(f)에 도시한 바와 같이, 저온산화막(7)을 에치백하여 게이트전극 양측면에 측벽(7a)을 형성한다.As shown in FIG. 1 (f), the low temperature oxide film 7 is etched back to form sidewalls 7a on both sides of the gate electrode.

상기 측벽(7a) 및 게이트전극(6)을 마스크로 이용한 식각공정으로 패드산화막(2)을 식각하여 기판(1)을 노출시킨다.The pad oxide film 2 is etched by using the sidewall 7a and the gate electrode 6 as a mask to expose the substrate 1.

이어, 제1도(g)에 도시한 바와 같이, 게이트전극(6) 및 측벽(7a)을 마스크로 이용한 이온주입을 통해 노출된 기판(1)표면내에 소오스 및 드레인영역(n+)을 형성한다.Subsequently, as shown in FIG. 1G, source and drain regions n + are formed in the exposed surface of the substrate 1 through ion implantation using the gate electrode 6 and the sidewall 7a as a mask. do.

그러나 이와 같은 종래 모스패트(MSOFET)에 있어서는 소자의 구조가 스케일 다운(scale down)됨에 따라 에벌런치(Avalanche)-브레이크다운(break down), 그리고 드레인 접합 부근에서 발생하는 열전자 효과(hot-electron effect), 기판전류(substrate current) 등의 문제가 발생하는 결점이 있었다.However, in such a conventional MOSFET, hot-electron effects occur near the avalanche-breakdown and drain junctions as the device structure scales down. ), A problem such as substrate current (substrate current) occurs.

여기서, 열전자(hot electron)란, 소자의 사이즈가 작아짐에 따라 채널의 길이가 짧아지게 되는데, 이로 인하여 소오스 및 드레인 사이의 간격이 줄어들게 되어 소오스에서 인가된 전자가 드레인접합의 채널방향의 가장자리(pinchoff)근처의 높은 전기장(high electric field)에 의하여 급속히 가속되어 발행하는 핫 일렉트론(hot electron)을 말한다.(참조 : Chenming Hu et al., hot-electron-induced MOSFET degradat-ion motal, monitor and improvement, IEEE transactions on electron devices, Vol. ED-32, No.2(February 1985), pp.375-385)In this case, the hot electrons are shortened as the size of the device decreases, thereby reducing the gap between the source and the drain. Hot electrons that are accelerated and issued by a nearby high electric field (see Chenming Hu et al., Hot-electron-induced MOSFET degradat-ion motal, monitor and improvement, IEEE transactions on electron devices, Vol. ED-32, No. 2 (February 1985), pp. 375-385)

상기 인용한 논문에 의하면 핫 일렉트론의 불안정성은 짧은 채널의 길이와 높은 인가전압에 기인한 드레인접합 근처에서의 매우 높은 전기장이 원인이다. 이렇게 발생한 핫캐리어(전자)는 게이트절연막으로 주입되어 다시 기판전류로 흐르게 된다.According to the paper cited above, the instability of hot electrons is due to the very high electric field near the drain junction due to the short channel length and high applied voltage. The hot carriers (electrons) thus generated are injected into the gate insulating film and flow back to the substrate current.

본 발명은 상기와 같은 종래의 결점을 해결하기 위해 안출한 것으로, 이를 첨부된 도면을 참조하여 설명하면 다음과 같다.The present invention has been made to solve the above-mentioned conventional drawbacks, when described with reference to the accompanying drawings as follows.

먼저, 제2도(a)에 도시한 바와 같이, 기판(1)위에 패드산화막(2)과 질화막(3)을 차례로 증착한다.First, as shown in FIG. 2A, the pad oxide film 2 and the nitride film 3 are sequentially deposited on the substrate 1.

이후, 선택적으로 필드산화막(Fox : Field Oxide)을 형성한 다음, 제2도(b)에 도시한 바와 같이, 게이트전극이 형성될 부분에만 질화막(3)을 남긴다.Thereafter, a field oxide film (Fox) is selectively formed, and as shown in FIG.

이어, 제2도(c)에 도시한 바와 같이, 패드산화막(2)위에 열산화막(thermal oxide)(d)을 형성하고, 제2도(d)에 도시한 바와 같이, 질화막(3)을 마스크로 이용하여 n-이온을 주입하여 LDD영역을 형성한다.Next, as shown in FIG. 2 (c), a thermal oxide film d is formed on the pad oxide film 2, and as shown in FIG. 2d, the nitride film 3 is formed. N - ions are implanted using a mask to form an LDD region.

이후, 제2도(d)에 도시한 바와 같이, 질화막(3)을 제거한 후, 질화막(3)이 제거된 부분의 기판(1)상에 게이트 절연막(5)을 형성한다.Thereafter, as shown in FIG. 2 (d), after the nitride film 3 is removed, the gate insulating film 5 is formed on the substrate 1 in the portion where the nitride film 3 is removed.

그리고 제2도(f)에 도시한 바와 같이, 게이트 절연막(5)을 포함한 기판(1)전면에 폴리실리콘(6)을 증착한다.As shown in FIG. 2 (f), polysilicon 6 is deposited on the entire surface of the substrate 1 including the gate insulating film 5.

이어, 폴리실리콘(6)을 선택적으로 제거하여 제2도(g)에 도시한 바와 같이, 게이트 절연막(5)상에 게이트전극(6a)을 형성한다.Next, the polysilicon 6 is selectively removed to form a gate electrode 6a on the gate insulating film 5, as shown in FIG.

그리고 게이트전극(6a)을 포함한 기판(1)전면에 저온산화막(7)을 증착한후, 에치백하여 제2도(h)에 도시한 바와 같이, 게이트전극(6a)의 양측면에 측벽(7a)을 형성한다.After depositing the low temperature oxide film 7 on the entire surface of the substrate 1 including the gate electrode 6a, the sidewalls 7a are formed on both sides of the gate electrode 6a, as shown in FIG. ).

이후, 제2도(i)에 도시한 바와 같이, 게이트전극(6a) 및 측벽(7a)을 마스크로 이용하여 n+이온주입을 통해 소오스 및 드레인영역을 형성한다.Thereafter, as shown in FIG. 2 (i), the source and drain regions are formed through n + ion implantation using the gate electrode 6a and the sidewall 7a as a mask.

이와 같이, 본 발명에 의하면, 소오스/드레인영역을 n-와 n+로 구성하여 LDD(Light Doped Drain)구조를 갖게 하므로 정션 커패시터를 줄일 수 있음은 물론, 종래의 공급전압(supply voltage)으로 인한 애벌런치-브레이크다운이나 열전자 효과의 문제를 해결할 수 있는 효과가 있다.As described above, according to the present invention, since the source / drain region is composed of n − and n + to have a light doped drain (LDD) structure, the junction capacitor can be reduced, and due to the conventional supply voltage. It can solve the problem of avalanche breakdown or hot electron effect.

Claims (1)

기판상에 패드산하막과 질화막을 차례로 증착하는 공정과, 상기 질화막을 패터닝하여 게이트전극영역을 정의하는 공정과, 상기 노출된 패드산화막상에 열산화막을 형성한 후, N-이온을 주입하고, 상기 질화막을 제거하는 공정과, 상기 질화막이 제거된 부분에 게이트절연막을 형성한 후, 상기 게이트절연막을 포함한 전면에 폴리실리콘층을 형성하는 공정과, 상기 폴리실리콘층을 패터닝하여 게이트전극을 형성하는 공정과, 상기 게이트전극 양측면에 측벽을 형성하는 공정과, 상기 게이트전극 및 측벽을 마스크로 N+이온을 주입하여 소오스 및 드레인을 형성하는 공정을 포함하여 이루어짐을 특징으로 하는 모스패트 제조방법.Depositing a pad underlayer and a nitride film on a substrate in turn, patterning the nitride film to define a gate electrode region, forming a thermal oxide film on the exposed pad oxide film, and then implanting N − ions; Removing the nitride film, forming a gate insulating film on the portion where the nitride film is removed, forming a polysilicon layer on the entire surface including the gate insulating film, and patterning the polysilicon layer to form a gate electrode. And forming a sidewall on both sides of the gate electrode, and forming a source and a drain by implanting N + ions with the gate electrode and the sidewall as a mask.
KR1019900002998A 1990-03-07 1990-03-07 Method of manufacturing mosfet KR0161840B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900002998A KR0161840B1 (en) 1990-03-07 1990-03-07 Method of manufacturing mosfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900002998A KR0161840B1 (en) 1990-03-07 1990-03-07 Method of manufacturing mosfet

Publications (2)

Publication Number Publication Date
KR910017672A KR910017672A (en) 1991-11-05
KR0161840B1 true KR0161840B1 (en) 1998-12-01

Family

ID=19296741

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900002998A KR0161840B1 (en) 1990-03-07 1990-03-07 Method of manufacturing mosfet

Country Status (1)

Country Link
KR (1) KR0161840B1 (en)

Also Published As

Publication number Publication date
KR910017672A (en) 1991-11-05

Similar Documents

Publication Publication Date Title
KR940006702B1 (en) Manufacturing method of mosfet
US5364807A (en) Method for fabricating LDD transitor utilizing halo implant
JPH0216020B2 (en)
JPH06204469A (en) Field-effect transistor and manufacture thereof
US6300207B1 (en) Depleted sidewall-poly LDD transistor
JP3057436B2 (en) Semiconductor device and manufacturing method thereof
JP3057439B2 (en) Method for manufacturing semiconductor device
KR0161840B1 (en) Method of manufacturing mosfet
JPH0548117A (en) Electrostatic induction semiconductor device
KR0183785B1 (en) Method of manufacturing mos transistor
JP3049496B2 (en) Method of manufacturing MOSFET
KR100287886B1 (en) Structure and method of fabrication for semiconductor device
KR100226770B1 (en) Manufacturing method of a semiconductor device
KR0167606B1 (en) Process of fabricating mos-transistor
KR0156157B1 (en) Method of fabricating semiconductor device
KR100480802B1 (en) Manufacturing method of semiconductor device
KR940002778B1 (en) Manufacturing method for ldd-strucutred tr
KR960008736B1 (en) Mosfet and the manufacturing method thereof
KR0147678B1 (en) Method for manufacturing semiconductor device
KR100252842B1 (en) Semiconductor device and its manufacture method
KR920000637B1 (en) Manufacturing method of mosfet its devices
KR940002780B1 (en) Structure and manufacturing for high voltage tr
KR0179168B1 (en) Method for fabricating semiconductor device
KR940005453B1 (en) Manufacturing method of semiconductor transistor
KR0172820B1 (en) Method of manufacturing semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090727

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee