JPH0562796B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing circuit, and more particularly to a digital signal processing circuit that performs a binary tree search.

[Conventional technology]

Conventionally, this type of digital signal processing has been performed by a digital signal processing processor, and a binary tree search program stored in memory such as ROM is used to perform transfers between various registers, access data memory, and perform four arithmetic operations. , branches, conditional branches, etc.

[Problem that the invention seeks to solve]

The conventional method of performing a binary tree search described above has the disadvantage that a large amount of memory must be allocated because the program for the binary tree search must be stored in memory. Ta.

Furthermore, because the control is performed by a program, conditional branches and unconditional branches are unavoidable, so there is a drawback that the processing time for performing a binary tree search is long.

[Means for solving problems]

The digital signal processing circuit of the present invention includes: a register for storing search target data of a binary tree search supplied from a data bus; a memory for storing a threshold value and a processing result of the binary tree search; a memory pointer that stores an address signal for memory reading; and a subtracter that mutually subtracts the threshold value read from the memory and the search target data supplied from the register, and supplies code data obtained as a result of this subtraction. and a memory address generator that generates the address signal to be supplied to the memory pointer after being supplied with a state transition signal indicating numerically a plurality of states instructing a predetermined operation, the output of the memory pointer, and the code data. and a bus driver that outputs the processing result read from the memory to the data bus.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

Register 11 is configured to receive data for performing a binary tree search from data bus 17, store it, and provide this data to subtracter 15.

The memory 12 stores the threshold value of the binary tree search and the processing result of the binary tree search, and these are specified by the address signal stored in the memory pointer 13 and read out and sent to the subtracter 15. , bus driver 16, respectively.

The memory pointer 13 receives and stores the address signal generated by the memory address generator 14, and provides it to the memory 12 as an address when reading the memory 12, and also provides it to the memory address generator 14 as its input. It is configured.

The memory address generator 14 inputs the address signal of the memory pointer 13, the sign output of the subtracter 15, and a state transition signal 18 that is generated every clock and indicates one of the four states M1 to M4, and generates an address. It is configured to generate a signal and provide it to the memory pointer 12.

The subtracter 15 inputs the threshold value from the memory 12 and the data from the register 11, and generates a memory address by subtracting the latter from the former and outputting the sign of the result as a positive (including 0; the same applies hereinafter) or a negative sign. It is configured to be applied to the input of the device 14.

The bus driver 16 is configured to input the processing result from the memory 12 and provide it to the data bus 17 as an output.

FIG. 2 is an operational flow diagram showing the operation of the embodiment of the present invention shown in FIG.

In FIG. 2, M1 to M indicate the states of the state transition signals 18, respectively represented by 00, 01, 10, and 11.
14 is added to or subtracted from the address signal from the memory pointer 13 according to the sign output from the subtracter 15. This state transition signal 18 is
This is a signal obtained by decoding the program code of a digital signal processor (DSP) (not shown) that controls the circuit of this embodiment, and is generated every system clock of the DSP. State M1 is to set the initial value of the address signal output from the memory address generator 14; state M2 is to add or subtract 2 to the value of the address signal in accordance with the sign;
State M3 adds or subtracts 1 to the value of the address signal in accordance with the sign, and state M4 subtracts 7 from the value of the address signal when the sign is negative or adds 8 when the sign is positive. Instruct. These states change in the order of M1, M2, M3, and M4, and a binary tree search is executed.

When the state of the state transition signal 18 is M1, the memory address generator 14 generates "0100" as the initial value address signal, which is the address signal of the memory pointer 1.
given to 3. The memory pointer 13 stores this and gives it to the memory 12 as the address signal 21 of the memory pointer.
2 reads out the contents of the memory designated by this address signal as a memory threshold value 22, and provides this threshold value T4 to the subtracter 15. On the other hand, register 1
1 reads out the stored data received from the data bus 17 to perform the binary tree search and supplies it to the subtracter 15. The subtracter 15 subtracts the threshold value T4 from the memory 12 from the data from the register 11, and outputs the sign of this subtraction result as a positive or negative sign output 23 to the memory address generator 14.
give to At this time, if the sign output 23 is positive, the process branches to the left, and if it is negative, the process branches to the right.

Here, the state of the state transition signal 18 changes from M1 to M2.
Transition to. When the state of the state transition signal 18 is M2, the memory address generator 14 inputs the sign output 23 from the subtracter 15 and the memory pointer address signal 21, and when the sign output 23 is negative, the memory "0010", which is obtained by subtracting 2 from the pointer address signal 21, is generated as an address signal, and if it is positive, the memory pointer address signal 21
"0110", which is the sum of 2 and 2, is generated as an address signal.

This address signal is given to the memory pointer 13, which stores it and gives it to the memory 12 as a memory pointer address signal.

The address signal of this memory pointer has a value of "0010" when the sign output 23 of the subtracter 15 is negative as a result of generation by the memory address generator 14, and branches to 24 when the sign output 23 is positive. has the value "0110" and branches to 27.

Thereafter, the same operations as those described above are repeated, including reading the threshold value 25 or 28 of the memory, subtracting from the data in the register 11, outputting the sign 26 or 29, and transitioning the state of the state transition signal 18 from M2 to M3. However, when the state transition signal 18 is M3, the memory address generator 14 subtracts 1 from the memory pointer address signal 24 or 27 if the sign output 26 or 29 is negative, and subtracts 1 if it is positive. The added value is generated as an address signal.

Next, when the state of the state transition signal 18 transitions from M3 to M4, the memory address generator 14 adds 7 to the address signal of the memory pointer if the sign output is negative, and adds 8 if the sign output is positive. Generated as an address signal. This address signal is stored in the memory pointer 13 and further stored in the memory 12.
The binary tree search processing results U0 to U7 stored in the memory 12 are read out in accordance with the value of this address signal. The processing result of this binary tree search U0~
U7 is U0<U1<...<U7, and is given to the data bus 17 as the output of the bus driver 16.

The processing result of the binary tree search on the data stored in the receiving register 11 from the data bus 17 as described above can be obtained on the data bus 17 as an output of the bus driver 16.

〔Effect of the invention〕

As explained above, by using the digital signal processing circuit of the present invention as a constituent circuit of a digital signal processing processor, there is an effect that the memory capacity of the program for binary tree search can be reduced. Another advantage is that the processing time for performing a binary tree search can be shortened.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention;
FIG. 2 is an operational flow diagram showing the operation of one embodiment of the present invention. 11...Register, 12...Memory, 13...
Memory pointer, 14...Memory address generator, 15...Subtractor, 16...Bus driver, 1
7...Data bus, 18...State transition signal.

Claims (1)

[Scope of Claims] 1. A register that stores search target data of a binary tree search supplied from a data bus, a memory that stores a threshold value and a processing result of the binary tree search, and the memory readout. a memory pointer that stores an address signal for the search; a subtracter that performs subtraction between the threshold value read from the memory and the search target data supplied from the register and supplies code data obtained as a result of this subtraction; , a memory address generator that receives supply of a state transition signal each numerically indicating a plurality of states instructing a predetermined operation, the output of the memory pointer, and the code data and generates the address signal to be supplied to the memory pointer; and a bus driver that outputs the processing result read from the memory to the data bus.