JPS5862748A - Microprogram sequencer - Google Patents

Abstract

PURPOSE:To decrease the execution time of subroutine jump and return instruction, by incorporating an instruction address register and a register file for return address storage of a subroutine. CONSTITUTION:A jump instruction CALL is interpreted in a machine cycle T6, the jump address C is selected at a multiplexer 1 and a register REG2 is selected as an instruction address register with a control circuit 5A. Further, in a machine cycle T7, the register REG2 is revised by +1 at an addition/subtraction circuit 2, and when a return instruction RTN is interpreted in a machine cycle 8, the selection of the internal register of a register file 4 is changed from the register REG2 to a register REG1 with the control circuit 5A, control is transferred from the subroutine C to the subroutine B and the processing from the address B+3 to the subroutine B is restarted.

Description

DETAILED DESCRIPTION OF THE INVENTION One invention relates to a microprogram sequencer.゛Conventionally, in an arithmetic control unit that is controlled by a microprogram, when reading out a valid micro-instruction from a control storage device in which a micro-program is stored, the micro-program sequence/return is performed as shown in Figure 1. It was getting worse. A microprogram sequencer usually has a multi-delete add/subtract circuit 2 and an instruction address register 3.
・Register file 4 ・Control circuit 5. ! ′.

That is, the multiplexer 1 inputs the input signal PO, the output signal of the register file 4 +1 yihDR, and the V output signal to the subroutine.
The output signal Minn is selected based on the control signal output from the control circuit 5), and the output signal Minn is input to the addition/subtraction circuit 2 and
1. The information is also input to a control storage device (not shown). In addition, the output signal MADD of the 2jII subtraction circuit 2
is input to the intra-strata address vy star 3 and also to the 1 register file 4, and the control circuit 5 controls the selection of each V star in the register file 4 from the signal ysmTJK. , and also generate control signals for read/write operations. When creating a jump address to a subroutine using such a microprogram sequencer, first, as shown in FIG.
A datum is stored in the memory address signal MADR, and its output signal PG is output as a memory address signal MADR to a control storage device (not shown) via a multiplexer 1.
AI) l is written to the V star RIG in the system file 4 based on the selection signal 181 B output from the control circuit 5 (-f syncycle A-TI) 6 In the next machine cycle, addition and subtraction are performed in 2. The contents of the instruction address register 3 are incremented by 1 by the circuit 2, and the contents of the V-star IIQIO are also updated. However,! In the thin cycle T3, the round microinstructions successively issued from the unillustrated control ffi storage device are jump instructions 0ALL, and the jump address 1 of the v jump instruction is output to the unillustrated control storage device, and the control circuit 5 outputs the jump instruction 0ALL. Register RIG 2 is selected from the system file 4. Thus, in machine cycle Te4, the contents of the instruction/address register 3 and the register RIG2 are updated by +1 by the addition/subtraction circuit 2, and subroutine B is processed.

Similar processing is repeated thereafter, and when the process moves to machine cycle T9, the ficro instruction read from address 1+4 of the control storage device (not shown) is a return instruction Ill''N, so the selection signal 1 output from the control circuit 5 is The output signal M+2 is selected by multiplexer 1 in machine cycle TIO.
is selected and output to a control storage device (not shown). In addition%
The underlined address information in FIG. 2 represents data used as address information in the first machine cycle. However, the conventional microderogram sequencer 'Torata VM'
Since the address register 3 is separated from the system file 4, the actual circuit design becomes complicated and the number of input signals to the multiplexer 10 increases. Further, FIG. 3 shows another conventional example. In the figure, the multiplexer 1゜addition/subtraction circuit 2, instruction address register 3, system file 4, and control circuit 5 are the same devices as described above (Figure t41), and the output signal of the addition/subtraction circuit 2 is sent via the instruction address register 3. The data is then transferred to the register file 4. When creating a subroutine address using such a register control device, as shown in FIG. , Mu+1, Mu+2 (machine cycle TI%T2), and when the V jump command 0AIII is detected in machine cycle T3, the destination address 1
is selected by the multiplexer 1 and outputted to a storage device (not shown), and an execution start address table +2 when returning from subroutine B is written to the register IIIGI in the system file 4.

Then, when processing moves to machine cycle T9, address B+4 is stored in the instruction address register 3 by the return instruction from subroutine C, and the microphone instruction read from this address is the return instruction RTN of subroutine 1. Then, the register RmG1 is selected by the selection signal ysmt+ output from the control circuit 5, and its output signal M+2 is output from the machine cycle TIO.
selected by multiplexer 1 at 5 (not shown). ! ] Output to the Q control storage device. The same process is repeated thereafter. However, in the microprogram sequencer shown in FIG. 3, the output signal of the adder/subtracter circuit 2 cannot be written directly to the register file 4, and it takes more time than necessary to update the memory address. There was a feeling that it was a waste of time. Therefore, the present invention has been made based on the above-mentioned drawbacks, and by integrating an instruction address register and a register file for holding a return address from a subroutine, execution of a subroutine jump and a return instruction can be executed in one machine. It is an object of the present invention to provide a microprogram sequencer that performs operations in cycles, reduces the number of circuit elements, and simplifies packaging design.

This invention will be explained below.

In FIG. 5 showing an embodiment of the present invention, a multiplexer 1, an addition/subtraction circuit 2, a register file 4, and a control circuit 5 are the same devices as described above. It is designed to be executed using a rising waveform or a falling waveform.

The operation of such a configuration will be explained with reference to the time chart of FIG. First, machine cycle TI
and T2, the selection signal 1F output from the control circuit 5
Register RIII in preregister file 4 by 81L
GO is used as an instruction address register, and its value is updated by +1 via the addition/subtraction circuit 2. Next, in machine cycle T3, the instruction code read from the control storage device (not shown) is the jump instruction 0ALL.
Therefore, the destination address (jump address) B is selected by the multiplexer 1 and output to the control i'':tii^ position (not shown), and the 1 selection signal 11
Register RKG 1 is selected by BmL, and the next address 1 day is written to register RIGI. Write L -C
, t/register IGI in machine cycles T4 and T5
73E instruction is used as an at 1/s register and inputs +1 to the adder/subtractor 2 every machine cycle.
It will be updated one by one. During this time, the contents of the register RIGO do not change. However, in machine cycle T6, the jump command (!ALL) is decoded again, and its jump address C is selected by the multiplexer l, and one circuit 5mnyo presis 1RBCk2 is selected. After this, in machine cycle T7, register Rna2 is incremented by +1 by addition/subtraction cycle #&2, and furthermore, in machine cycle T8, a return command RTN is given. Then, the selection of the internal registers of control circuit 5 and staff file 4 is from register IIKG2 to register 1llG.
1, control is transferred from subroutine C to subroutine 1, and processing of subroutine 1 is restarted from address B+3. Thus, in the machine cycle TIO, the return instruction RTN is decoded again, and the instruction address register is set to register R by the control circuit 5.
IG1 is changed to register R11iGO, and thereafter register R11t()O is updated by +1 by addition/subtraction circuit 2 (machine cycle 'flt, Te12). Thereafter, the address update process is repeatedly executed in the same manner.

As described above, according to the microprogram sequencer of the present invention, the next microinstruction to be executed is stored by integrating the instruction address register and the register file for holding the return address from the subroutine. It is possible to reduce the number of input signals to the multiplexer that selects and generates the address of the control storage device, eliminates the need for an instruction address register, and allows efficient use of the internal V-star in the system file. It is possible to reduce costs.

[Brief explanation of the drawing]

FIGS. 1 and 3 are block diagrams showing an example of the configuration of a conventional microprogram sequencer, FIGS. II2 and 4 are time charts for explaining its operation, and FIG. A block diagram showing one embodiment, and Fig. 6 is a time chart showing an example of its operation. 1...Multiplexer, 2-...Addition/subtraction circuit, 3...
・Register, 4... and system file, 5,5m...
・Control circuit. Kiyoshi Inomata, agent for Izuho

Claims (1)

[Claims] Execution of subroutine jump and return instructions in one
A microprogram sequencer that is executed in a machine cycle and is characterized by having a structure shown in (4) to ((')K below. (B) A multiplexer that receives at least the output of the above register file and the jump destination address signal of the subroutine as input, ゛(q) !Address update and register file control circuit that updates the multiplexer output by a predetermined value and supplies it to the register file.