JPH056274A - Data processor - Google Patents

Abstract

PURPOSE:To execute a high-speed processing without competing units even when a store instruction and the instruction of another load system are mixed. CONSTITUTION:A calculation data supplying means 31 is provided to read the contents of a register 83b in a register file 8 and to supply them to a computing element 7, and a store data supplying means 32 is provided to read the contents of a different register 83a in the register file 8 independently of the calculation data supplying means 31 and to supply the data to an operand access unit 5 as store data. By parallelly executing the operation processing of the computing element 7 and the write operation of the operand access unit 5 to a main storage device, the preprocessing of a store instruction is executed. Thus, the following store instruction can be simultaneously processed while executing the preceding load system instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to speeding up a store instruction in a pipeline type data processing device.

[0002]

2. Description of the Related Art Instructions handled by a data processing device are roughly classified into load type instructions and store type instructions. In a pipeline type data processing device, store instructions are
Due to various restrictions, it could not be processed at high speed as expected. For example, Japanese Patent Laid-Open No. 63-136138 relates to speeding up store-type instruction processing immediately after a load-type instruction.
Although -1032 and the like relate to speeding up of load-type instruction processing immediately after the store-type instruction, none of them consider the processing when the store-type instruction is sandwiched between the load-type instructions.

FIG. 15 is a block diagram showing an example of a conventional data processing apparatus. In the figure, 1 is a basic processing unit (BPU), 2 is a main memory unit (MMU), and 3 is an instruction reading unit (IPU). 4 is an instruction decode unit (D
EC), 5 is an operand access unit (OP
U) and 6 are arithmetic / execution units (also referred to as EXUs and arithmetic units). FIG. 16 is a more detailed block diagram of the EXU 6, in which 7 is an arithmetic unit (ALU) and 8 is a register file (REG). The load instructions are
Operand data and REG read from MMU2
The operation of inputting the contents of 8 is performed by the ALU 7, and the result is stored in the REG 8. On the other hand, store instructions are RE
The contents of G8 are read and written to MMU2.

Next, the operation will be described. For load-type instructions, the IPU 3 reads the instruction code from the MMU 2. The DEC 4 decodes the instruction code read by the IPU 3, generates various control signals, and controls the OPU 5 and the EXU 6. The OPU 5 reads out necessary operand data from the MMU 2 according to the control signal from the DEC 4. E
The XU 6 receives the data read by the OPU 5 and the contents of the REG 8 specified by the DEC 4 according to the instruction from the DEC 4.
It is processed by the ALU 7 and stored in the REG 8.

FIG. 17 is a pipeline processing configuration diagram showing a flow of the above-described series of processing. Stage 1 is an instruction read stage and corresponds to the processing of the IPU 3. Stage 2 is an instruction decoding stage and corresponds to the processing of DEC4. Stage 3 is an operand access stage and corresponds to the processing of OPU5. Stage 4
Is an operation / execution stage and corresponds to the processing of EXU6.

FIG. 18 is a pipeline transition diagram showing the flow of the series of processes described above. The horizontal axis represents time and the vertical axis represents the pipeline stage. L is a load instruction, A is an addition instruction, N is a logical product instruction, and all the instructions are load-related instructions. When such instructions are continuously executed, the flow of the pipeline is not disturbed and the processing proceeds smoothly.

FIG. 19 is a pipeline transition diagram showing processing of a store instruction. ST indicates a store instruction. The store instruction is a store-type instruction that directly writes the contents of REG8 to MMU2. The store instruction read by the IPU 3 in the cycle 2 is decoded by the DEC 4 in the cycle 3. After that, if it is a load type instruction, cycle 4 is stage 3 and operand access is performed by the OPU 5, but read of operand data is not necessary for the store instruction, so stage 3 is omitted and transition is made to stage 4. It is better to do it. But cycle 4
Has an L instruction in stage 4, and this L instruction is
Since it conflicts with the store instruction for outputting the store data to the OPU 5 via the, the store instruction is held in the DEC 4 up to cycle 4 for one extra cycle. In cycle 5, the store instruction transits to stage 4, and the store data is fetched from REG8. Next, the control of the store instruction is transferred to the OPU 5, and the data fetched from the REG 8 is written to the MMU 2 via the OPU 5. The add instruction following the store instruction was added to the stage 1 because the store instruction was held in the stage 2 for an extra cycle in the cycle 4.
Held for 2 cycles. Furthermore, the store instruction is OPU5.
In order to avoid a conflict between the cycle of using the add instruction and the cycle of the add instruction using the OPU5, the add instruction in the cycle 6 is held for one extra cycle in the stage 2 as well.

[0008]

Since the conventional data processing device is constructed as described above, since the operand access unit conflicts between the store instruction and another load type instruction, There is a problem that an extra cycle is required to avoid the contention and high-speed data processing cannot be performed.

The present invention has been made in order to solve the above problems, and even if a store instruction and another load instruction are mixed, there is no unit competition and a data processing device capable of high-speed processing. The purpose is to get.

[0010]

According to a first aspect of the present invention, there is provided a data processing device in which a store data output port of an operation execution unit and a content of two different registers in a register file are read independently from each other. A register file having two read ports (operation data supply means and store data supply means), one of the output ports of the register file being the data input of the arithmetic unit and the other being connected to one input of the multiplexer However, the output of the arithmetic unit is connected to the other input of the multiplexer.

According to the second aspect of the invention, in order to achieve the above-mentioned object, a storage device is provided between the basic processing device and the main storage device.
It is characterized in that a buffer is provided, whether a preceding process is performed or not is determined by a flag, and writing from the store buffer to the main storage device side is controlled by this flag.

In order to achieve the above-mentioned object, the third invention is provided with an invalid address register for temporarily holding a store address so that the contents of the cache can be invalidated by the invalid address register. It is characterized by executing the preceding processing.

[0013]

According to the first aspect of the present invention, the arithmetic data supplying means supplies the contents of the register in the register file to the arithmetic unit, and the store data supplying means stores the contents of the register different from the register. And the supply to the operand access unit can be performed in parallel.

According to the second invention, the store address and the store data by the store instruction are stored as
If the flag temporarily holds in the buffer and the flag indicates preceding processing, the main memory is rewritten after waiting for the normal end of the instruction preceding the store instruction.

Further, according to the third invention, even if the store has to be discarded due to the abnormal processing of the instruction preceding the store instruction, it corresponds to the store address held in the invalid address register. It is possible to invalidate the contents of the cache memory.

[0016]

【Example】

Example 1. An embodiment of the first invention will be described in detail below based on the embodiment shown in FIG. 1. In the figure, 8 is a register file (REG) having two output ports (81 and 82), and 9 is a register file. It is a multiplexer (MPX). Also, 81
Is a store instruction dedicated port, 82 is a calculation data dedicated port, 83 is a register group, and 71 is a calculator output port. Further, 31 is a store data supply means, and 32 is a calculation data supply means. Other parts are the same as in the conventional example.

Next, the operation will be described. The operation of the load type instruction is the same as that of the conventional data processing device. The store instruction is read by the IPU 3 and decoded by the DEC 4, and then the OPU 5 is used as it is to start a data write operation to the MMU 2. The write data is supplied to the OPU 5 from the store instruction dedicated port 81 of the REG 8.

FIG. 2 is a pipeline transition diagram of the data processing apparatus according to the present invention. Store instruction is stage 1,
After the stage 2, unlike the conventional case, the write operation to the MMU 2 can be started using the OPU 5 in the stage 3 without repeating the cycle. This is the conventional REG8
Since the data path from the OPU5 to the OPU5 was via the ALU7, it competed with the stage 4 of the load instruction, but in the present invention, it is possible because the data path 81 dedicated to the store instruction is provided. . That is, the arithmetic data supply means 32 reads the contents of the register 83b in the REG 8 and supplies the contents to the ALU 7, so that the cycle data E
The XU 6 can execute the L instruction, and at the same time, the store / data supply means 31 causes the other register 83 in the REG 8 to operate.
The contents of a are read and supplied as store data to the OPU5 via the MPX9.
Can execute ST instructions in parallel. As described above, the store instruction has completed all the processing up to cycle 4, and ends without shifting to stage 4. On the other hand, since the operand access for the subsequent add instruction does not conflict with the use of the OPU 5 by the store instruction, the add instruction can shift to stage 3 in cycle 5 and directly enter stage 4.

As described above, according to the first invention, the REG
Since the contents of 8 can be supplied to the OPU 5 without passing through the ALU 7, the write operation to the MMU 2 by the store instruction can be performed at the same time as the stage 4 of the preceding load-related instruction at the stage 3 of the store instruction. Further, it is possible to avoid the conflict with the use of the OPU 5 in the stage 3 of the other load type instruction following the store instruction, so that the flow of the pipeline is disturbed even if the load type instruction and the store instruction are mixed. It can be processed at high speed. Such parallel processing of the operand access of the store instruction at the same time as the execution stage of the preceding instruction will be referred to as "prestore processing".

In the above embodiment, two output ports are provided in the REG 8 to obtain a port for inputting the ALU 7 in the stage 4 and a port for inputting the OPU 5 in the stage 3, but as shown in FIG. RE dedicated to ALU7 input
REG2 (8b) dedicated to G1 (8a) and OPU5 input
Even if the same data is simultaneously written to both of the outputs of the ALU 7 by providing the same effect, the same operation and effect as in the above embodiment can be obtained.

Example 2. FIG. 4 is a pipeline transition diagram in the case where the data processing device according to the first embodiment is added to the configuration according to the prior art, where M is a multiplication instruction and ST is a store instruction. If the addition by the ALU 7 is repeated to realize the multiplication instruction, the stage 4 of the M instruction does not end in one cycle. Further, in some cases, for example, in cycle 7, addition detects an overflow, changes the subsequent instruction sequence, and executes exception processing due to overflow. On the other hand, ST has reached stage 3 in cycle 4 and has written to MMU 2. M
After the completion of the instruction, the exception processing must be performed without executing the ST instruction, but the MMU2 has already been rewritten by the ST instruction.

In order to avoid such a problem, the stage 3 of the ST instruction may be delayed until the final cycle of the M instruction. That is, as shown in FIG. 5, in the cycle 7 which is a cycle one step before the final step of the M instruction, ST
The instruction may be transited from stage 2 to stage 3. However, this method needs to be able to determine whether or not the cycle of the stage 4 currently being executed is the step immediately before the final step, but the determination is not always possible. If the judgment cannot be made, the ST instruction is transited from the stage 2 to the stage 3 in the final step of the M instruction as shown in FIG. Can not be improved.

FIG. 7 is a block diagram showing an embodiment of a data processing device according to the second invention. In FIG.
0 is a store buffer (STB), and other parts are the same as in the conventional example.

FIG. 8 is a pipeline transition diagram according to the present invention. In cycle 4, the store instruction is in stage 3,
Store data written to STB10, still MMU
Not written to 2. After that, in cycle 8, it is sufficient to write the contents of the STB 10 to the MMU 2 after it is confirmed that the M instruction is normally completed in the final step of the M instruction. At this time, the subsequent L instruction is OPU5 in cycle 5.
Is used to read data from MMU2, so it does not conflict with the write to MMU2 in cycle 8.

FIG. 9 is a more detailed block diagram of the STB 10, in which 11 is a store data register (S
DR), 12a and 12b are J / K type flips.
A flop, 13 is an input bus (DIN), 14 is an output bus (DOUT), 15 is a store instruction signal (WR) output by the BPU 1, and 16 is a restore signal (PRE) indicating that writing is performed in the stage 3. ), 17 is a reset signal (RST), and 18 is a restore execution instruction signal (E
XE) and 19 are memory write instruction signals (MW) for instructing writing to the MMU 2.

FIG. 10 is a timing chart showing a normal write operation. In cycle 5, the write operation is started by WR15, DIN13 is held in SDR11 and is output as DOUT14 in cycle 6 and thereafter.
WR15 is held by JK12a and MW19 is held in cycle 6
Becomes significant, and the write operation to the memory is performed.

FIG. 11 is a timing chart corresponding to FIG. In cycle 5, the write operation is started by WR15, DIN13 is held in SDR11 and is output as DOUT14 in cycle 6 and thereafter.
It is the same as FIG. However, in cycle 5, PRE1
6 is significant at the same time as WR15, so JK12
a is not set, but JK12b is set. In cycle 8, that is, by making the final step EXE18 of the M instruction significant, MW19 becomes significant, and JK12
Clear b. As described above, the write executed by the ST instruction at the stage 3 is held by the STB 10, the normal end of the M instruction is confirmed, and it is written to the MMU 2 at the cycle 8.

FIG. 12 is a timing chart corresponding to FIG. Since the M instruction detected an error in cycle 8, EXE18 is masked, and error processing is performed in cycle 9
Then, RST17 is made significant and JK12b is cleared.

As described above, according to the second invention, the writing by the restore processing is temporarily held in the STB 10, and the writing to the main storage device is executed after waiting for the normal end of the preceding instruction. , It is possible to avoid the problem that the main storage device is changed before the end of the preceding instruction.

In the above embodiment, one data register is used as the store buffer, but a store buffer composed of a plurality of sets of data registers and JK12a and JK12b also has the same operation and effect. Play.

Example 3. FIG. 13 shows an example of a configuration in which a cache memory is added. In the figure, 20 is a cache
It is a memory (CAM), and other parts are the same as in the conventional example. When the restore operation is performed with such a configuration,
Since the CAM 20 is between the STB 10 and the BPU 1, the CAM 20 may be rewritten before the end of the preceding instruction.

FIG. 14 is designed to solve the above problem. In the figure, 21 is an invalid address register (INV), and other parts are the same as in the conventional example.

As all the write processing performed by the BPU1, the address and data are held in the STB10, and the CA
When the copy of the contents of MMU2 corresponding to the address is held in M20, the copy is written in CAM20, and at the same time, the write address is also held in INV21. When discarding the write processing due to exception processing of the instruction preceding the store instruction, the RST17 signal is made significant and JK12b
And the write address held in INV21 is supplied to CAM20, and CAM20
It is only necessary to invalidate the copy of the contents of the MMU 2 corresponding to the address supplied from the NV 21.

As described above, according to the third invention, even if the store instruction must be discarded after the contents of the CAM 20 are rewritten by the restore processing of the store instruction, the address held in the INV 21 is stored. By using, it is possible to invalidate only the problematic address among the contents of CAM20, so that the contents of CAM20 can be saved as much as possible, and even if the restore process is performed, the hit rate of CAM20 can be processed with almost no drop. .

[0035]

As described above, according to the first aspect of the present invention, the operation data supplying means for supplying the operation data and the store data for supplying the store data for restoring the store instruction are provided.
Since the data supply means is provided, the arithmetic processing of the preceding instruction and the restore processing of the store instruction can be performed at the same time, and a faster data processing device can be obtained.

According to the second aspect of the invention, a store buffer is provided between the basic processing unit and the storage unit to temporarily hold the store data and the store address, and to end the instruction preceding the store instruction. Since the storage device is rewritten with the stored store data and the stored address after confirming that the prestore operation can be started without confirming the normal end of the preceding instruction.

According to the third aspect of the invention, in a data processing device having a cache memory, an invalid address register for holding a store address is provided, and when the restore process is canceled, Only the data previously written to the cache memory can be discarded depending on the contents of the invalid address register.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of an arithmetic / execution unit of a data processing device according to a first invention.

FIG. 2 is a pipeline transition diagram of one embodiment of the data processing device according to the first invention.

FIG. 3 is a block diagram showing a second configuration example of an execution / arithmetic unit of the data processing device according to the first invention.

FIG. 4 is a pipeline transition diagram of an embodiment of the data processing device according to the first invention.

FIG. 5 is a pipeline transition diagram of an embodiment of the data processing device according to the first invention.

FIG. 6 is a pipeline transition diagram of an embodiment of the data processing device according to the first invention.

FIG. 7 is a block diagram showing an embodiment of a data processing device according to the second invention.

FIG. 8 is a pipeline transition diagram of an embodiment of a data processing device according to the second invention.

FIG. 9 is a block diagram showing a more detailed configuration of a store buffer of a data processing device according to a second invention.

FIG. 10 is a timing chart of the data processing device according to the second invention.

FIG. 11 is a timing chart of the data processing device according to the second invention.

FIG. 12 is a timing chart of the data processing device according to the second invention.

FIG. 13 is a block diagram showing a configuration in which a cache memory is added to the data processing device according to the second invention.

FIG. 14 is a block diagram showing an embodiment of a data processing device according to the third invention.

FIG. 15 is a block diagram showing a conventional data processing device.

FIG. 16 is a block diagram showing a calculation / execution unit of a conventional data processing device.

FIG. 17 is a pipeline configuration diagram showing a pipeline configuration of a conventional data processing device.

FIG. 18 is a pipeline transition diagram of a conventional data processing device.

FIG. 19 is a pipeline transition diagram of a conventional data processing device.

[Explanation of symbols]

1 Basic processing device 2 main memory 3 Instruction read unit 4 instruction decode unit 5 operand access unit 6 Operation / execution unit 7 arithmetic unit 8 register file 9 Multiplexer 10 store buffer 11 Store data register 12 JK flip flops 13 input bus 14 output bus 15 Store instruction signal 16 Prestore instruction signal 17 Reset signal 18 Prestore instruction signal 19 Memory write instruction signal 20 cash memory 21 Invalid Address Register

Claims (3)

[Claims] 1. An arithmetic data supply means for reading out the contents of a register in a register file and supplying it to an arithmetic unit,
The operation data supply means independently reads the contents of different registers in the register file, and stores the read data as store data to a unit other than the operation device. A data processing device, wherein arithmetic processing and store data supply operation to a unit other than the arithmetic unit are performed in parallel. 2. A store buffer holding a store data and a store address generated by the store instruction, and another instruction in which the store data and the store address held in the store buffer precede the store instruction. By a flag indicating whether or not the preceding processing of the store instruction is executed before the end of the, and a signal indicating the normal processing of the preceding instruction preceding the store instruction when the flag indicates the preceding processing of the store instruction. When writing from the store buffer to the storage device, and when the flag does not indicate the preceding process, the writing from the store buffer to the storage device is performed regardless of the state of the signal indicating the normal end of the preceding instruction. Characteristic data processing device. 3. A cache memory for holding data,
When rewriting the contents of the cache memory by the preceding processing of the store instruction executed before the end of another instruction preceding the store instruction, an invalid address register for holding the store address of the data, and the cache memory After rewriting the contents of
A data processing device, comprising: invalidation means for discarding the contents of the memory by the address held in the invalid address register.