JPH0562382B2 - - Google Patents

Info

Publication number
JPH0562382B2
JPH0562382B2 JP60132120A JP13212085A JPH0562382B2 JP H0562382 B2 JPH0562382 B2 JP H0562382B2 JP 60132120 A JP60132120 A JP 60132120A JP 13212085 A JP13212085 A JP 13212085A JP H0562382 B2 JPH0562382 B2 JP H0562382B2
Authority
JP
Japan
Prior art keywords
data
channel
multiplexer
buffer
parcels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60132120A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6113359A (ja
Inventor
Robert James Halford
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cray Research LLC
Original Assignee
Cray Research LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cray Research LLC filed Critical Cray Research LLC
Publication of JPS6113359A publication Critical patent/JPS6113359A/ja
Publication of JPH0562382B2 publication Critical patent/JPH0562382B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
JP60132120A 1984-06-21 1985-06-19 周辺インターフエイス装置 Granted JPS6113359A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62278684A 1984-06-21 1984-06-21
US622786 1984-06-21

Publications (2)

Publication Number Publication Date
JPS6113359A JPS6113359A (ja) 1986-01-21
JPH0562382B2 true JPH0562382B2 (en, 2012) 1993-09-08

Family

ID=24495517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60132120A Granted JPS6113359A (ja) 1984-06-21 1985-06-19 周辺インターフエイス装置

Country Status (6)

Country Link
US (1) US4807121A (en, 2012)
EP (1) EP0165915B1 (en, 2012)
JP (1) JPS6113359A (en, 2012)
AT (1) ATE110479T1 (en, 2012)
CA (1) CA1228677A (en, 2012)
DE (1) DE3587910T2 (en, 2012)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU1671688A (en) * 1987-06-03 1988-12-08 Honeywell Bull Inc. Peripheral controller and adapter interface
EP0321555A1 (en) * 1987-07-01 1989-06-28 Unisys Corporation Fast-tag transfer improvement
JP2527458B2 (ja) * 1988-03-04 1996-08-21 富士通株式会社 デ―タ転送制御装置
US5283791A (en) * 1988-08-02 1994-02-01 Cray Research Systems, Inc. Error recovery method and apparatus for high performance disk drives
US5218689A (en) * 1988-08-16 1993-06-08 Cray Research, Inc. Single disk emulation interface for an array of asynchronously operating disk drives
JP2850431B2 (ja) 1988-09-05 1999-01-27 セイコーエプソン株式会社 記録媒体駆動装置及びこれを備えた電子機器
US5179667A (en) * 1988-09-14 1993-01-12 Silicon Graphics, Inc. Synchronized DRAM control apparatus using two different clock rates
US5193193A (en) * 1988-09-14 1993-03-09 Silicon Graphics, Inc. Bus control system for arbitrating requests with predetermined on/off time limitations
WO1990006550A1 (en) * 1988-12-08 1990-06-14 Cray Research, Inc. Single disk emulation for asynchronous disk array
EP0374764B1 (en) * 1988-12-19 2001-04-04 Nec Corporation Data transfer apparatus
DE58908047D1 (de) * 1989-04-25 1994-08-18 Siemens Ag Verfahren zur Synchronisation von Datenverarbeitungsanlagen.
US5347637A (en) * 1989-08-08 1994-09-13 Cray Research, Inc. Modular input/output system for supercomputers
US5303349A (en) * 1990-06-06 1994-04-12 Valitek, Inc. Interface for establishing a number of consecutive time frames of bidirectional command and data block communication between a Host's standard parallel port and a peripheral device
US5255372A (en) * 1990-08-31 1993-10-19 International Business Machines Corporation Apparatus for efficiently interconnecing channels of a multiprocessor system multiplexed via channel adapters
US5206952A (en) * 1990-09-12 1993-04-27 Cray Research, Inc. Fault tolerant networking architecture
US5276900A (en) * 1990-12-14 1994-01-04 Stream Computers Master connected to common bus providing synchronous, contiguous time periods having an instruction followed by data from different time period not immediately contiguous thereto
US5276684A (en) * 1991-07-22 1994-01-04 International Business Machines Corporation High performance I/O processor
GB2261537A (en) * 1991-11-14 1993-05-19 Techful International Limited Computer
US5388217A (en) * 1991-12-13 1995-02-07 Cray Research, Inc. Distributing system for multi-processor input and output using channel adapters
JPH07122865B2 (ja) * 1992-01-02 1995-12-25 インターナショナル・ビジネス・マシーンズ・コーポレイション バス動作の動作速度を制御するようにしたバス・インターフェースを有するコンピュータ・システム
US5640596A (en) * 1992-03-10 1997-06-17 Hitachi, Ltd. Input output control system for transferring control programs collectively as one transfer unit designated by plurality of input output requests to be executed
JP2587190B2 (ja) * 1992-09-04 1997-03-05 インターナショナル・ビジネス・マシーンズ・コーポレイション システム間チャネルページング機構
US5572691A (en) * 1993-04-21 1996-11-05 Gi Corporation Apparatus and method for providing multiple data streams from stored data using dual memory buffers
DE69431332T2 (de) * 1993-07-13 2003-01-02 Hewlett-Packard Co. (N.D.Ges.D.Staates Delaware), Palo Alto Kombinieren von Ton- und Fernsprech-Daten für einem Rechner
DE69300523T2 (de) * 1993-11-26 1996-03-14 Sgs Thomson Microelectronics Prozessorschnittstellenschaltung zum Austausch von seriellen digitalen Daten mit einem Peripheriegerät.
US5577213A (en) * 1994-06-03 1996-11-19 At&T Global Information Solutions Company Multi-device adapter card for computer
DE69520706T2 (de) 1994-06-03 2001-08-02 Hyundai Electronics America, Milpitas Herstellungsverfahren für einen elektrischen Vorrichtungs-Adapter
US5548791A (en) * 1994-07-25 1996-08-20 International Business Machines Corporation Input/output control system with plural channel paths to I/O devices
US5619731A (en) * 1994-09-23 1997-04-08 Ardent Teleproductions, Inc. Interactive music CD and data
US5495614A (en) * 1994-12-14 1996-02-27 International Business Machines Corporation Interface control process between using programs and shared hardware facilities
US5613162A (en) * 1995-01-04 1997-03-18 Ast Research, Inc. Method and apparatus for performing efficient direct memory access data transfers
DE69614291T2 (de) * 1995-03-17 2001-12-06 Lsi Logic Corp., Fort Collins (n+i) Ein/Ausgabekanälesteuerung, mit (n) Datenverwaltern, in einer homogenen Software-Programmierbetriebsumgebung
US5864712A (en) * 1995-03-17 1999-01-26 Lsi Logic Corporation Method and apparatus for controlling (N+I) I/O channels with (N) data managers in a homogenous software programmable environment
JP3518034B2 (ja) * 1995-03-30 2004-04-12 三菱電機株式会社 ソート方法並びにソート処理装置並びにデータ処理装置
WO1997006490A1 (en) * 1995-08-09 1997-02-20 Cirrus Logic, Inc. Parasitic personal computer interface
US5768624A (en) * 1996-02-28 1998-06-16 Opti Inc. Method and apparatus for employing ping-pong buffering with one level deep buffers for fast DRAM access
US6038621A (en) * 1996-11-04 2000-03-14 Hewlett-Packard Company Dynamic peripheral control of I/O buffers in peripherals with modular I/O
US6078968A (en) * 1997-10-03 2000-06-20 Vicom Systems, Inc. Platform-independent communications protocol supporting communications between a processor and subsystem controller based on identifying information
EP1691296A3 (en) * 1997-10-03 2010-03-17 Panasonic Corporation Memory interface device and memory address generation device
US6694381B1 (en) 1997-12-17 2004-02-17 Vicom Systems, Inc. Platform-independent communications protocol supporting communications between a processor and subsystem controller
DE19830625B4 (de) * 1998-07-09 2008-04-03 Robert Bosch Gmbh Digitale Schnittstelleneinheit
GB2362777B (en) * 2000-05-25 2002-05-08 3Com Corp System for detection of asynchronous packet rates and maintenance of maximum theoretical packet rate
US6874043B2 (en) * 2000-10-17 2005-03-29 Bridgeworks Ltd. Data buffer
GB2372115A (en) * 2001-02-08 2002-08-14 Mitel Semiconductor Ltd Direct memory access controller
US6779055B2 (en) 2001-06-20 2004-08-17 Freescale Semiconductor, Inc. First-in, first-out memory system having both simultaneous and alternating data access and method thereof
JP2003338200A (ja) * 2002-05-17 2003-11-28 Mitsubishi Electric Corp 半導体集積回路装置
US20050182863A1 (en) * 2004-02-18 2005-08-18 Arm Limited, Direct memory access control
CN101809934B (zh) * 2007-06-19 2014-07-02 北卡罗来纳科姆斯科普公司 用于使用管理端口电路的方法、系统和计算机程序产品
CN103984659B (zh) * 2014-05-15 2017-07-21 华为技术有限公司 分时使用串口的方法和装置

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3319230A (en) * 1956-09-26 1967-05-09 Ibm Data processing machine including program interrupt feature
US3812475A (en) * 1957-12-26 1974-05-21 Ibm Data synchronizer
US3336582A (en) * 1964-09-01 1967-08-15 Ibm Interlocked communication system
US3427592A (en) * 1964-11-12 1969-02-11 Ibm Data processing system
US3400372A (en) * 1965-02-16 1968-09-03 Ibm Terminal for a multi-data processing system
US3432813A (en) * 1966-04-19 1969-03-11 Ibm Apparatus for control of a plurality of peripheral devices
US3564502A (en) * 1968-01-15 1971-02-16 Ibm Channel position signaling method and means
US3582906A (en) * 1969-06-27 1971-06-01 Ibm High-speed dc interlocked communication system interface
US3623155A (en) * 1969-12-24 1971-11-23 Ibm Optimum apparatus and method for check bit generation and error detection, location and correction
US3688274A (en) * 1970-12-23 1972-08-29 Ibm Command retry control by peripheral devices
US3725864A (en) * 1971-03-03 1973-04-03 Ibm Input/output control
US3812473A (en) * 1972-11-24 1974-05-21 Ibm Storage system with conflict-free multiple simultaneous access
FR2260141A1 (en) * 1974-02-01 1975-08-29 Honeywell Bull Soc Ind Data transfer control for data processor - is used between periodic and non-periodic units employing buffer memory
US4313160A (en) * 1976-08-17 1982-01-26 Computer Automation, Inc. Distributed input/output controller system
US4115854A (en) * 1977-03-28 1978-09-19 International Business Machines Corporation Channel bus controller
US4300193A (en) * 1979-01-31 1981-11-10 Honeywell Information Systems Inc. Data processing system having data multiplex control apparatus
US4442504A (en) * 1981-03-09 1984-04-10 Allen-Bradley Company Modular programmable controller
US4495564A (en) * 1981-08-10 1985-01-22 International Business Machines Corporation Multi sub-channel adapter with single status/address register
US4460959A (en) * 1981-09-16 1984-07-17 Honeywell Information Systems Inc. Logic control system including cache memory for CPU-memory transfers
US4571671A (en) * 1983-05-13 1986-02-18 International Business Machines Corporation Data processor having multiple-buffer adapter between a system channel and an input/output bus

Also Published As

Publication number Publication date
EP0165915A2 (en) 1985-12-27
CA1228677A (en) 1987-10-27
DE3587910T2 (de) 1994-12-15
EP0165915A3 (en) 1988-12-07
DE3587910D1 (de) 1994-09-29
US4807121A (en) 1989-02-21
ATE110479T1 (de) 1994-09-15
JPS6113359A (ja) 1986-01-21
EP0165915B1 (en) 1994-08-24

Similar Documents

Publication Publication Date Title
JPH0562382B2 (en, 2012)
EP0125561B1 (en) Data-processing system having multi-buffer adapter between a system channel and an input/output bus
US4860244A (en) Buffer system for input/output portion of digital data processing system
US5315708A (en) Method and apparatus for transferring data through a staging memory
US5301279A (en) Apparatus for conditioning priority arbitration
US4542457A (en) Burst mode data block transfer system
KR0163234B1 (ko) 데이타 스트리밍 메카니즘, 스트리밍 장치 어댑터, 컴퓨터 시스템 및 데이타 처리 시스템
EP0082683B1 (en) Computer memory system
US4868742A (en) Input/output bus for system which generates a new header parcel when an interrupted data block transfer between a computer and peripherals is resumed
US4400778A (en) Large-volume, high-speed data processor
US4607348A (en) Transfer rate control system from tape peripheral to buffer memory of peripheral controller
US4602331A (en) Magnetic tape-data link processor providing automatic data transfer
JPH06266650A (ja) データを転送する方法と装置及びデータ転送をインタリーブする装置
JPH03156562A (ja) バス間アダプタ
JPS62221057A (ja) ポインタアドレスを発生するための装置および方法
EP0133015B1 (en) Data transfer system
JPH06103213A (ja) 入出力装置
US4616337A (en) Automatic read system for peripheral-controller
US7035956B2 (en) Transmission control circuit, reception control circuit, communications control circuit, and communications control unit
US5613141A (en) Data storage subsystem having dedicated links connecting a host adapter, controller and direct access storage devices
JPH0776950B2 (ja) データ処理方法及び装置
US4771378A (en) Electrical interface system
KR100638378B1 (ko) 디스크 제어장치의 메모리 구조에 대한 시스템 및 방법
NO152918B (no) Databehandlingssystem
KR920007949B1 (ko) 컴퓨터 주변장치 제어기

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term