JPH056225A - Digital rotating phase servo device - Google Patents

Digital rotating phase servo device

Info

Publication number
JPH056225A
JPH056225A JP3148685A JP14868591A JPH056225A JP H056225 A JPH056225 A JP H056225A JP 3148685 A JP3148685 A JP 3148685A JP 14868591 A JP14868591 A JP 14868591A JP H056225 A JPH056225 A JP H056225A
Authority
JP
Japan
Prior art keywords
order lag
order
lead
filters
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3148685A
Other languages
Japanese (ja)
Inventor
Junichiro Tabuchi
潤一郎 田渕
Yukio Tamashima
征雄 玉嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP3148685A priority Critical patent/JPH056225A/en
Publication of JPH056225A publication Critical patent/JPH056225A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a high-order lag-lend tipe filter used as a phase compensating filter with simple configuration by serially connecting and inserting plural first-order lag-lead filters in a phase servo loop. CONSTITUTION:First-order lag-lend type filters 31 and 32 are serially connected and inserted in the phase servo loop in place of second-order lag-lead filters. In order to constitute this connection with the software of a microcomputer, it is executed twice with the first-order lag-lead filters 31 and 32 as sub routines. In order to obtaining a desired phase compensating characteristic, in the case of executing the sub routine twice, coefficients K6-K8 of coefficient multipliers 43-45 can be made equal or different in the two times of execution. Delay time is made equal for delay equipments 41 and 42 in the two times of execution for executing the same sub routine, and the poles of the two first-order lag-lead filters are made completely coincident. Thus, neither oscillation due to deterioration in servo characteristic nor deterioration in performance of the high-order lag-lead filter is caused.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、8ミリビデオテープレ
コーダ(以下「8ミリVTR」と略す。)のシリンダモ
ータやキャプスタンモータ等の回転位相制御に用いられ
るデジタル回転位相サーボ装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital rotary phase servo device used for rotary phase control of a cylinder motor or a capstan motor of an 8 mm video tape recorder (hereinafter abbreviated as "8 mm VTR").

【0002】[0002]

【従来の技術】8ミリVTRのキャプスタンモータのデ
ジタルサーボ装置は、一般に図3に示す機能ブロック図
のようになる。
2. Description of the Related Art A digital servo device for an 8 mm VTR capstan motor generally has a functional block diagram shown in FIG.

【0003】図において、1はキャプスタンモータであ
り、該モータの回転に応じて発生するFG信号はアンプ
2を通り速度エラー信号作成装置3と第1の位相エラー
信号作成装置4に入力される。速度エラー信号作成装置
3では、FG信号の周期を計測し速度エラー信号を作成
する。第1の位相エラー信号作成装置4では、FG信号
と基準位相信号との位相差を計測し位相エラー信号を作
成する。速度エラー信号と位相エラー信号は加算器5に
て加算され、位相補償フィルタとして設けられている2
次のラグリードフィルタ6を通り、低域でのサーボゲイ
ンを高くし、キャプスタンモータ1へ加えられ駆動制御
する。以上は8ミリVTRが記録モードの場合について
説明した。再生モードではスイッチ7を端子7aから端
子7bに切換え、8ミリVTRの規格である4周波パイ
ロット方式を用い、第2の位相エラー信号作成装置8に
より位相エラー信号が作成される。なお、図3に示され
た速度エラー信号作成装置3、第1の位相エラー信号作
成装置4、加算器5、2次のラグリードフィルタ6、ス
イッチ7、第2の位相エラー信号作成装置8は、実際に
はマイコンのソフトウエアで構成されている。
In the figure, reference numeral 1 denotes a capstan motor, and an FG signal generated in response to the rotation of the motor passes through an amplifier 2 and is inputted to a speed error signal producing device 3 and a first phase error signal producing device 4. .. The speed error signal creating device 3 measures the cycle of the FG signal and creates a speed error signal. The first phase error signal creation device 4 creates a phase error signal by measuring the phase difference between the FG signal and the reference phase signal. The speed error signal and the phase error signal are added by the adder 5 and provided as a phase compensation filter 2
After passing through the lag lead filter 6, the servo gain in the low frequency band is increased, and the capstan motor 1 is driven and controlled. The above has described the case where the 8 mm VTR is in the recording mode. In the reproduction mode, the switch 7 is switched from the terminal 7a to the terminal 7b, and the phase error signal is generated by the second phase error signal generating device 8 using the 4-frequency pilot method which is the standard of 8 mm VTR. The speed error signal generating device 3, the first phase error signal generating device 4, the adder 5, the secondary lag lead filter 6, the switch 7, and the second phase error signal generating device 8 shown in FIG. Actually, it is composed of microcomputer software.

【0004】次に、2次のラグリードフィルタについて
説明する。図4は2次のラグリードフィルタの一例を示
す機能ブロック図であり、11、12、13、14はデ
ジタルサーボの1サンプリング時間、信号を遅延する遅
延器、15、16、17、18、19は各々K1、K
2、K3、K4、K5という値を信号に乗算する係数乗
算器、20、21は加算器である。なお、図示した2次
のラグリードフィルタの差分方程式は、
Next, the secondary lag lead filter will be described. FIG. 4 is a functional block diagram showing an example of a second-order lag lead filter. Reference numerals 11, 12, 13, and 14 denote delay times for delaying a signal for one sampling time of digital servo and 15, 16, 17, 18, and 19. Are K1 and K respectively
Coefficient multipliers for multiplying the signals by the values 2, K3, K4, K5, and 20 and 21 are adders. The difference equation of the second-order lag-lead filter shown in the figure is

【0005】[0005]

【数1】 [Equation 1]

【0006】となる。[0006]

【0007】[0007]

【発明が解決しようとする課題】しかしながら、高次の
ラグリードフィルタをマイコンのソフトウエアで構成す
る場合、パラメータが増し複雑な計算が必要となる。よ
ってプログラムが大きくなり、プログラム記憶用メモリ
を有効活用できないという課題があった。
However, when a high-order lag lead filter is constructed by software of a microcomputer, the parameters increase and complicated calculation is required. Therefore, there is a problem that the program becomes large and the memory for storing the program cannot be effectively used.

【0008】[0008]

【課題を解決するための手段】よって、本発明は上記課
題を解決するために、デジタル回転位相サーボ装置の位
相サーボループ内に、1次のラグリードフィルタを複数
個直列接続して挿入した。
According to the present invention, in order to solve the above-mentioned problems, a plurality of primary lag lead filters are connected in series and inserted in a phase servo loop of a digital rotary phase servo apparatus.

【0009】[0009]

【作用】1次のラグリードフィルタを複数個直列接続す
ることにより、高次のラグリードフィルタをとして作用
する。
Operation A plurality of first-order lag lead filters are connected in series to function as a higher-order lag lead filter.

【0010】[0010]

【実施例】以下図面に従い本発明の実施例について説明
する。図1は本発明の一実施例を示す機能ブロック図で
あり、従来技術を示した図3と同一構成要素には同一符
号を付し説明は省略する。図3と異なる点は、2次のラ
グリードフィルタに替えて2つの1次のラグリードフィ
ルタ31、32を直列接続し、位相サーボループ内に挿
入したことである。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram showing an embodiment of the present invention. The same components as those of FIG. The difference from FIG. 3 is that two primary lag lead filters 31 and 32 are connected in series instead of the secondary lag lead filter and are inserted in the phase servo loop.

【0011】図2に1次のラグリードフィルタの一例を
機能ブロック図で示す。図4と同様、41、42はデジ
タルサーボの1サンプリング時間、信号を遅延する遅延
器、43、44、45は各々K6、K7、K8、という
値を信号に乗算する係数乗算器、46、47は加算器で
ある。差分方程式は、
FIG. 2 is a functional block diagram showing an example of the primary lag-lead filter. As in FIG. 4, 41 and 42 are digital servo one sampling time, delay devices for delaying signals, 43, 44 and 45 are coefficient multipliers for multiplying signals by K6, K7, and K8, and 46 and 47, respectively. Is an adder. The difference equation is

【0012】[0012]

【数2】 [Equation 2]

【0013】となる。[0013]

【0014】1次のラグリードフィルタを2個直列接続
することをマイコンのソフトウエアで構成するには、1
次のラグリードフィルタをサブルーチンとし、該サブル
ーチンを2回実行すればよい。所望の位相補償特性を得
るためには係数乗算器43、44、45の係数K6、K
7、K8は、サブルーチンを2回実行するに際し2回共
同じ値としてもよく、1回目と2回目とで異なる値とし
てもよい。なお、遅延器41、42の遅延時間は同一サ
ブルーチンを実行させるため、1回目と2回目とで等し
い。すなわち2つの1次のラグリードフィルタの極は完
全に一致している。よって、サーボ特性が悪化して発振
したり、高次のラグリードフィルタの特性が出ないとい
うことはない。また、3次、4次とさらに高次のラグリ
ードフィルタを得るには、該サブルーチンを3回、4回
と実行すればよく、複雑なプログラムを構成する必要が
ない。
To configure the serial connection of two primary lag lead filters with the software of the microcomputer, 1
The next lag lead filter may be used as a subroutine, and the subroutine may be executed twice. In order to obtain a desired phase compensation characteristic, the coefficients K6, K of the coefficient multipliers 43, 44, 45
7, K8 may have the same value twice when the subroutine is executed twice, or may have different values between the first time and the second time. The delay times of the delay devices 41 and 42 are the same in the first and second times because the same subroutine is executed. That is, the poles of the two first-order lag-lead filters are exactly the same. Therefore, the servo characteristics are not deteriorated and oscillate, and the characteristics of the high-order lag lead filter are not lost. Further, in order to obtain third-order, fourth-order, and higher-order lag-lead filters, the subroutine may be executed three times and four times, and it is not necessary to configure a complicated program.

【0015】[0015]

【発明の効果】本発明によれば、パラメータが増す複雑
な計算を必要としない高次のラグリードフィルタをマイ
コンのソフトウエアで構成することができる。よって、
プログラム記憶用メモリを有効活用することができ、そ
の効果は大である。
According to the present invention, a high-order lag-lead filter which does not require complicated calculation in which parameters increase can be constructed by software of a microcomputer. Therefore,
The memory for program storage can be effectively used, and the effect is great.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示した機能ブロック図であ
る。
FIG. 1 is a functional block diagram showing an embodiment of the present invention.

【図2】図1に示す実施例の要部を示した機能ブロック
図である。
FIG. 2 is a functional block diagram showing a main part of the embodiment shown in FIG.

【図3】従来技術を示した機能ブロック図である。FIG. 3 is a functional block diagram showing a conventional technique.

【図4】図3に示す従来技術の要部を示した機能ブロッ
ク図である。
FIG. 4 is a functional block diagram showing a main part of the conventional technique shown in FIG.

【符号の説明】[Explanation of symbols]

1 …キャプスタンモータ 3 …第1の位相エラー信号作成装置 31、32 …1次のラグリードフィルタ 1 ... Capstan motor 3 ... 1st phase error signal preparation apparatus 31, 32 ... 1st-order lag lead filter

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 G11B 15/467 Q 8110−5D ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location G11B 15/467 Q 8110-5D

Claims (1)

【特許請求の範囲】 【請求項1】 位相サーボループ内に1次のラグリード
フィルタを複数個直列接続して挿入したことを特徴とす
るデジタル回転位相サーボ装置。
Claim: What is claimed is: 1. A digital rotary phase servo apparatus comprising a plurality of first-order lag lead filters connected in series in a phase servo loop.
JP3148685A 1991-06-20 1991-06-20 Digital rotating phase servo device Pending JPH056225A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3148685A JPH056225A (en) 1991-06-20 1991-06-20 Digital rotating phase servo device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3148685A JPH056225A (en) 1991-06-20 1991-06-20 Digital rotating phase servo device

Publications (1)

Publication Number Publication Date
JPH056225A true JPH056225A (en) 1993-01-14

Family

ID=15458312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3148685A Pending JPH056225A (en) 1991-06-20 1991-06-20 Digital rotating phase servo device

Country Status (1)

Country Link
JP (1) JPH056225A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5984790A (en) * 1997-08-13 1999-11-16 Nsk Ltd. Universal joint

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60208113A (en) * 1984-03-31 1985-10-19 Hitachi Ltd Digital filter
JPS61143822A (en) * 1984-12-18 1986-07-01 Hitachi Ltd Digital control device
JPS6488959A (en) * 1987-09-30 1989-04-03 Toshiba Corp Clv servo circuit for optical disk reproducing device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60208113A (en) * 1984-03-31 1985-10-19 Hitachi Ltd Digital filter
JPS61143822A (en) * 1984-12-18 1986-07-01 Hitachi Ltd Digital control device
JPS6488959A (en) * 1987-09-30 1989-04-03 Toshiba Corp Clv servo circuit for optical disk reproducing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5984790A (en) * 1997-08-13 1999-11-16 Nsk Ltd. Universal joint

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