JPS60208113A - Digital filter - Google Patents

Abstract

PURPOSE:To obtain a digital filter having a lag/lead filter characteristic where a polygonal point frequency is sufficiently low by connecting a multiplier and a digital LPF in parallel and adding the outputs so as to decrease the number of elements. CONSTITUTION:An input digital signal X is inputted to the multiplier 11 of a coefficient alpha, a prescribed gain characteristic causing a phase lead is provided, the input digital signal X is inputted to the digital LPF12 formed with a feedback path which has a unit delay element 16, multipliers 14, 15 and at least the unit delay element 16, the signal is subjected to moving means processing sequentially, the phase delay characteristic is provided, they are added by an adder 10 so as to attain the linear lag/lead filter characteristic. The transfer function G(Z) of the filter is represented by alpha+(1-beta)/(1-betaZ<-1>).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a digital filter having low-pass characteristics, and particularly to a digital filter suitable for use in a phase compensation circuit of a phase control system.

[Background of the Invention] Conventionally, a -order lag lead filter (10g-1gα
A low-pass filter with an analog configuration having the following characteristics is used.

FIG. 1 (α) is a block diagram showing an example of such a filter (-order lag lead filter), in which 1.2 is a resistor, 3 is a capacitor, X is an input signal, and Y is an output signal.

The transfer function G(8) of such a filter is expressed as follows, where the resistance values of the resistors 1 and 2 are l't+ and R2, respectively, and the capacitance cap of the capacitor 6 is C.

However, 'I+ -0(R+ +12)+1t, w
, □R.

The frequency characteristics of this filter are as shown in FIG. 1(b), with a corner frequency of 11. fH is expressed as the modulus 0 /L-1/2π'I"I, fH-1/2πT2 Incidentally, in recent years, the use of integrated circuits (ICs) in electronic circuits has progressed, and there is a demand for ICs for filters as well. However, when converting the above-mentioned analog filter into an IC, it is necessary to attach the capacitor 6 externally, and a means for starting the capacitor 3 is provided, which makes the IC package difficult. The number of input/output pins increases, resulting in a circuit configuration that is not suitable for IC implementation.Furthermore, this filter suffers from deterioration in characteristics due to leakage current from the capacitor 6 and deterioration of the capacitor 6.

In order to solve this problem, a low-pass filter having a digital configuration, that is, a digital filter having lag-lead filter characteristics, has been proposed.

FIG. 2 is a block diagram showing an example of such a conventional digital filter, in which 4 and 5 are adders, 6 and 7°8 are multipliers,
9 is a unit delay element.

This digital filter has a cyclic filter configuration having a feedback loop and a feedforward loop, and if the coefficients by which the input signals of the multipliers 6, 7 and 8 are multiplied are α, b, and c, respectively, 2 Transmission amount on plane @
As is generally well known, G (z) is expressed by the following formula.

Now, in order for the characteristics of this digital filter to be equivalent to the characteristics of the low-pass filter shown in Figure 1, equation (2) must be changed to equation (
1) must match isometrically.

Therefore, when the coefficients α, b, and c are calculated using the difference approximation method, which is a method of two-conversion, they are each expressed as a modulus.

By setting the coefficients α, b, and c in this manner, the digital filter shown in FIG. 2 can have characteristics equivalent to those of the analog configuration filter shown in FIG. 1.

When integrated into an IC, this digital filter does not require any special input/output pins, and its characteristics do not deteriorate. However, when actually forming this digital filter, a register is required after the adder 4.5 and multiplier 6.7.8, and furthermore, the register after the multiplier 6, 7.8 is For example, if the input data X is 10 bits, it is necessary to process data of 18 or more pits each, and the register becomes large. Also, a multiplier 6°7.
Since the coefficients α, b, and c of 8 must be set with very high precision, an 8 to 10-bit ROM (read-only memory) is used to store these coefficients α, b, and c. I need.

As described above, the cyclic digital filter requires a large number of registers, especially large registers and memories, and therefore has no choice but to have an enormous number of elements.

Furthermore, as a method for realizing a digital filter having lag-lead filter characteristics, a method using a moving average method is also known. This method averages a plurality of sample data, and sequentially shifts the sample data to be averaged one sampling point at a time. However, in the digital filter using the moving average method, the corner frequency m (cutoff frequency) f depends on the number of sample data to be averaged, and the corner frequency m (cutoff frequency) f depends on the number of sample data to be averaged. In order to lower the value of 6, we must increase its number.

Therefore, when using a digital filter for the phase compensation circuit of the phase control system of a video tape recorder, the corner frequency kfc is normally set for the sampling frequency Is! ,/1
The value must be set to about 00, but the number of sample data to be averaged for this purpose is about 44. Therefore, about 44 registers for holding these sample data and 44 addition operations are required, and the digital filter has a very large number of elements and becomes large-scale.

As described above, conventional digital filters having lag-lead filter characteristics require a large number of elements, and in particular, their use in the phase compensation circuit of the phase control system of a video tape recorder is impractical in terms of cost.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above, reduce the number of elements, and provide a digital filter having lag-lead filter characteristics with a sufficiently low corner frequency.

[Structure of the invention]

In order to achieve this object, the present invention provides a constant gain circuit including a multiplier, a digital TFT including a multiplier and a unit delay element, and a feedback loop including the unit delay element.
, PF are connected in parallel, and the digital LPF
is a sequential moving average of input sample data and has low-pass filter characteristics, and is characterized in that the constant gain circuit and the digital LPF provide first-order lag-lead filter characteristics.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 6 is a block diagram showing an embodiment of the digital filter according to the present invention, in which 10 is an adder, 11 is a multiplier,
12 is a digital LPF (low pass filter), 13 is an adder, 14.15 is a multiplier, and 16 is a unit delay element.

In this embodiment, a multiplier 11 and a digital LPF'12 are arranged in parallel, and their outputs are added by an adder'a10 to obtain the first
An attempt is made to obtain the lag lead filter characteristics shown in Figure (6). That is, the digital LPP 12 is given a broken line characteristic (phase delay characteristic) shown by the broken line in FIG.
The digital LP 112 and the multiplier 11 have a constant gain characteristic (to cause a phase lead) shown by the dashed line, and the overall characteristics of the digital LP 112 and the multiplier 11 are the same as shown by the solid line in FIG. 1(b). .

This point will be explained below.

First, looking at equation (2) above, this equation can be transformed as follows.

Here, a---100 Then, equation (4) becomes as follows.

moreover, Then, equation (5) can be expressed as follows.

This equation (7) expresses the characteristics shown in Figure 1(b) when each coefficient α and β satisfy equation (6) and each coefficient α and C are expressed by equation (3). be. And this (7)
The formula is a circuit with a transfer function α and a transfer function (1-β)/(1-
It shows the transfer function of a circuit in which the circuits β2-9 are connected in parallel.

In this embodiment, the coefficient of the multiplier 11, which is one circuit connected in parallel with each other, is the above α, and the transfer function of the digital LPF 12, which is the other circuit, is (1-β)/(1-βg-1
), so that the transfer function of equation (7) can be obtained as a whole.In other words, in FIG. The output of this digital filter is X and Y, and the output of digital LPF 12 is W.
1. If the output of the multiplier 14 is ■, then Y-αX+W (8) V-β (X+g-'V), therefore, the transfer function G of the digital LPF 12 is
(z) becomes, and by substituting equation (9) into equation (8), the transfer function G (g) of the entire digital filter becomes, which agrees with equation (7).

By the way, in the tooJ formula, if we set β-1/2,
G'(z)---7-21 This expression is equivalent to a series, and in general, the 00 expression is equivalent to the series (1-β)Σz-s n·0. From this, equation (9) is -(1-β)[
1+βg-1+βz +・tenffrLz−'ten・=)
Since it is represented by
12 is 1 times the unit delay time T (however, n = 1.2
,3. ...) to the delayed sample data (1-β)β
This means that a weight of 7 is applied and a moving average is sequentially applied to an infinite number of sample data.

Figure 5 shows the digital L P of Figure 6 when β is a variable.
This shows the characteristics of F12, and in this case, sampling zero-order hold is applied. In addition, in FIG. 5, the sampling frequency is set to 7. (1, /'I',),
The horizontal axis represents Vf (-7-T,). The drop in gain is due to the sampling frequency! It occurs at an integer multiple of 8.

As is clear from FIG. 5, by changing the coefficient β, the digital 1. , cutoff frequency of PF12! .

can be changed.

FIG. 6(α) shows different values of coefficient β1. For β2,
This shows the overall characteristics of the embodiment of FIG. 3 expressed by equation (11). In this case as well, sampling zero-order hold is applied.

In the figure, curves A' and B' are the characteristics of the digital LPF 12 in FIG. 6 when β is a peak and β2, respectively, and β1
1/8. β2 was set to 1/4. On the other hand, curve A
, B are the characteristics of the entire digital filter shown in FIG. 6 when β is βhβ2, and in the area P, the influence of the coefficient α appears and a lag-lead filter characteristic is obtained. The high frequency gale can be changed by appropriately selecting each coefficient.

In addition, w6 (b) is difficult to understand the lag lead filter characteristics due to the drop in gain at sampling frequency 18 in the same figure (α), so the song MA in Fig. 6 (α),
Assuming that there is no drop in gain for B,
FIG. 3 schematically shows the overall characteristics of FIG.

Now, in this embodiment, the coefficients α and β can be set to arbitrary values in order to obtain predetermined characteristics. Therefore, by setting the coefficient α of the multiplier 11 to α-1/2m, the multiplier 11 can be simply used as a register. #I can. In practice, the input sample data string may be shifted using hard logic (wiring) and then supplied to the adder 10. Also, the multiplier 14
can also be configured with only a shift register by setting the coefficient β to β-1/2".Furthermore, since the coefficient of the multiplier 15 is (1-β)/β-2-1, , the multiplier 15 can be formed by a shift register and a subtracter.

As described above, this embodiment can be configured with a shift register, an adder, a subtracter, and a memory for the unit delay element 16, and these shift registers and subtracters constitute the multipliers 11, 14, and 15 themselves. It does not require any other shift registers or memory. Therefore, the number of elements is significantly reduced.

FIG. 7 is a block diagram showing another embodiment of the digital filter according to the present invention, in which 17 is a multiplier, and parts corresponding to those in FIG. 3 are given the same reference numerals.

In this embodiment, a feedback loop of a digital LPF 12 is formed by a unit delay element 16 and a multiplier 17, and this feedback loop feeds back the output of the multiplier 14 to the adder 13, and also converts the output of the multiplier 14 into a digital signal. This is the output of the LPF 12.

Now, if the coefficient of the multiplier 14 is 1/L1 and the coefficient of the multiplier 17 is (L-1), then the transmission amount W of the digital L P l+' 12 is
iG (g). Here, assuming β-(L-1)/L, the above transfer function G(8) becomes as follows, which matches the above equation (lO). Therefore, the coefficient of multiplier 14 is (1-β), and the coefficient of multiplier 17 is β/(
1-β), this embodiment has the same characteristics as the embodiment shown in FIG.

In the embodiment shown in FIG. 3, the feedback loop by the unit delay element 16 feeds back the output of the multiplier 14, and the output of the multiplier 14 is further supplied to the multiplier 15 to output the digital LP signal.
The final output of F12 is the output of digital LPFI 2, which is the output of multiplier 14 in this embodiment shown in FIG. &
Feedback is made in the final output feedback loop. Generally, when implementing a feedback loop, feedback of the final output results in less response distortion and calculation rounding errors. Therefore, in this embodiment, these response distortions and rounding errors can be reduced.

FIG. 8 is a block diagram showing still another embodiment of the digital filter according to the present invention, in which 18 is a subtracter, 19 is an adder, and parts corresponding to those in FIG. 3 are given the same symbols. .

In this embodiment, the number of 3B multipliers in the digital L P F 12 is reduced compared to the above two embodiments. That is, a subtracter 18 that subtracts the output of the unit delay element 16 of the feedback loop from input data X, and a subtracter 1
A multiplier 14 to which the output of 8 is supplied, and a multiplier 1
A digital LPF 12 is formed by an adder 19 that adds the output of the unit delay element 4 and the output of the unit delay element 16, and this adder 1
9 is supplied to the unit delay element 16 and is also used as the output W of the digital LPF 12.

The relationship between the input data X1 and the output data W of this digital LPF 12 is W-K (X-z"W) 1z-'W, so the transfer function G (z) of the digital LPF is expressed as .Here, if K-1-β, then this transfer function G~
) becomes, which matches the above equation 00). Therefore, by setting the coefficient of the multiplier 14 to (1-β), this embodiment can have the same characteristics as the embodiment shown in FIG. There is one less multiplier, that is, one shift register, and the number of elements is further reduced.

When applying the digital filter having the first-order lag lead filter characteristics in the above embodiment to a phase compensation circuit of a phase control system, it is necessary to set the cutoff frequency fc to 1/100 to 1/1000 of the sampling frequency f8, Further, it is necessary to set the high frequency gain difference to -10 to -30 dB.

Therefore, in the above equation (7), the coefficients α and β are α−1
/2 and β-1/27, the above conditions can be satisfied by setting m = 3 to 5 and n'' to 5 to 6.

FIG. 9 shows the characteristics of the above embodiment when the coefficients α and β are set as described above.

As described above, by taking the weighted sequential moving average, it is possible to give the digital filter arbitrary lag-lead filter characteristics as shown in FIG. By setting α, β, L, etc. to all binary values (numbers in 2" format), the multiplier can be configured with a shift register and no other shift register is required. Moreover, only one memory is required for the unit delay element 16, and the number of elements is significantly reduced.

Although there are various other configurations of the digital filter based on the successive moving average method, in the above embodiment, #1 is inserted at the point where the multiplier is inserted before the starting point of the feedback loop to the unit delay element. It has the above characteristics.

By using the digital LPF in the above embodiment, an n-order LPF can be formed.

FIG. 10 is a block diagram showing a specific example of this. Generally, a first-order filter can be realized by cascading first-order (or second-order) filters, but as an n-order LPF, the same power 71
One primary LPF 12a, 12b, . . . with 17 frequencies.
・Represented by a nine-pole phi consisting of 12c connected in cascade. Such an external LPF can be realized by serially connecting n digital LPFs 12 shown in FIG. 6, FIG. 7, or FIG. 8.

Now, when the coefficient β of the multiplier in the -order digital LPF 12 is set to 1/24 and 1/26, the characteristics of the 6th order (tt-3) LPF are expressed as
A comparison with the characteristics of (n-1) is shown in FIG. As is clear from this figure, these characteristics are completely comparable to those of an analog LPF, and are fully usable.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to obtain a first-order lag-lead filter characteristic in which the cutoff frequency and gain can be arbitrarily set, and in addition, the configuration can be simplified and the number of elements can be significantly reduced. Therefore, the chip size can be reduced and IC can be realized at low cost, and the characteristics can be easily changed, and a digital filter with excellent functions can be provided without the drawbacks of the above-mentioned conventional technology.

[Brief explanation of drawings]

Fig. 1 (α) is a block diagram showing a conventional analog first-order lag lead filter, Fig. 1 (b) is its characteristic diagram, Fig. 2 is a block diagram showing an example of a conventional digital filter, and Fig. 6 is a block diagram showing one embodiment of the digital filter according to the present invention, FIG. 4 is a schematic diagram for explaining the functions of each part in FIG. 6, FIG. 5 is a characteristic diagram of the digital LPF shown in FIG. 3, and FIG. Figures (ci) and (b) are characteristic diagrams of the embodiment shown in Figure 6;
7 and 8 are block diagrams showing other embodiments of the digital filter according to the present invention, and FIG. 9 shows coefficients α and β.
10 is a characteristic diagram of each embodiment when specifying 1 based on the digital LPF of FIG.
FIG. 11 is a block diagram showing a specific example of the next-order filter, and a characteristic diagram showing an example of its characteristics. 10.13.19... Adder, 11, 14, 15°1
7... Multiplier, 12... Digital LPF, 16...
・, unit delay element. Figure 1 Figure 3 Figure 6 t), C) C) l Q, 01 (/, / f75/(b
] υυυ/ 0.01 0.1 fTs Fig. 7 O Fig. 8 Fig. 91;

Claims (1)

[Scope of Claims] (1) A feedback path is formed that includes a first multiplier that multiplies an input digital signal, a unit delay element, and a multiplier, and includes at least the unit delay element, and the input digital signal It consists of a digital low-pass filter that sequentially performs moving average processing, and a first adder that adds the output digital signal of the first multiplier and the output digital signal of the digital low-pass filter. A digital filter characterized in that it is configured so that it can be obtained. (2. The digital filter according to claim (1), characterized in that the digital low-pass filter is connected in cascade in multiple stages. (3) Claim (1) or (2) ), wherein each of the multipliers has a binary coefficient and is a shift register. (4) Claims (1), (2), or In item (3), the digital low-pass filter includes the feedback path including only the unit delay element, the feedback path, an adder to which the input digital signal is supplied, and a digital signal from the adder. and a sixth multiplier that multiplies the digital signal from the second multiplier to form the output digital signal, and the return path is the second multiplier. A digital filter characterized in that the digital signal from the adder is fed back to the adder. (5) In claim (1), (2) or (3), the digital low-pass filter teeth,
The feedback path includes the unit delay element and a fourth multiplier connected in series, and the feedback path and an adder to which the input digital signal is supplied multiply the digital signal from the adder. a fifth multiplier for processing and forming the output digital signal, the feedback path feeding back the output digital signal to the adder. (6) In claim No. (]), (2), or (3), the digital low-pass filter is characterized in that the feedback path includes only the unit delay element, and , consisting of a subtracter to which the input digital signal is supplied, a multiplier that multiplies the digital signal from the subtracter, and an adder to which the digital signal from the multiplier is supplied and forms the output digital signal. , wherein the feedback path feeds back the output digital signal to the subtracter and the adder.