JPH0562003U - Chip type electronic parts - Google Patents

Chip type electronic parts

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Publication number
JPH0562003U
JPH0562003U JP737192U JP737192U JPH0562003U JP H0562003 U JPH0562003 U JP H0562003U JP 737192 U JP737192 U JP 737192U JP 737192 U JP737192 U JP 737192U JP H0562003 U JPH0562003 U JP H0562003U
Authority
JP
Japan
Prior art keywords
electrodes
varistor
mounting
external
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP737192U
Other languages
Japanese (ja)
Inventor
武志 鈴木
昭仁 近藤
Original Assignee
マルコン電子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by マルコン電子株式会社 filed Critical マルコン電子株式会社
Priority to JP737192U priority Critical patent/JPH0562003U/en
Publication of JPH0562003U publication Critical patent/JPH0562003U/en
Pending legal-status Critical Current

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  • Non-Adjustable Resistors (AREA)
  • Thermistors And Varistors (AREA)
  • Details Of Resistors (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Abstract

(57)【要約】 【目的】 実装基板への実装時のはんだ付け時における
ツームストーン現象を解消し実装作業の安定化を図る。 【構成】 複数の内部電極1とバリスタ焼結体2が積層
構造となっており、前記内部電極1の外部取り出し電極
を積層体3の両側面部分とし、それ以外の内部電極1が
前記バリスタ焼結体2で囲まれて、内部電極1の外部取
り出し電極が位置する前記積層体3の両側面を含む端面
周辺に銀又は銀−パラジウム等のはんだ付け性の良い金
属で外部電極4、5を形成し、前記積層体3の両側面に
位置する前記外部電極4,5部分にはんだで濡れない材
料を被覆し被覆層6を形成する。これによって、実装基
板への装着の際被覆層6にはんだが付着しないようにな
る。
(57) [Summary] [Purpose] To stabilize the mounting work by eliminating the tombstone phenomenon during soldering when mounting on a mounting board. [Structure] A plurality of internal electrodes 1 and a varistor sintered body 2 have a laminated structure, and the external extraction electrodes of the internal electrodes 1 are the side surface portions of the laminated body 3, and the other internal electrodes 1 are the varistor fired. Surrounded by the united body 2, the external electrodes 4, 5 are made of a metal with good solderability such as silver or silver-palladium around the end faces including both side faces of the laminate 3 where the external extraction electrodes of the internal electrode 1 are located. Then, the external electrodes 4 and 5 located on both side surfaces of the laminate 3 are coated with a material that is not wet with solder to form a coating layer 6. This prevents solder from adhering to the coating layer 6 when it is mounted on the mounting board.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案は、セラミックコンデンサ又はバリスタ等の実装基板に装着してなる外 部電極構成を改良したチップ形電子部品に関する。 The present invention relates to a chip-type electronic component having an improved external electrode structure mounted on a mounting substrate such as a ceramic capacitor or a varistor.

【0002】[0002]

【従来の技術】[Prior Art]

従来一般化しているこれらチップ形電子部品、例えば単板形のチップバリスタ は、図3に示すようにバリスタ焼結体11の両面にバリスタ電極12を設け、こ のバリスタ電極12と接続した外部電極13を前記バリスタ焼結体11の両側面 を含む端面周辺に設け、この外部電極13を除く面に外装14を施しバリスタ本 体15を構成するようにしてなるものである。 As shown in FIG. 3, these chip-type electronic components that have been generalized in the past, such as a single-plate type chip varistor, are provided with varistor electrodes 12 on both sides of a varistor sintered body 11, and an external electrode connected to this varistor electrode 12. 13 is provided around the end faces including both side faces of the varistor sintered body 11, and the exterior 14 is provided on the surface excluding the external electrodes 13 to form the varistor main body 15.

【0003】 しかして、以上の構成になるバリスタ本体15の必要機器へのはんだ付けとし ては主にリフロー法が使用されており、その例を図4に示すが、実装基板16に 対してはんだ付けに寄与する外部電極13は、実装基板16と垂直な面、すなわ ちバリスタ焼結体11の両側面に位置する部分であるが、溶融したはんだによる 表面張力がバリスタ本体15を立ち上げるモーメントtが発生することからツー ムストーン現象(一方の電極が基板から浮き上がり垂直になってしまう現象)が 多発し、一方の外部電極13と基板電極17の所望の接続状態が確保できず、接 触不良となる問題点を抱えていた。The reflow method is mainly used for soldering the varistor main body 15 having the above-described configuration to necessary equipment. An example of this is shown in FIG. The external electrodes 13 that contribute to the attachment are located on a surface perpendicular to the mounting substrate 16, that is, on both side surfaces of the varistor sintered body 11. The surface tension of the molten solder raises the varistor body 15 moment. Due to the occurrence of t, a tombstone phenomenon (a phenomenon in which one electrode floats up from the substrate and becomes vertical) frequently occurs, and the desired connection state between the external electrode 13 on one side and the substrate electrode 17 cannot be secured, resulting in poor contact. Had the problem of becoming.

【0004】 そのため、このような問題点を解消する対策として、特開平2−156514 号公報に開示された技術がある。この公報に開示された技術は、図5に示すよう にチップ部品本体18の被実装基板への接触面の両端に一対の外部電極19を設 けたものであり、実装基板へのはんだ付け手段としてのリフロー法によってもツ ームストーン現象の発生がない利点を有している。Therefore, as a measure for solving such a problem, there is a technique disclosed in Japanese Patent Laid-Open No. 2-156514. The technique disclosed in this publication is such that a pair of external electrodes 19 are provided at both ends of the contact surface of the chip component body 18 with the mounted substrate as shown in FIG. The reflow method also has the advantage that the tombstone phenomenon does not occur.

【0005】 しかしながら、図6に示すように複数の内部電極20とバリスタ焼結体21が 積層構造となっており、前記内部電極20の外部取り出し電極を積層体22の両 側面部とし、それ以外の内部電極20が前記バリスタ焼結体21で囲まれた積層 形バリスタのようなものには、外部電極23を積層体22の両側面を含む端面周 辺に設ける必要があり、上記開示技術を積層形のバリスタにそのまま適用できず 、仮に適用するとすれば、スルホール等を作る必要があり、その場合寸法が大き くなり好ましくなかった。However, as shown in FIG. 6, a plurality of internal electrodes 20 and a varistor sintered body 21 have a laminated structure, and the external extraction electrodes of the internal electrodes 20 are both side surface portions of the laminated body 22, and other than that. In such a laminated varistor in which the internal electrode 20 is surrounded by the varistor sintered body 21, it is necessary to provide the external electrodes 23 on the end face periphery including both side surfaces of the laminated body 22. It cannot be applied to a laminated varistor as it is, and if it were to be applied, it would be necessary to form through holes and the like, and in that case the dimensions would be large, which was not desirable.

【0006】 また、実装基板への取付面は一方面のみであるため、はんだ付け実装の際方向 性の確認が必要であり、実装基板へ装着作業上有効なものとは言えなかった。Further, since the mounting surface to the mounting board is only one side, it is necessary to confirm the directionality at the time of soldering mounting, and it cannot be said that the mounting work to the mounting board is effective.

【0007】[0007]

【考案が解決しようとする課題】[Problems to be solved by the device]

以上述べたように、図3に示すチップ形バリスタは、ツームストーン現象が多 発してしまう問題があり、また図6に示す外部電極を積層体の両側面を含む端面 周辺に設けることができず外部電極に対称性がなくなるため、実装基板へのはん だ付けの際、方向性を揃えなければならず作業性を損ねる問題をもっていた。 As described above, the chip-type varistor shown in FIG. 3 has a problem that the tombstone phenomenon frequently occurs, and the external electrodes shown in FIG. 6 cannot be provided around the end face including both side faces of the laminate. Since the external electrodes have no symmetry, there is a problem in that workability is impaired because the directions must be aligned when soldering to the mounting board.

【0008】 本考案の目的は、部品本体の対称性を保ち、かつ実装基板へのはんだ付けの際 ツームストーン現象を解消したチップ形電子部品を提供することである。An object of the present invention is to provide a chip-type electronic component that maintains the symmetry of the component body and eliminates the tombstone phenomenon when soldering to a mounting board.

【0009】[0009]

【課題を解決するための手段】[Means for Solving the Problems]

本考案になるチップ形電子部品は、両側面を含む端面周辺に外部電極を設け、 この外部電極を被実装基板に設けた基板電極とはんだ付けにて接続してなるチッ プ形電子部品において、被実装基板と接触しない両側面に位置する前記外部電極 をはんだで濡れない材料で被覆層を形成したことを特徴とするものである。 The chip-type electronic component according to the present invention is a chip-type electronic component in which external electrodes are provided around the end faces including both side faces, and the external electrodes are connected to the substrate electrodes provided on the mounting substrate by soldering. It is characterized in that a coating layer is formed on the external electrodes located on both side surfaces which are not in contact with the mounted substrate by a material which is not wetted by solder.

【0010】[0010]

【作用】[Action]

電子部品本体の両側面を含む端面周辺に設けた外部電極の両側面に位置する部 分をはんだで濡れない材料で被覆しているため、この被覆部はリフロー時はんだ に濡れずモーメントは発生せず、ツームストーン現象の要因は解消される。 Since the parts located on both sides of the external electrodes, which are located around the end faces including both sides of the electronic component body, are covered with a material that does not get wet with solder, this coated part does not get wet with solder during reflow and a moment is not generated. The factor of the tombstone phenomenon is eliminated.

【0011】[0011]

【実施例】【Example】

以下、本考案の実施例について積層形のチップバリスタを例示し図面を参照し て説明する。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings by exemplifying a laminated chip varistor.

【0012】 図1に示すように、複数の内部電極1とバリスタ焼結体2が積層構造となって おり、前記内部電極1の外部取り出し電極を積層体3の両側面部分とし、それ以 外の内部電極1が前記バリスタ焼結体2で囲まれて、内部電極1の外部取り出し 電極が位置する前記積層体3の両側面を含む端面周辺に銀又は銀−パラジウム等 のはんだ付け性の良い金属で外部電極4,5を形成し、しかる後実装基板へのは んだ付け実装時に基板電極と接触しない積層体3の両側面に位置する前記外部電 極4,5部分に、例えばガラス,亜鉛又は耐熱性樹脂等からなるはんだで濡れな い材料を被覆し被覆層6を形成してなるものである。As shown in FIG. 1, a plurality of internal electrodes 1 and a varistor sintered body 2 have a laminated structure, and the external extraction electrodes of the internal electrodes 1 are the side surface portions of the laminated body 3, and other than that. Of the internal electrode 1 is surrounded by the varistor sintered body 2, and the outer extraction electrode of the internal electrode 1 has good solderability of silver or silver-palladium around the end faces including both side faces of the laminated body 3 where the electrodes are located. The external electrodes 4 and 5 are formed of metal, and are then attached to the external electrodes 4 and 5 located on both side surfaces of the laminated body 3 which do not come into contact with the substrate electrodes during the mounting by mounting on the mounting substrate. The coating layer 6 is formed by coating a material which is not wet with solder such as zinc or heat resistant resin.

【0013】 以上のような構成になる積層形のチップバリスタを実装基板にはんだ付け装着 する場合、図2に示すように実装基板7に設けた基板電極8に、前記積層体3の 端面周辺に位置する外部電極4,5を接触させはんだリフローをする訳であるが 、基板電極7と接触しない積層体3の両側面に位置する前記外部電極4,5部分 にははんだで濡れない材料を被覆した被覆層6が形成されているため、この部分 にははんだが着かず、ツームストーン現象の発生要因を解消でき、基板電極7と 外部電極4,5の接触部分のはんだ付け9がスムースに行われ、実装基板7への 接触状態の優れた積層形のチップバリスタが得られる。When the laminated chip varistor having the above-described structure is soldered and mounted on the mounting board, the board electrodes 8 provided on the mounting board 7 are connected to the periphery of the end surface of the laminated body 3 as shown in FIG. The external electrodes 4 and 5 located there are brought into contact with each other for solder reflow, but the external electrodes 4 and 5 located on both side surfaces of the laminate 3 which do not come into contact with the substrate electrode 7 are coated with a material which is not wet with solder. Since the covered coating layer 6 is formed, the solder does not adhere to this portion, and the cause of the tombstone phenomenon can be eliminated, and the soldering 9 at the contact portion between the substrate electrode 7 and the external electrodes 4 and 5 can be performed smoothly. As a result, a laminated chip varistor having excellent contact with the mounting substrate 7 can be obtained.

【0014】 以下、図1に示す本考案Aと図3に示す従来例BのV.S.Pによるリフロー はんだ付けにおけるツームストーン現象の発生状況を比較した結果、表1に示す 通りであった。Hereinafter, V. of the invention A shown in FIG. 1 and conventional example B shown in FIG. 3 will be described. S. Reflow by P As a result of comparing the occurrence of the tombstone phenomenon in soldering, the results are shown in Table 1.

【0015】 試料は、本考案A及び従来例Bとも1.8mm×0.8mm×0.5mm寸法 の積層体にAg−Pbペーストを塗布し850℃で焼成して外部電極を形成した 積層形チップバリスタであり、本考案Aの被覆層は、ガラスペーストを800℃ で焼成して構成したものである。The samples of the present invention A and the conventional example B are a laminated type in which an Ag-Pb paste is applied to a laminate having a size of 1.8 mm × 0.8 mm × 0.5 mm and baked at 850 ° C. to form an external electrode. This is a chip varistor, and the coating layer of Invention A is formed by firing glass paste at 800 ° C.

【0016】 試料数は本考案A及び従来例Bともそれぞれ100個である。The number of samples in each of the present invention A and the conventional example B is 100.

【0017】[0017]

【表1】 [Table 1]

【0018】 表1から明らかなように、従来例Bはツームストーンの現象発生率が3%あり 、実装基板への装着信頼性に欠け実用上問題があるのに対し、本考案Aはツーム ストーンの現象発生率が皆無であり、実装基板への装着信頼性に富む優れた作用 効果を実証した。As is clear from Table 1, in the conventional example B, the occurrence rate of the tombstone is 3%, and the reliability of mounting on the mounting board is lacking and there is a problem in practical use. The occurrence rate of the phenomenon is zero, and it has been demonstrated that it has an excellent effect of being highly reliable in mounting on a mounting board.

【0019】 なお、上記実施例では、積層形のチップバリスタを例示して説明したが、これ に限定されることなく単板状のチップバリスタを始め、セラミックコンデンサ及 び積層形のセラミックコンデンサに適用しても同様の効果を得ることができる。In the above embodiments, the laminated chip varistor has been described as an example. However, the invention is not limited to this, and is applied to a ceramic capacitor and a laminated ceramic capacitor including a single-plate chip varistor. Even if it is, the same effect can be obtained.

【0020】[0020]

【考案の効果】[Effect of the device]

本考案によれば、チップ形電子部品の対称性を保ち、実装基板への装着作業を 損ねることなく、実装時のはんだ付け時におけるツームストーン現象を解消した 実用的価値の高いチップ形電子部品を得ることができる。 According to the present invention, a chip-type electronic component with high practical value that maintains the symmetry of the chip-type electronic component and eliminates the tombstone phenomenon during soldering during mounting without impairing the mounting work on the mounting board. Obtainable.

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案の一実施例に係る積層形のチップバリス
タを示す一部断面斜視図である。
FIG. 1 is a partial cross-sectional perspective view showing a laminated chip varistor according to an embodiment of the present invention.

【図2】本考案の一実施例に係る図1に示す積層形のチ
ップバリスタの実装基板への装着例を示す正面図であ
る。
FIG. 2 is a front view showing an example of mounting the laminated chip varistor shown in FIG. 1 on a mounting board according to an embodiment of the present invention.

【図3】従来例に係るチップバリスタを示す断面図であ
る。
FIG. 3 is a sectional view showing a chip varistor according to a conventional example.

【図4】従来例に係る図3に示すチップバリスタの実装
基板への装着例を示す正面図である。
FIG. 4 is a front view showing an example of mounting the chip varistor shown in FIG. 3 on a mounting substrate according to a conventional example.

【図5】従来例に係るチップ部品を示す示す斜視図であ
る。
FIG. 5 is a perspective view showing a chip part according to a conventional example.

【図6】一般的な積層形バリスタを示す断面図である。FIG. 6 is a sectional view showing a general laminated varistor.

【符号の説明】[Explanation of symbols]

1 内部電極 2 バリスタ焼結体 3 積層体 4 外部電極 5 外部電極 6 被覆層 7 実装基板 8 基板電極 1 Internal Electrode 2 Varistor Sintered Body 3 Laminated Body 4 External Electrode 5 External Electrode 6 Cover Layer 7 Mounting Substrate 8 Board Electrode

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01G 1/14 F 9174−5E ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01G 1/14 F 9174-5E

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 両側面を含む端面周辺に外部電極を設
け、この外部電極を被実装基板に設けた基板電極とはん
だ付けにて接続してなるチップ形電子部品において、被
実装基板と接触しない両側面に位置する前記外部電極を
はんだで濡れない材料で被覆層を形成したことを特徴と
するチップ形電子部品。
1. A chip-type electronic component in which an external electrode is provided around an end face including both side surfaces and the external electrode is connected to a substrate electrode provided on the mounted substrate by soldering, and does not contact the mounted substrate. A chip-type electronic component, wherein a coating layer is formed on the external electrodes located on both sides by a material that does not get wet with solder.
JP737192U 1992-01-23 1992-01-23 Chip type electronic parts Pending JPH0562003U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP737192U JPH0562003U (en) 1992-01-23 1992-01-23 Chip type electronic parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP737192U JPH0562003U (en) 1992-01-23 1992-01-23 Chip type electronic parts

Publications (1)

Publication Number Publication Date
JPH0562003U true JPH0562003U (en) 1993-08-13

Family

ID=11664115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP737192U Pending JPH0562003U (en) 1992-01-23 1992-01-23 Chip type electronic parts

Country Status (1)

Country Link
JP (1) JPH0562003U (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005243835A (en) * 2004-02-25 2005-09-08 Murata Mfg Co Ltd Chip electronic component
US20140041913A1 (en) * 2012-08-09 2014-02-13 Tdk Corporation Electronic circuit module component
JP2014135429A (en) * 2013-01-11 2014-07-24 Taiyo Yuden Co Ltd Laminated ceramic capacitor
JP2015228506A (en) * 2015-07-22 2015-12-17 太陽誘電株式会社 Multilayer ceramic capacitor
US9251958B2 (en) 2012-04-19 2016-02-02 Murata Manufacturing Co., Ltd. Monolithic ceramic electronic component
US9269494B2 (en) 2012-04-19 2016-02-23 Murata Manufacturing Co., Ltd. Monolithic ceramic electronic component

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005243835A (en) * 2004-02-25 2005-09-08 Murata Mfg Co Ltd Chip electronic component
JP4649847B2 (en) * 2004-02-25 2011-03-16 株式会社村田製作所 Chip-type electronic components
US9251958B2 (en) 2012-04-19 2016-02-02 Murata Manufacturing Co., Ltd. Monolithic ceramic electronic component
US9269494B2 (en) 2012-04-19 2016-02-23 Murata Manufacturing Co., Ltd. Monolithic ceramic electronic component
US20140041913A1 (en) * 2012-08-09 2014-02-13 Tdk Corporation Electronic circuit module component
US9320146B2 (en) * 2012-08-09 2016-04-19 Tdk Corporation Electronic circuit module component
JP2014135429A (en) * 2013-01-11 2014-07-24 Taiyo Yuden Co Ltd Laminated ceramic capacitor
US9318265B2 (en) 2013-01-11 2016-04-19 Taiyo Yuden Co., Ltd. Multilayer ceramic capacitor provided with external electrodes partially covered by solder non-adhesion film
JP2015228506A (en) * 2015-07-22 2015-12-17 太陽誘電株式会社 Multilayer ceramic capacitor

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