JPH0562003U - Chip type electronic parts - Google Patents

Abstract

(57) [Summary] [Purpose] To stabilize the mounting work by eliminating the tombstone phenomenon during soldering when mounting on a mounting board. [Structure] A plurality of internal electrodes 1 and a varistor sintered body 2 have a laminated structure, and the external extraction electrodes of the internal electrodes 1 are the side surface portions of the laminated body 3, and the other internal electrodes 1 are the varistor fired. Surrounded by the united body 2, the external electrodes 4, 5 are made of a metal with good solderability such as silver or silver-palladium around the end faces including both side faces of the laminate 3 where the external extraction electrodes of the internal electrode 1 are located. Then, the external electrodes 4 and 5 located on both side surfaces of the laminate 3 are coated with a material that is not wet with solder to form a coating layer 6. This prevents solder from adhering to the coating layer 6 when it is mounted on the mounting board.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a chip-type electronic component having an improved external electrode structure mounted on a mounting substrate such as a ceramic capacitor or a varistor.

[0002]

[Prior Art]

 As shown in FIG. 3, these chip-type electronic components that have been generalized in the past, such as a single-plate type chip varistor, are provided with varistor electrodes 12 on both sides of a varistor sintered body 11, and an external electrode connected to this varistor electrode 12. 13 is provided around the end faces including both side faces of the varistor sintered body 11, and the exterior 14 is provided on the surface excluding the external electrodes 13 to form the varistor main body 15.

The reflow method is mainly used for soldering the varistor main body 15 having the above-described configuration to necessary equipment. An example of this is shown in FIG. The external electrodes 13 that contribute to the attachment are located on a surface perpendicular to the mounting substrate 16, that is, on both side surfaces of the varistor sintered body 11. The surface tension of the molten solder raises the varistor body 15 moment. Due to the occurrence of t, a tombstone phenomenon (a phenomenon in which one electrode floats up from the substrate and becomes vertical) frequently occurs, and the desired connection state between the external electrode 13 on one side and the substrate electrode 17 cannot be secured, resulting in poor contact. Had the problem of becoming.

Therefore, as a measure for solving such a problem, there is a technique disclosed in Japanese Patent Laid-Open No. 2-156514. The technique disclosed in this publication is such that a pair of external electrodes 19 are provided at both ends of the contact surface of the chip component body 18 with the mounted substrate as shown in FIG. The reflow method also has the advantage that the tombstone phenomenon does not occur.

However, as shown in FIG. 6, a plurality of internal electrodes 20 and a varistor sintered body 21 have a laminated structure, and the external extraction electrodes of the internal electrodes 20 are both side surface portions of the laminated body 22, and other than that. In such a laminated varistor in which the internal electrode 20 is surrounded by the varistor sintered body 21, it is necessary to provide the external electrodes 23 on the end face periphery including both side surfaces of the laminated body 22. It cannot be applied to a laminated varistor as it is, and if it were to be applied, it would be necessary to form through holes and the like, and in that case the dimensions would be large, which was not desirable.

Further, since the mounting surface to the mounting board is only one side, it is necessary to confirm the directionality at the time of soldering mounting, and it cannot be said that the mounting work to the mounting board is effective.

[0007]

[Problems to be solved by the device]

 As described above, the chip-type varistor shown in FIG. 3 has a problem that the tombstone phenomenon frequently occurs, and the external electrodes shown in FIG. 6 cannot be provided around the end face including both side faces of the laminate. Since the external electrodes have no symmetry, there is a problem in that workability is impaired because the directions must be aligned when soldering to the mounting board.

An object of the present invention is to provide a chip-type electronic component that maintains the symmetry of the component body and eliminates the tombstone phenomenon when soldering to a mounting board.

[0009]

[Means for Solving the Problems]

 The chip-type electronic component according to the present invention is a chip-type electronic component in which external electrodes are provided around the end faces including both side faces, and the external electrodes are connected to the substrate electrodes provided on the mounting substrate by soldering. It is characterized in that a coating layer is formed on the external electrodes located on both side surfaces which are not in contact with the mounted substrate by a material which is not wetted by solder.

[0010]

[Action]

 Since the parts located on both sides of the external electrodes, which are located around the end faces including both sides of the electronic component body, are covered with a material that does not get wet with solder, this coated part does not get wet with solder during reflow and a moment is not generated. The factor of the tombstone phenomenon is eliminated.

[0011]

【Example】

 Hereinafter, an embodiment of the present invention will be described with reference to the drawings by exemplifying a laminated chip varistor.

As shown in FIG. 1, a plurality of internal electrodes 1 and a varistor sintered body 2 have a laminated structure, and the external extraction electrodes of the internal electrodes 1 are the side surface portions of the laminated body 3, and other than that. Of the internal electrode 1 is surrounded by the varistor sintered body 2, and the outer extraction electrode of the internal electrode 1 has good solderability of silver or silver-palladium around the end faces including both side faces of the laminated body 3 where the electrodes are located. The external electrodes 4 and 5 are formed of metal, and are then attached to the external electrodes 4 and 5 located on both side surfaces of the laminated body 3 which do not come into contact with the substrate electrodes during the mounting by mounting on the mounting substrate. The coating layer 6 is formed by coating a material which is not wet with solder such as zinc or heat resistant resin.

When the laminated chip varistor having the above-described structure is soldered and mounted on the mounting board, the board electrodes 8 provided on the mounting board 7 are connected to the periphery of the end surface of the laminated body 3 as shown in FIG. The external electrodes 4 and 5 located there are brought into contact with each other for solder reflow, but the external electrodes 4 and 5 located on both side surfaces of the laminate 3 which do not come into contact with the substrate electrode 7 are coated with a material which is not wet with solder. Since the covered coating layer 6 is formed, the solder does not adhere to this portion, and the cause of the tombstone phenomenon can be eliminated, and the soldering 9 at the contact portion between the substrate electrode 7 and the external electrodes 4 and 5 can be performed smoothly. As a result, a laminated chip varistor having excellent contact with the mounting substrate 7 can be obtained.

Hereinafter, V. of the invention A shown in FIG. 1 and conventional example B shown in FIG. 3 will be described. S. Reflow by P As a result of comparing the occurrence of the tombstone phenomenon in soldering, the results are shown in Table 1.

The samples of the present invention A and the conventional example B are a laminated type in which an Ag-Pb paste is applied to a laminate having a size of 1.8 mm × 0.8 mm × 0.5 mm and baked at 850 ° C. to form an external electrode. This is a chip varistor, and the coating layer of Invention A is formed by firing glass paste at 800 ° C.

The number of samples in each of the present invention A and the conventional example B is 100.

[0017]

[Table 1]

As is clear from Table 1, in the conventional example B, the occurrence rate of the tombstone is 3%, and the reliability of mounting on the mounting board is lacking and there is a problem in practical use. The occurrence rate of the phenomenon is zero, and it has been demonstrated that it has an excellent effect of being highly reliable in mounting on a mounting board.

In the above embodiments, the laminated chip varistor has been described as an example. However, the invention is not limited to this, and is applied to a ceramic capacitor and a laminated ceramic capacitor including a single-plate chip varistor. Even if it is, the same effect can be obtained.

[0020]

[Effect of the device]

 According to the present invention, a chip-type electronic component with high practical value that maintains the symmetry of the chip-type electronic component and eliminates the tombstone phenomenon during soldering during mounting without impairing the mounting work on the mounting board. Obtainable.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional perspective view showing a laminated chip varistor according to an embodiment of the present invention.

FIG. 2 is a front view showing an example of mounting the laminated chip varistor shown in FIG. 1 on a mounting board according to an embodiment of the present invention.

FIG. 3 is a sectional view showing a chip varistor according to a conventional example.

FIG. 4 is a front view showing an example of mounting the chip varistor shown in FIG. 3 on a mounting substrate according to a conventional example.

FIG. 5 is a perspective view showing a chip part according to a conventional example.

FIG. 6 is a sectional view showing a general laminated varistor.

[Explanation of symbols]

 1 Internal Electrode 2 Varistor Sintered Body 3 Laminated Body 4 External Electrode 5 External Electrode 6 Cover Layer 7 Mounting Substrate 8 Board Electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01G 1/14 F 9174-5E

Claims (1)

[Scope of utility model registration request] 1. A chip-type electronic component in which an external electrode is provided around an end face including both side surfaces and the external electrode is connected to a substrate electrode provided on the mounted substrate by soldering, and does not contact the mounted substrate. A chip-type electronic component, wherein a coating layer is formed on the external electrodes located on both sides by a material that does not get wet with solder.