JPH0557239B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a GaAs crystal with high resistance and a method for manufacturing the same. The high resistance GaAs crystal of the present invention is
It can be mainly used as a substrate for various microwave devices, optical devices, etc., and as an infrared modulating material, and the present invention further provides a method for manufacturing the same with high yield. (Prior Art) Conventionally, the following method is known as a method for manufacturing a high resistance GaAs crystal having a specific resistance of 10 ⁶ Ω·cm or more at 300 Ω. (A) A method of crystal growth in which the total concentration of deep electrically active impurities such as chromium, oxygen, iron, etc. is intentionally doped to a higher concentration than the total concentration of shallow electrically active impurities [Reference 1, Tokkosho 53-46070]. (B) Ga of GaAs polycrystalline raw material used before crystal growth
Crystal growth is performed by controlling the composition ratio of Ga and As, or in the case of direct synthesis, by controlling the molar ratio of charged Ga and As [Reference 2, DE
Holmes et.al. “Stoichiometry−Related
Centere in LEC GaAs”, Semi-Insulating
− Materials, Evian (1982), p19,
Shiba Publishing〕. Methods (A) and (B) above are methods for obtaining high-resistance GaAs crystals, and both focus on the conditions before or during crystal growth, and the effect of the thermal environment on electrical resistance after solidification of the crystal is not considered. Not touched. [Problems to be solved by the invention] In high-resistance GaAs crystals, it is necessary to improve the characteristics and reproducibility of the active layer formed on the wafer by direct ion implantation or epitaxial method. Therefore, it is required to reduce the concentration of doping impurities.
Alternatively, in order to improve crystallinity, it is necessary to reduce the amount of impurity doped. By the way, most of the electrically active shallow impurities are caused by contamination from the raw materials used, crucibles or boats, or heaters, and the size of these impurities is predicted before crystal growth and is processed accordingly. By using the above-mentioned conventional method, in which the necessary minimum amount of deep impurities is doped before or during crystal growth, or generated by changing the composition ratio of the raw materials used, ζ > 5 × 10 ⁶ (Ω- It is difficult to obtain GaAs crystals with high resistance (cm) with good reproducibility, and this has been a cause of lower yields. An object of the present invention is to solve the above-mentioned drawbacks of the conventional method, and to provide a novel high-resistance GaAs crystal and a method for producing the same with good reproducibility. [Means for solving the problem] The present invention utilizes a deep impurity level that can be controlled by thermal energy, such as an EL2 unit, and changes the thermal environment after crystal solidification, thereby increasing the resistance. The present invention provides a GaAs crystal and a method for manufacturing the same. In the present invention, the concentration of thermally uncontrollable impurity levels is in a range of 5×10 ¹⁶ cm ^-3 or less, and the concentration of thermally controllable impurity levels is in a thermally uncontrollable range. A high-resistance GaAs crystal obtained using thermally controllable impurity levels with a specific resistance of 5
The high-resistance GaAs crystal described above having a resistance of ×10 ⁶ Ωcm or more, and the GaAs crystal having a concentration of thermally uncontrollable impurity levels of 5 × 10 ¹⁶ cm ^-3 or less,
600 in an atmosphere containing inert gas, As, or in vacuum
This is a method for manufacturing a high-resistance GaAs crystal, which is characterized by performing thermal control in a temperature range of ~1100°C for 4 to 60 hours. The high-resistance GaAs crystal of the present invention and its manufacturing method will be explained in detail below in terms of its principle. Impurities such as chromium, oxygen, iron, etc., or inherent defects in the GaAs crystal form electrically active deep impurity levels in the GaAs crystal. Regarding the former impurity, the lattice position that the impurity occupies in the GaAs crystal is determined during crystal solidification, so the energy level formed by the impurity and its concentration can be controlled by changing the thermal environment after solidification. is not possible. On the other hand, regarding the latter intrinsic defect, considering the fact that dislocations, which are a type of crystal defect, can easily move even at 600℃, the deep impurity level and concentration created by the intrinsic defect can be changed depending on the thermal environment after solidification. It is easy to see that it can be controlled. In fact, Rumsby
found that by annealing the solidified GaAs crystal in an appropriate thermal environment, the concentration of deep donor-type levels called "EL2" created by inherent defects in the GaAs crystal changes [Reference 3] ,D.
Rumsby et al. “Improved Uniformity of LEC
Undoped Gallium Arsenide Rroduced by
High Temperature Annealing” GaAs IC
Symposium (1983) IEEE 34-37]. Furthermore, it has been found that the concentration of this "EL2" is approximately 5×10 ¹⁵ to 5×10 ¹⁶ cm ^-3 in GaAs crystals [Reference 4, F. Hasegawa et.al.
“Distribution of the Main Trap EL2 in
Undoped LEC GaAs”Jap.J.Appl.Phys. 22
(1983) L502: Reference 5, DE Holmes et al.
“Contour maps of EL2 deep level in liquid−
encapsulated Czochralski GaAs” J.Appl.
Phys. 55 (1984) 3588]. This shows that the concentration of deep impurity levels created by intrinsic defects can be controlled by the thermal environment after crystal solidification. In addition, in recent years, the theory of “assembly of As” (EL2 family) as the origin of “EL2” has become popular [Reference 6, M. Tanigichi et.al. “Spectral
distributions of photoquenching rate and
multimetastable states for midgap electron
trap (EL2 family) in GaAs”Appl.Phy.Lett.
45, (1984) 69] It is easy to imagine that the degree of formation of this “As aggregate” changes depending on the thermal environment, and the concentration of deep levels can change. The present invention will be specifically explained below. As raw materials, impurities such as chromium, oxygen, iron, etc., which form electrically active deep impurity levels and whose concentration cannot be controlled by the thermal environment after crystal solidification, are intentionally added to 5×10 ¹⁶ cm ^- Contains ³ or less, or Ga
The aim is to obtain high-resistance GaAs crystals using intentionally changed composition ratios of GaAs and As.
GaAs single crystals are grown and solidified using the HB method, GF method, or LEC method. Through this process, chromium,
Impurities such as oxygen and iron form electrically active deep levels in the forbidden band of GaAs, and this concentration cannot be controlled due to the thermal environment after solidification. Also
For those with different raw material composition ratios of Ga and As,
The deep donor level called “EL2” is 5×10 ¹⁵
About 5×10 ¹⁶ cm ⁻³ is formed after solidification. The solidified crystal is then heated for 600 to 600 minutes in an atmosphere containing inert gas or As, or in vacuum.
Thermal control is possible by performing heat treatment in the temperature range of 1100℃ for 4 to 60 hours.
Generates intrinsic defects that form deep levels, increases their concentration, and creates a state in which the concentration of stable electrically active deep levels is higher than the concentration of electrically active shallow impurity levels. It can be seen that a high-resistance GaAs crystal can be stably obtained by this method. However, if the heat treatment is performed in a harsher thermal environment than the heat treatment conditions of the present invention, that is, at 1100° C. or higher and for a treatment time of 60 hours or more, As will be violently dissociated from the ingot surface, resulting in a significant decrease in crystallinity. In addition, the thermal environment is milder than the conditions of the present invention, i.e., 600℃ or less,
If the heat treatment is performed for a treatment time of 4 hours or less, the effect will not be observed because there is insufficient thermal energy to generate inherent defects. [Example] The present invention will be specifically explained below using Examples. The raw material used is GaAs polycrystal with a carrier concentration of 5×10 ¹⁶ cm ^-3 or less, made by the HB method.
Use 1500g. By intentionally adding 285 mg of 99.99% pure metallic chromium to this GaAs polycrystal,
A GaAs crystal was grown by the LEC method using a PBN crucible, and a single crystal with a diameter of 55±3 mm and a length of 50 mm was obtained. The crystal is divided into three parts, S, M, and T, as shown in Figure 1. The lengths s, m, and t of each part are 10, 30, and 10 mm, respectively. Two wafers F and B are cut out from the positions F and B shown in the figure from each part of S and T, finished into mirror wafers through the lapping and polishing process, and then cut in the direction perpendicular to OF as shown in Figure 3. A 5 x 5 mm square sample was cut out, and the specific resistance was measured using a Van der Paun-type Hall measurement method. The results are shown in FIG. From this, the F1 wafer has a resistivity of nearly 10 ³ Ωcm at the center of the wafer, whereas
It can be seen that the resistance at the periphery of the wafer is less than 5×10 ⁶ Ω·cm, indicating that the resistance has been reduced. On the other hand, the B1 wafer has a specific resistance of 5×10 ⁶ Ω·cm or less over the entire surface of the wafer, indicating that the resistance has been reduced. From this, it is inferred that the portion M sandwiched between F1 and B1 has a low resistance. Next, this central portion M was vacuum sealed in a quartz tube, which was inserted into a heat treatment furnace as shown in FIG. 4, and heat treated at 800° C. for 12 hours. 1 in Figure 4
is a quartz tube, 2 is a heat treatment furnace, and 3 is a heater.
After the heat treatment, the ingot M was taken out and two wafers, M2 and M24, were cut out from a position 5 mm from the end of the ingot, as shown in FIG. The resistivity of this wafer was measured in the same manner as described above. This result is shown in Figure 3 for M2
(x mark), M24△ mark. As is clear from this figure, the specific resistance of both wafers was 10 ⁷ Ω·cm or more over the entire surface of the wafer, confirming that the resistivity was high. Further, using the remaining portion of the wafer whose resistivity was measured, the chromium concentration was measured by the GFA method, the silicon concentration by the SSMS method, and the carbon concentration by the LVM method, and the results are summarized in Table 1 below. [Table] It is clear from this table that there is almost no change in the concentration of chromium, which forms deep levels, and the concentration of silicon and carbon, which form shallow levels, due to heat treatment. In this example, the crystals after solidification were cooled to room temperature, taken out from the furnace, and subjected to heat treatment. However, after crystal solidification, the ingot has a melting point (1238℃)
By intentionally changing the thermal environment between 600 and 1100℃ and holding time between 4 and 60 hours during the cooling process from nearby to room temperature, it is possible to generate intrinsic defects and increase their concentration. Needless to say. (Effect of the invention) As explained above, by changing the thermal environment after solidification, it is possible to control the concentration of intrinsic defects that form electrically active deep levels. This method has the advantage of improving the yield of GaAs crystals, since it is possible to increase the resistance of GaAs crystals that would otherwise be defective by increasing their resistance and make them good.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the GaAs crystal and wafer cutting position in an embodiment of the present invention, FIG. 2 is a diagram illustrating sample sampling from the F1 wafer cut out as described above, and FIG. 3 is an embodiment of the present invention. This is a graph showing the results of measuring the relationship between the distance from the center of each wafer and the resistivity in
1, ● mark B1, × mark M2, △ mark M24 are shown. FIG. 4 is a diagram showing an embodiment of thermal control of the present invention.

Claims (1)

[Claims] 1. The concentration of thermally uncontrollable impurity levels is 5×
10 ¹⁶ cm ^-3 or less, and the concentration of thermally controllable impurity levels is the same as or higher than the concentration of thermally uncontrollable impurity levels. High-resistance GaAs crystal obtained by utilizing impurity levels that can be controlled virtually. 2. The high-resistance GaAs crystal according to claim 1, which has a specific resistance of 5×10 ⁶ Ωcm or more. 3 The concentration of thermally uncontrollable impurity levels is 5×
GaAs crystals in the range of 10 ¹⁶ cm ^-3 or less are heated at 600 to 1100 in an atmosphere containing inert gas, As, or in vacuum.
A method for producing a high-resistance GaAs crystal, characterized by performing thermal control for 4 to 60 hours in a temperature range of °C.