JPH0555584A - Manufacture of insulated-gate field-effect transistor - Google Patents

Abstract

PURPOSE:To eliminate a need for mask matching and enable machining accuracy/yield to be improved by allowing a phosphor glass oxide film to be adhered to an entire surface of a semiconductor substrate, reflow to be made, and then an entire surface of the phosphor glass oxide film to be etched until a silicon semiconductor substrate surface on a source diffusion region is exposed for a contact opening. CONSTITUTION:A contact opening of an aluminum electrode 9 to a source diffusion region 3 and a channel diffusion region 2 is self-aligned and then a side surface of a polycrystalline silicon film 11 which constitutes a gate electrode is formed gently by a phosphor glass oxide film 13. An ion is implanted for forming a source region with the polycrystalline silicon film 11 and a non- doped oxide film 12 as a mask. The phosphor glass oxide film 13 is adhered to an entire surface of a semiconductor substrate for reflowing. An entire surface of the phosphor glass oxide film 13 is etched by an anisotropic dry etching thus enabling an opening of a contact of the source diffusion region 3 and the channel diffusion region 2 to be formed in self-aligned manner.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor, and more particularly to a vertical insulated gate field effect transistor such as a power MOSFET.

[0002]

2. Description of the Related Art FIG. 5 is a sectional view of a conventional vertical insulated gate field effect transistor (hereinafter referred to as vertical MOSFET). Reference numeral 1 denotes an N-type semiconductor substrate, which is a vertical MO
It constitutes the drain region of the SFET. Reference numeral 2 is a channel diffusion region of a P-type vertical MOSFET. Reference numeral 3 is an N ⁺ type diffusion layer, which forms a source diffusion region. Reference numeral 4 is a gate insulating film made of a thin oxide film, and reference numeral 5
Is a gate electrode made of polycrystalline silicon, and by applying a voltage to the gate electrode 5, conduction between the source diffusion region 3 and the drain region is controlled via the gate insulating film 4. Reference numeral 8 is an interlayer insulating film made of an oxide film of phosphorus glass or the like, reference numeral 9 is an aluminum electrode, and forms a source electrode of the vertical MOSFET. Such a structure of the vertical MOSFET is suitable for a power MOSFET that handles a high breakdown voltage and a large current.

Conventionally, a MOSFET having such a structure has been manufactured by the manufacturing process described below. First, the surface of the N-type silicon semiconductor substrate 1 is gate-oxidized to form the gate insulating film 4
To the entire surface. Then, a polycrystalline silicon film is deposited on the entire surface of the gate insulating film 4. Then, the polycrystalline silicon film is doped with impurities such as phosphorus, and the gate electrode 5 is formed by photoetching.

Next, P-type impurities such as boron are ion-implanted by self-alignment using the gate electrode 5 which is a polycrystalline silicon film as a mask. By diffusing boron or the like into the semiconductor substrate 1 by heat treatment,
A P-type channel diffusion region 2 is formed. Then, a photoresist is applied on the entire surface, a portion which becomes a source region of the photoresist is opened, and phosphorus is ion-implanted using the photoresist and the gate electrode 5 as a mask. Then, by heat treatment, an N ⁺ type source diffusion region 3 which is a high concentration diffusion layer of phosphorus is formed. Thus, immediately below the gate electrode 5, the P type channel diffusion region 2 and the N ⁺ type source diffusion region 3 are doubly formed by self-alignment.

Next, a phosphorus-doped oxide film to be the interlayer insulating film 8 is deposited on the entire surface of the semiconductor substrate 1 by CVD or the like. Then, a baking process is performed, a source region is diffused by the heat treatment, a photoresist is applied to the entire surface, and a contact opening is formed by photoetching using a contact mask. After opening the contact, the photoresist is removed and an aluminum film is deposited on the entire surface of the semiconductor substrate. Then, a photoresist is applied, and an aluminum electrode 9 is formed by photoetching with a mask of the aluminum electrode. Through the series of steps described above, the vertical MOSFET shown in FIG. 5 is completed.

[0006]

However, in the above-mentioned conventional manufacturing method, the contact openings are formed by photoetching by aligning the contact pattern with a mask. Therefore, the mask misalignment of the contact pattern directly affects the processing accuracy of the product, which has been a problem for improving the processing accuracy of the product and the yield of the product. In addition, the contact opening is formed by photoetching an interlayer insulating film such as a thick phosphorous glass film, so that a step is steep or an overhang occurs in the opening,
There was a problem with the step coverage of the aluminum electrode.

[0007]

In order to solve the problems of the conventional manufacturing method, the present invention provides a method of manufacturing a vertical MOSFET, including a step of depositing a gate insulating film on a semiconductor substrate,
Depositing a polycrystalline silicon film on the gate insulating film, depositing a non-doped oxide film on the polycrystalline silicon film, and depositing the polycrystalline silicon film and the non-doped so as to form a gate electrode pattern. Photo-etching the oxide film, and forming a channel diffusion region by self-alignment using the gate electrode pattern as a mask,
Forming a source diffusion region using the photoresist and the gate electrode as a mask; depositing a phosphorus-doped oxide film on the semiconductor substrate and reflowing; and forming the phosphorus-doped oxide film and the gate insulating film on the semiconductor substrate surface. It is composed of a step of forming a contact opening by removing the whole surface by etching until it is exposed, and a step of depositing an aluminum film on the entire surface of the semiconductor substrate and forming an aluminum electrode by photoetching.

[0008]

In the present invention, the contact opening is coated with a phosphorus-doped oxide film on the entire surface of the semiconductor substrate and reflowed,
The phosphorus-doped oxide film and the gate insulating film are entirely etched until the surface of the silicon semiconductor substrate on the source diffusion region is exposed to form a contact opening by self-alignment. Therefore, the conventional process of applying photoresist for contacts and aligning masks is eliminated,
Since there is no need for mask alignment, the problem of mask misalignment disappears. Furthermore, since the phosphorus-doped glass film is reflowed and the phosphorus-doped oxide film is removed by etching the entire surface, the interlayer insulating film is gently formed on the side surface of the gate electrode, and the step coverage is greatly improved. As described above, the processing accuracy of the vertical MOSFET is improved, and the product yield is improved.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a vertical MOSFE according to an embodiment of the present invention.
It is sectional drawing of the completion stage in the manufacturing process of T. The contact opening of the aluminum electrode 9 to the source diffusion region 3 and the channel diffusion region 2 is self-aligned, and the side surface of the polycrystalline silicon film 11 forming the gate electrode is gently formed by the phosphor glass oxide film 13. This manufacturing method will be described below. First, after the cell isolation diffusion layer 14 is formed, the gate insulating film 4, which is a thin oxide film, is formed in the cell region of the N-type silicon semiconductor substrate 1 by 400 to 100.
It is formed by thermal oxidation of about 0 angstrom. The semiconductor substrate 1 is formed on an N ⁺ -type semiconductor substrate (not shown) by epitaxial growth or the like. The semiconductor substrate 1 serves as a drain region of a vertical MOSFET, and the drain electrode is an N ⁺ -type under N-type (not shown). Is taken out from the lower part of the semiconductor substrate. Next, a polycrystalline silicon film is grown on the entire surface by CVD to a thickness of several thousand angstroms,
By depositing phosphorus, which is an N-type impurity, N-type is doped. Then, a non-doped silicon oxide film 12 is similarly grown thereon by low pressure LPCVD to a thickness of about several thousand angstroms. Then, a photoresist is applied over the entire surface to transfer the gate electrode pattern, and the non-doped silicon oxide film 12 and the polycrystalline silicon film 11 are photoetched to form openings. FIG. 2 is a sectional view of this step.

Next, boron is ion-implanted by self-alignment using the oxide film 12 having the gate electrode pattern and the polycrystalline silicon film 11 as a mask. Then, by heat treatment, boron is diffused to form a P-type channel diffusion region 2. Then, a photoresist is applied, and a source diffusion mask pattern is exposed and developed to form a resist pattern, and a source region 3 is formed by using the photoresist and the polycrystalline silicon film 11 and the non-doped oxide film 12 to be the gate electrode as masks. Ion implantation of phosphorus is performed. Then, after removing the photoresist, a phosphorus glass oxide film 13, which is a phosphorus-doped oxide film, is deposited on the entire surface of the semiconductor substrate and reflowed. This phosphorous glass oxide film is formed by atmospheric pressure CVD etc.
Grow about a micron. Reflow is 900 ℃ -100
This is carried out at a temperature of 0 ° C., whereby the phosphorous glass oxide film 13 is embedded in the steep non-doped oxide film 12 and the end portion of the gate electrode of the polycrystalline silicon film 11. At the same time, the aforementioned ion-implanted high-concentration phosphorus is diffused into the channel diffusion region 2 and the source diffusion region 3 is formed in the vicinity of the gate electrode. FIG. 3 shows a sectional view of this step.

Next, the phosphor glass oxide film 13 is formed on the entire surface,
Etching is performed by anisotropic dry etching using Ar + CF4 + CHF3 gas. The etching is advanced beyond the gate insulating film 4 to the surface of the semiconductor substrate 1, that is, where the silicon base is exposed. At this time, the non-doped oxide film 1
Since 2 has a smaller etching rate than the phosphorus glass oxide film, the non-doped oxide film is not etched and serves to protect the polycrystalline silicon film. By this etching, the contact openings of the source diffusion region 3 and the channel diffusion region 2 are formed by self-alignment. Since the reflowed phosphorus glass oxide film 13 is entirely etched, the phosphorus glass oxide film 13 remains on the side surface of the gate electrode 5, and an interlayer insulating film having a gentle slope is formed. FIG. 4 is a sectional view of this step. Then, an aluminum film is formed on the entire surface by vapor deposition or the like, a photoresist is applied on the entire surface, and an aluminum electrode 9 is formed by photoetching with an electrode pattern. Through the above steps, FIG.
The vertical MOSFET shown in is completed.

[0012]

In the present invention, the contact opening is
A contact opening is formed by self-alignment by depositing a phosphorus glass oxide film on the entire surface of the semiconductor substrate, reflowing, and etching the entire surface of the phosphorus glass oxide film until the surface of the silicon semiconductor substrate on the source diffusion region is exposed. There is. Therefore, the conventional steps of applying photoresist for contact opening and mask alignment are eliminated, and the need for mask alignment is eliminated, so that the problem of mask alignment deviation is eliminated, the processing accuracy is improved, and the product yield is improved. Furthermore, since the phosphorus glass oxide film is reflowed and the phosphorus glass oxide film is removed by etching the entire surface,
The interlayer insulation film was formed gently on the side surface of the gate electrode, and the step coverage of the aluminum electrode was significantly improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process of a vertical MOSFET according to an embodiment of the present invention.

FIG. 2 is a sectional view of a manufacturing process of a vertical MOSFET according to an embodiment of the present invention.

FIG. 3 is a sectional view of a manufacturing process of a vertical MOSFET according to an embodiment of the present invention.

FIG. 4 is a sectional view of a manufacturing process of a vertical MOSFET according to an embodiment of the present invention.

FIG. 5 is a sectional view of a conventional vertical MOSFET.

Claims (2)

[Claims] 1. A step of depositing a gate insulating film on a semiconductor substrate, a step of depositing a polycrystalline silicon film on the gate insulating film, and a step of depositing a non-doped oxide film on the polycrystalline silicon film. A step of photoetching the polycrystalline silicon film and a non-doped oxide film so as to form a gate electrode pattern, a step of forming a channel diffusion region by self-alignment using the gate electrode pattern as a mask, a photoresist and the gate Forming a source diffusion region using the electrode as a mask, depositing a phosphorus-doped oxide film on the semiconductor substrate and reflowing it, and covering the entire surface of the phosphorus-doped oxide film and the gate insulating film until the surface of the semiconductor substrate is exposed. The step of forming a contact opening by removing it by etching, and removing the aluminum film over the entire semiconductor substrate. A method of manufacturing an insulated gate field effect transistor, comprising the steps of: depositing on a surface and forming an aluminum electrode by photoetching. 2. The method of manufacturing an insulated gate field effect transistor according to claim 1, wherein the entire surface etching is anisotropic etching.