JPH0555567A - Manufacture of tft matrix - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing a TFT matrix having a large process margin without problem such as a shift of a threshold value of TFT characteristics, deterioration of a breakdown voltage, etc., by using a film forming method having high productivity with a static electricity. CONSTITUTION:A gate electrode 8 connected to a gate bus 2 is formed of opaque metal on a transparent insulating board 1, a gate insulating film 4, a semiconductor active layer 5 and a channel protective film 6 are sequentially laminated on the entire board 1, the entire film 6 is covered with a positive type resist film 7, the entire film 7 is exposed from its rear surface, and the channel protective film is etched with the pattern of the film 7 as a mask. A semiconductor junction layer 8, source.drain metal films 9, and a drain bus material 10 are sequentially laminated on the entire board 1, the bus material 10 is etched with the film 11 as a mask, the films 7, 11 are removed, the layer 8, the films 9 are lifted OFF, and a source electrode 13 and a drain electrode 14 are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a TFT matrix of a TFT matrix type color liquid crystal panel used as a laptop personal computer or a wall TV.

The display quality of the TFT matrix is CR.
Although it is being recognized that the performance as a T-substitute can be secured, the yield during the manufacturing process such as disconnection, short circuit, and TFT characteristic distribution becomes an important industrial problem.

Static electricity during the process has a great influence on a short circuit, a TFT characteristic distribution and the like, and it is particularly important to select a process after the TFT section has formed a device form.

[0004]

2. Description of the Related Art FIGS. 4 and 5 are explanatory views of a conventional example, in which a left side is a plan perspective view and a right side is a cross sectional view cut along a line AA 'of the plan perspective view in the order of steps. ..

In the figure, 15 is a transparent insulating substrate, 16 is a gate bus, 17 is a gate electrode, 18 is a gate insulating film, 19 is a semiconductor active layer, 20 is a channel protective film, 21 is a positive resist film, and 22 is a semiconductor. Bonding layer, 23 is source / drain metal film,
24 is the source electrode, 25 is the drain electrode, 26 is the drain bath material, 27 is the drain bath, and 28 is erosion.

Conventionally, the alignment accuracy of the gate electrode 17 of the TFT and the source / drain electrodes 24, 25 is large by using a transparent insulating substrate
In the self-alignment type TFT by the exposure method from the back surface of the substrate, which was used to secure 15 as well, the semiconductor junction layer 22 and the source / drain metal film 23 are formed to a thickness that facilitates lift-off as shown in FIG. Retaining, lift-off, etching processing into the shape of the source electrode 24 and the drain electrode 25, and then forming the drain bus 27 again, or, as shown in FIG. 5, the semiconductor junction layer 22, the source / drain metal. Following the film 23, the drain bus material 26 was formed, and then lift-off was performed.

[0007]

Therefore, according to the first conventional method shown in FIG. 4, the source / drain electrodes 24 and 25 of the TFTs arranged on the substrate are separated from each other by hundreds of thousands to millions. Aluminum as drain bath material 26 (A
l) The film formation on the entire surface is performed by the sputtering method or the electron beam evaporation method. Therefore, the threshold value shift of TFT characteristics and the breakdown voltage deterioration that occur when the film formation method with static electricity such as sputtering and electron beam evaporation are used. Problems arise.

On the other hand, when the resistance heating vapor deposition method is used as the Al film forming method, the influence of static electricity can be avoided, but there are problems in that the productivity is poor and the reproducibility of the film quality is poor. Therefore, if the conventional second film forming method, which is accompanied by the generation of static electricity but has good productivity, is used before the separate molding of the source / drain electrodes of the TFT, as shown in FIG. Since the thick films 22, 23, and 26 containing the material are lifted off, the process becomes unstable, and Al of the drain bus material 26 at the lift-off edge is eroded 28 by the resist stripping solution used during the lift-off. is there.

In view of the above points, the present invention is accompanied by static electricity. However, while using the conventional film forming method with good productivity, there is no problem such as threshold shift of TFT characteristics and deterioration of breakdown voltage, and the process It is an object to provide a manufacturing process of a TFT matrix having a large margin.

[0010]

1, 2 and 3 are explanatory views of the principle of the present invention, in which a left side is a plane perspective view and a right side is a sectional view taken along line AA 'of the plane perspective view. It is schematically shown in the order of steps.

In the figure, 1 is a transparent insulating substrate, 2 is a gate bus, 3 is a gate electrode, 4 is a gate insulating film, 5 is a semiconductor active layer, 6 is a channel protective film, 7 is a positive resist film, and 8 is a semiconductor. Bonding layer, 9 is a source / drain metal film,
10 is a drain bus material, 11 is a resist film, 12 is a drain bus, 13 is a source electrode, and 14 is a drain electrode.

In order to solve the above-mentioned problems, the source / drain electrodes and the drain bus material for forming the matrix structure are formed on the entire surface of the substrate by the semiconductor junction layer, or
By adopting a step of forming a film while leaving almost all over the surface, and then performing patterning and etching, the semiconductor bonding layer having sufficient conductivity to release static electricity has an effect of removing static electricity.

Further, since the semiconductor junction layer which is the first layer can be formed with extremely weak power, there is no influence of static electricity. That is, an object of the present invention is to form a gate electrode made of an opaque metal, a gate insulating film, a semiconductor active layer, and a source / drain electrode containing a junction layer semiconductor on a transparent insulating substrate in this order, and a channel protective film on the gate electrode. In a method of manufacturing a TFT matrix semiconductor device having a lower gate stagger type TFT having a switching element as a switching element, as shown in FIG.
The step of forming the gate electrode 3 connected to the gate bus 2 with an opaque metal, and as shown in FIG. 1B, the gate insulating film 4 is formed on the entire surface of the transparent insulating substrate 1 so as to cover the gate electrode 3. A step of sequentially laminating the semiconductor active layer 5 and the channel protection film 6, and as shown in FIG. 1C, a positive resist film 7 is applied on the entire surface of the channel protection film 6, and the gate electrode 3 is used as a mask. Then, the whole surface of the positive type resist film 7 is exposed from the rear surface of the transparent insulating substrate 1, and after development, the channel protective film 6 is etched by using the formed positive type resist film 7 pattern as a mask. As shown in FIG. 2D, a step of sequentially laminating the semiconductor junction layer 8, the source / drain metal film 9, and the drain bus material 10 on the entire surface of the transparent insulating substrate 1, and as shown in FIG. , Using the resist film 11 as a mask, 2 (f), the positive resist film 7 and the resist film 11 are removed, and the semiconductor bonding layer 8 formed on the channel protection film 6 is removed. The step of lifting off the source / drain metal film 9 and patterning the source / drain metal film 9 to form the source electrode 12 and the drain electrode 13;
In the second method of the present invention, the steps from FIG. 1 (a) to FIG. 1 (c) are exactly the same as those of the first invention, but subsequently,
As shown in FIG. 3 (g), on the entire surface of the transparent insulating substrate 1,
The semiconductor junction layer 8 and the source / drain metal film 9 are sequentially formed,
As shown in FIG. 3H, the positive resist film 7 is removed and the semiconductor junction layer 8 and the source / drain metal film 9 formed on the channel protection film 6 are lifted off. The drain bus material 10 on the entire surface of the transparent insulation sheet 1.
As shown in FIG. 3I, the drain bus material 10 is etched by using the resist film 11 as a mask, and the resist film of the etching mask is not shown. -Drain metal film 9 is patterned to form source electrode 13 and drain electrode 14
In addition, the semiconductor active layer 5 is made of a-Si having a thickness of 2,000 Å or less, and the semiconductor junction layer 8 is made of phosphorus-doped a-Si having a thickness of 2,000 Å or less. Thus, the drain bus material 10 is made of Al or a metal film containing Al as a main component.

[0014]

In the present invention, the semiconductor junction layer, which can be formed with extremely weak power and has a sufficient conductivity to release static electricity, is used as the static electricity removing film, so that the source / drain and drain bus materials can be formed. It is possible to provide a manufacturing process of a TFT matrix having a large process margin without problems such as threshold shift of TFT characteristics and deterioration of withstand voltage while using a method with good productivity, which involves static electricity in film formation.

[0015]

1 and 2 are explanatory views of the principle of the present invention and schematic sectional views in order of steps of the first embodiment, and FIG. 3 is an explanatory view of principle of the present invention and schematic sectional views in order of process of the second embodiment. Is.

A first embodiment of the present invention will be described in the order of steps with reference to FIGS. As shown in FIG. 1 (a),
A titanium (Ti) film is sputtered on the transparent glass substrate 1 to a thickness of 800 Å and patterned to form the gate electrode 3 connected to the gate bus 2.

As shown in FIG. 1 (b), a transparent glass substrate 1 is set on the entire surface of the transparent glass substrate 1 by using a load-lock type plasma CVD apparatus. Then, the transparent glass substrate 1 is transferred to the first film forming chamber, and silane (SiH ₄ ) 50 sccm, ammonia (NH ₃ ) 100 sccm, nitrogen (N ₂ ) 500 sccm are transferred from each process gas container. , Hydrogen (H ₂ ) 3
00 sccm of quaternary process gas was introduced from the gas inlet through the gas shower into the chamber, and the frequency was 13.56 MHz.
Under the conditions of an output of 400 W and an internal pressure of chamber 6 of 100 Pa, silicon nitride (Si
N: H) film is formed to a thickness of 3,000 Å.

Next, the transparent glass substrate 1 is transferred to the second film forming chamber, and amorphous silicon (a-Si) is used as the semiconductor active layer 5.
The layer is formed from the container of each process gas at
A binary process gas of H ₄ 200 sccm and H ₂ 800 sccm was introduced into the chamber through the gas shower from the gas inlet.
A thickness of 150 Å is formed on the transparent glass substrate 1 under the conditions of a frequency of 13.56 MHz, an output of 80 W and a chamber pressure of 100 Pa.

Further, the transparent glass substrate 1 is transferred to the third film forming chamber, and as the channel protective film 6, at a substrate temperature of 200 ° C., SiH ₄ 50 sccm, laughter (N ₂ 0) 2,000 from each process gas container.
The binary process gas of sccm was introduced into the chamber through the gas shower from the gas inlet, and the frequency was 13.56MHz, output.
Under the conditions of 400 W and chamber pressure of 100 Pa, a SiO ₂ film is laminated on the transparent glass substrate 1 to a thickness of 1,300 Å.

As shown in FIG. 1C, a positive resist film 7 is applied on the entire surface of the channel protection film 6, and the gate electrode 3 is formed.
The entire surface of the positive resist film 7 is exposed from the rear surface of the transparent glass substrate 1 using the mask as a mask, and after development, pattern etching of the channel protective film 6 is performed using the formed positive resist film 7 pattern as a mask.

As shown in FIG. 2 (d), a phosphorus-doped a-Si layer is used as a semiconductor bonding layer 8 on the entire surface of the transparent glass substrate 1 using a load lock plasma CVD apparatus, and the substrate temperature is set to 120 ° C. in a heating chamber. The transparent glass substrate 1 set inside is heated by a lamp heater and then moved to the film forming chamber. From each process gas container, SiH ₄ 200sccm, H ₂ 800sccm, PH ₃ 3
The sccm ternary process gas was introduced into the chamber through the gas shower from the gas inlet, and the frequency was 13.56 MHz and the output was 2
Under the conditions of 00 W and chamber pressure of 700 mTorr, a 500 Å thickness was formed on the transparent glass substrate 1, a Ti film was formed as a source / drain metal film 9 to a 500 Å thickness, and a drain bus material 10 was formed.
As a result, an Al film is sequentially laminated by DC sputtering to a thickness of 6,000 Å.

Heating during film formation in plasma CVD is performed by a sheath heater which is always set in the film formation chamber. Figure 2
As shown in (e), the drain bus material 10 is pattern-etched using the resist film 11 as a mask to form the drain bus 12.

As shown in FIG. 2F, the positive resist film 7 and the resist film 11 are removed, and the semiconductor junction layer 8 and the source / drain metal film 9 formed on the channel protection film 6 are removed. The source / drain metal film 9 is lifted off to pattern the source / drain metal film 9.
Forming 14

Next, a second embodiment of the present invention will be described with reference to FIG. The first steps from FIG. 1 (a) to FIG. 1 (c) are the same as those in the first embodiment of the present invention, and will be omitted.

After the step of FIG. 1C, as shown in FIG. 3G, the semiconductor bonding layer 8 is formed on the entire surface of the transparent insulating substrate 1.
As a result, a phosphorus-doped a-Si layer having a thickness of 500 Å and a Ti film as a source / drain metal film 9 having a thickness of 500 Å are sequentially laminated in the same manner as in the first embodiment.

As shown in FIG. 3H, the positive resist film 7 is removed, and the semiconductor junction layer 8 and the source / drain metal film 9 formed on the channel protection film 6 are lifted off.
Al as the drain bus material 10 on the entire surface of the transparent glass substrate 1
The film is coated to a thickness of 6,000Å by sputtering or electron beam evaporation.

As shown in FIG. 3I, using the resist film 11 as a mask, the drain bus material 10 is etched and the source / drain metal film 9 is patterned to form a source electrode 13 and a drain electrode 14. ..

[0028]

As described above, according to the present invention,
Providing a method for manufacturing a TFT matrix that has a large process margin without problems such as threshold shift of TFT characteristics and deterioration of breakdown voltage by using a method with good productivity that accompanies static electricity in film formation of source / drain and drain bus materials Yes, TF
It greatly contributes to the quality improvement of the T matrix.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention (No. 1)

FIG. 2 is an explanatory diagram of the principle of the present invention (No. 2)

FIG. 3 is an explanatory diagram of the principle of the present invention (No. 3)

FIG. 4 is an explanatory diagram of a conventional example (No. 1)

FIG. 5 is an explanatory diagram of a conventional example (No. 2)

[Explanation of symbols]

 1 transparent insulating substrate 2 gate bus 3 gate electrode 4 gate insulating film 5 semiconductor active layer 6 channel protective film 7 positive resist film 8 semiconductor junction layer 9 source / drain metal film 10 drain bus material 11 resist film 12 drain bus 13 source electrode 14 Drain electrode

Front page continuation (72) Inventor Yuji Murata 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Junichi Watanabe 1015, Kamedotachu, Nakahara-ku, Kawasaki, Kanagawa Prefecture (72) Invention Seito Sato 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (4)

[Claims] 1. A gate electrode made of an opaque metal, a gate insulating film, a semiconductor active layer, a source / drain electrode containing a junction layer semiconductor are sequentially formed on a transparent insulating substrate, and a channel protective film is formed on the gate electrode. In a method of manufacturing a TFT matrix semiconductor device using a gate stagger type thin film transistor (TFT) as a switching element, a step of forming a gate electrode (3) connected to a gate bus (2) with an opaque metal on a transparent insulating substrate (1) And a gate insulating film (4), a semiconductor active layer (5), a channel protective film covering the entire surface of the transparent insulating substrate (1) covering the gate electrode (3).
A step of sequentially stacking (6), a positive resist film (7) is applied on the entire surface of the channel protective film (6), and the back surface of the transparent insulating substrate (1) is formed by using the gate electrode (3) as a mask. Exposing the entire surface of the positive resist film (7), and developing and then etching the channel protective film (6) using the formed positive resist film (7) pattern as a mask; and the transparent insulating substrate. (1) A step of sequentially laminating the semiconductor junction layer (8), the source / drain metal film (9), and the drain bus material (10) on the entire upper surface, and using the resist film (11) as a mask, the drain bus Material (1
(0) and the resist film (11), the positive resist film (7) is removed at the same time, and the semiconductor bonding layer (8) formed on the channel protective film (6), A step of lifting off the source / drain metal film (9) and patterning the source / drain metal film (9) to form a source electrode (13) and a drain electrode (14). Method for manufacturing TFT matrix. 2. A gate electrode made of an opaque metal, a gate insulating film, a semiconductor active layer, and a source / drain electrode containing a junction layer semiconductor are sequentially formed on a transparent insulating substrate, and a channel protective film is formed on the gate electrode. In a method of manufacturing a TFT matrix semiconductor device using a gate stagger type thin film transistor (TFT) as a switching element, a step of forming a gate electrode (3) connected to a gate bus (2) with an opaque metal on a transparent insulating substrate (1) And a gate insulating film (4), a semiconductor active layer (5), a channel protective film covering the entire surface of the transparent insulating substrate (1) covering the gate electrode (3).
(6) are sequentially laminated, a positive resist film (7) is applied on the entire surface of the channel protective film (6), and the gate electrode (3) is used as a mask to form a transparent insulating substrate (1). The entire surface of the positive type resist film (7) is exposed from the back surface, and after development, the channel protection film (6) is etched using the formed positive type resist film (7) pattern as a mask, and the transparent insulating film. The step of sequentially stacking the semiconductor junction layer (8) and the source / drain metal film (9) on the entire surface of the substrate (1) and removing the positive type resist film (7) to form the channel protective film.
(6) A step of lifting off the semiconductor junction layer (8) and the source / drain metal film (9) formed on the transparent insulating substrate (1) to cover the entire surface of the transparent insulating substrate (1) with a drain bus material (10), Using the resist film (11) as a mask, the drain bus material (1
0) is etched and the source / drain metal film (9) is patterned to form a source electrode (13) and a drain electrode (14).
Matrix manufacturing method. 3. The semiconductor active layer (5) is amorphous silicon having a thickness of 200 nm or less, and the semiconductor bonding layer.
3. The T according to claim 1, wherein (8) is made of phosphorus-doped amorphous silicon having a thickness of 200 nm or less.
Method of manufacturing FT matrix. 4. The method of manufacturing a TFT matrix according to claim 1, wherein the drain bus material (10) is aluminum or a metal film containing aluminum as a main component.