JPH0555567A - Manufacture of tft matrix - Google Patents

Manufacture of tft matrix

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Publication number
JPH0555567A
JPH0555567A JP21402391A JP21402391A JPH0555567A JP H0555567 A JPH0555567 A JP H0555567A JP 21402391 A JP21402391 A JP 21402391A JP 21402391 A JP21402391 A JP 21402391A JP H0555567 A JPH0555567 A JP H0555567A
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Japan
Prior art keywords
film
drain
source
channel protective
layer
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JP21402391A
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Japanese (ja)
Inventor
Ikuo Daiki
Hirayuki Iida
Yuji Murata
Yasuhiro Nasu
Kiyotake Sato
Junichi Watabe
育夫 代木
精威 佐藤
祐司 村田
純一 渡部
安宏 那須
平志 飯田
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Fujitsu Ltd
富士通株式会社
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Priority to JP21402391A priority Critical patent/JPH0555567A/en
Publication of JPH0555567A publication Critical patent/JPH0555567A/en
Application status is Withdrawn legal-status Critical

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Abstract

PURPOSE:To provide a method for manufacturing a TFT matrix having a large process margin without problem such as a shift of a threshold value of TFT characteristics, deterioration of a breakdown voltage, etc., by using a film forming method having high productivity with a static electricity. CONSTITUTION:A gate electrode 8 connected to a gate bus 2 is formed of opaque metal on a transparent insulating board 1, a gate insulating film 4, a semiconductor active layer 5 and a channel protective film 6 are sequentially laminated on the entire board 1, the entire film 6 is covered with a positive type resist film 7, the entire film 7 is exposed from its rear surface, and the channel protective film is etched with the pattern of the film 7 as a mask. A semiconductor junction layer 8, source.drain metal films 9, and a drain bus material 10 are sequentially laminated on the entire board 1, the bus material 10 is etched with the film 11 as a mask, the films 7, 11 are removed, the layer 8, the films 9 are lifted OFF, and a source electrode 13 and a drain electrode 14 are formed.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は,ラップトップパソコンや壁掛けTVとして用いられるTFTマトリクス型カラー液晶パネルのTFTマトリクスの製造方法に関する。 The present invention relates to a process for the production of TFT matrix of TFT-matrix color liquid crystal panel to be used as a laptop personal computer or a wall-mounted TV.

【0002】TFTマトリクスは,その表示品質はCR [0002] The TFT matrix, the display quality is CR
T代替としての性能を確保できそうなことが認知されつつあるが,断線や短絡,TFT特性分布などその製造工程中の歩留りが産業上重要な問題となる。 It likely be ensured the performance of the T alternative is being recognized, the disconnection or short circuit, the yield on industrial important issue during the production process such as a TFT characteristic distribution.

【0003】工程中の静電気は短絡,TFT特性分布などに大きな影響を及ぼし,特にTFT部が素子形態をなした後の工程選択が重要である。 [0003] static electricity in process short, have a major impact on such TFT characteristic distribution, it is particularly important step selection after the TFT portion is without a device embodiment.

【0004】 [0004]

【従来の技術】図4,図5は従来例の説明図であり,左側に平面透視図,右側は平面透視図のA─A'ラインでカットした断面図を工程順に模式的に示してある。 BACKGROUND ART FIG. 4, FIG. 5 is an explanatory view of a conventional example, a perspective plan view on the left, right is shown a sectional view cut A - A 'line of a perspective plan view in the order of steps schematically .

【0005】図において,15は透明絶縁基板,16はゲートバス,17はゲート電極,18はゲート絶縁膜,19は半導体活性層,20はチャネル保護膜,21はポジ型レジスト膜,22は半導体接合層,23はソース・ドレイン金属膜, [0005] In Figure, the transparent insulating substrate 15, 16 denotes a gate bus, 17 denotes a gate electrode, 18 denotes a gate insulating film, 19 denotes a semiconductor active layer, 20 is a channel protective film, 21 is a positive resist film, 22 is a semiconductor bonding layer, 23 is a source-drain metal layer,
24はソース電極, 25はドレイン電極, 26はドレインバス材料, 27はドレインバス,28は浸食である。 24 denotes a source electrode, 25 drain electrode, 26 drain bus materials, 27 drain bus, 28 is eroded.

【0006】従来,TFTのゲート電極17とソース・ドレイン電極24,25 の合わせ精度を大面積の透明絶縁基板 Conventionally, a transparent insulating substrate having a large area of ​​the alignment accuracy of the gate electrode 17 of the TFT and the source and drain electrodes 24 and 25
15においても確保するために用いていた基板裏面からの露光法による自己整合型TFTでは,図4に示すように半導体接合層22とソース・ドレイン金属膜23をリフトオフし易い厚さの成膜にとどめ,リフトオフし,ソース電極24, ドレイン電極25の形状にエッチング加工してから,改めて,ドレインバス27の形成を行う方法,或いは,図5に示すように,半導体接合層22,ソース・ドレイン金属膜23に引続き,ドレインバス材料26まで成膜した後に,リフトオフする方法があった。 In a self-aligned TFT according to the exposure method from the rear side of the substrate has been employed in order to ensure also in 15, the semiconductor junction layer 22 and the source-drain metal film 23 are lifted off easily thick film formation as shown in FIG. 4 kept, and lifted off, the source electrode 24, after etching to form the drain electrode 25, again, a method of performing the formation of the drain bus 27, or, as shown in FIG. 5, the semiconductor junction layer 22, the source-drain metal following film 23, after forming up to the drain bus material 26, there is a method of lift-off.

【0007】 [0007]

【発明が解決しようとする課題】従って,図4に示す従来の第1の方法では,基板上に数十万〜数百万個配置されているTFTの各ソース・ドレイン電極24,25 が分離された後にドレインバス材料26としてのアルミニウム(A [SUMMARY OF THE INVENTION Thus, in a first method of the prior art shown in FIG. 4, the source and drain electrodes 24 and 25 of the TFT is several hundred thousand to several million disposed on a substrate separate aluminum (a as the drain bus material 26 after it has been
l)の全面成膜をスパッタ法, 或いは, 電子ビーム蒸着法により行うので, スパッタ, 電子ビーム蒸着等の静電気を伴う成膜法を用いた場合に起こるTFT特性のしきい値シフトや耐圧劣化等の問題が生じる。 Sputtering on the entire surface deposition of l), or an electron is performed by a beam evaporation, sputtering, electron beam threshold shifts and breakdown voltage of the TFT characteristics occurring when using deposition method with electrostatic deposition or the like, etc. It occurs problems.

【0008】一方,Alの成膜法に抵抗加熱蒸着法を用いると,静電気の影響は避けられるが,生産性が悪く,また,膜質の再現性が悪いといった問題がある。 [0008] On the other hand, the use of a resistance heating evaporation method to the film formation method of Al, but the influence of the static electricity is avoided, poor productivity, also, the film quality of reproducibility and there is a problem such as bad. そのため,静電気の発生をともなうけれども,しかし,生産性の良い従来の第2の成膜法をTFTのソース・ドレイン電極の分離成形の前に用いようとすると,図5に示すように,ドレインバス材料を含む厚い膜22,23,26をリフトオフするため,工程が不安定となり,また,リフトオフ時に用いるレジスト剥離液によって,リフトオフエッジ部のドレインバス材料26のAlが浸食28されるという問題点がある。 Therefore, although accompanied by generation of static electricity, however, the second film forming method good conventional productivity and are to be used prior to separation forming the source and drain electrodes of the TFT, as shown in FIG. 5, the drain bus for lifting off the thick film 22, 23, 26 containing a material, the process becomes unstable and by resist stripping solution used during the lift-off, a problem that Al of drain bus material 26 of the lift-off edge portion is eroded 28 is there.

【0009】本発明は,上記の点を鑑み,静電気をともなうが, しかし, 生産性の良い従来の成膜法を用いながら,TFT特性のしきい値シフトや耐圧劣化等の問題がなく,プロセスマージンも大きいTFTマトリクスの製造工程を提供することを目的とする。 [0009] The present invention has been made in view the above points, but accompanied by static electricity, but while using good conventional film formation method productivity, no problems such as threshold shifts and breakdown voltage of the TFT characteristics, the process and to provide also a large TFT matrix manufacturing process margin.

【0010】 [0010]

【課題を解決するための手段】図1,図2,図3は本発明の原理説明図であり,左側に平面透視図,右側は平面透視図のA─A'ラインでカットした断面図を工程順に模式的に示してある。 Means for Solving the Problems] 1, 2, 3 is an explanatory view of the principle of the present invention, a perspective plan view on the left, a cross-sectional view cut right at A - A 'line of a perspective plan view It is schematically shown in order of processes.

【0011】図において,1は透明絶縁基板,2はゲートバス,3はゲート電極,4はゲート絶縁膜,5は半導体活性層,6はチャネル保護膜,7はポジ型レジスト膜,8は半導体接合層,9はソース・ドレイン金属膜, [0011] In FIG, 1 is a transparent insulating substrate, 2 denotes a gate bus, a gate electrode 3, the gate insulating film 4, 5 the semiconductor active layer, the channel protective film 6, 7 positive resist film, 8 denotes a semiconductor bonding layer, the source-drain metal film 9,
10はドレインバス材料, 11はレジスト膜, 12はドレインバス, 13はソース電極, 14はドレイン電極である。 10 drain bus materials, 11 resist film, 12 denotes a drain bus, the source electrode 13, 14 is a drain electrode.

【0012】上記の問題点を解決するためには, マトリクス構成とするためのソース・ドレイン電極及びドレインバス材料を半導体接合層が基板表面に全面,或いは, [0012] In order to solve the above problems, the entire surface to the source and drain electrodes and the drain bus material of the semiconductor junction layer is the substrate surface to a matrix arrangement, or,
ほぼ全面にわたって残した状態で成膜し,後にパターニング,エッチングする工程を採用することで,静電気を逃がすのに十分な導電率を有する半導体接合層が静電気を除去する効果を持つ。 Almost formed, leaving the entire surface, by employing patterning, the step of etching after, have the effect of semiconductor junction layers having sufficient conductivity to dissipate static electricity discharge any static electricity.

【0013】また,第一層目となる半導体接合層の成膜時は極弱いパワーで成膜可能なため,静電気の影響がないことを利用できる。 Further, since the time of forming the first layer and comprising a semiconductor junction layer can be deposited in very weak power can be used that there is no influence of static electricity. 即ち,本発明の目的は,透明絶縁基板上に不透明金属からなるゲート電極,ゲート絶縁膜,半導体活性層,接合層半導体を含むソース・ドレイン電極の順に膜形成され,ゲート電極上部にチャネル保護膜を有する下ゲートスタガー型TFTをスイッチング素子とするTFTマトリクス半導体装置の製造方法において,図1(a)に示すように,透明絶縁基板1上に, It is an object of the present invention, a gate electrode made of an opaque metal to a transparent insulating substrate, a gate insulating film, a semiconductor active layer, the bonding layer is film formed in this order of the source and drain electrodes comprising a semiconductor, a gate electrode upper part channel protective film the lower Getosutaga type TFT in the manufacturing method of the TFT matrix semiconductor device according to the switching element, as shown in FIG. 1 (a), on a transparent insulating substrate 1 having,
ゲートバス2に接続したゲート電極3を不透明金属により形成する工程と,図1(b)に示すように,該透明絶縁基板1上全面に,該ゲート電極3を覆って,ゲート絶縁膜4,半導体活性層5,チャネル保護膜6を順次積層する工程と,図1(c)に示すように,該チャネル保護膜6上全面にポジ型レジスト膜7を塗布し, 該ゲート電極3をマスクとして, 該透明絶縁基板1の裏面より該ポジ型レジスト膜7の全面露光を行い, 現像後, 形成されたポジ型レジスト膜7パターンをマスクとして該チャネル保護膜6のエッチングを行う工程と,図2(d)に示すように,該透明絶縁基板1上全面に,該半導体接合層8,ソース・ドレイン金属膜9,ドレインバス材料10を順次積層する工程と,図2(e)に示すように,レジスト膜11をマスクとして, 該 Forming by an opaque metal gate electrode 3 connected to the gate bus 2, as shown in FIG. 1 (b), the transparent insulating substrate 1 over the entire surface, covering the gate electrode 3, the gate insulating film 4, semiconductor active layer 5, a step of sequentially laminating the channel protective film 6, as shown in FIG. 1 (c), a positive resist film 7 is coated on the channel protective film 6 on the entire surface of the gate electrode 3 as a mask performs overall exposure of the transparent insulating the positive resist film 7 from the back surface of the substrate 1, and performing etching of the channel protective film 6 after development, formed a positive resist film 7 pattern as a mask, Figure 2 as shown in (d), the transparent insulating substrate 1 on the entire surface of the semiconductor junction layer 8, the source-drain metal film 9, the step of sequentially laminating the drain bus material 10, as shown in FIG. 2 (e) the resist film 11 as a mask, the レインバス材料10をエッチングする工程と,図2(f)に示すように,該ポジ型レジスト膜7,及びレジスト膜11を除去して, 該チャネル保護膜6上に成膜した該半導体接合層8,ソース・ドレイン金属膜9をリフトオフし,該ソース・ドレイン金属膜9をパターニングして, ソース電極12, 並びに, ドレイン電極13を形成する工程とを含むことにより,また, Etching the Reinbasu material 10, as shown in FIG. 2 (f), the positive resist film 7, and the resist film 11 is removed to the semiconductor junction layer was formed on the channel protective film 6 8 , lifted off the source-drain metal film 9, and patterning the source-drain metal film 9, the source electrode 12, and, by a step of forming a drain electrode 13, also,
本発明の第2の方法では,図1(a)から図1(c)までの工程は,第1の発明と全く同様であるが,続いて, In the second method of the present invention, the steps from FIGS. 1 (a) to FIG. 1 (c), is exactly the same as the first invention, subsequently,
図3(g)に示すように,該透明絶縁基板1上全面に, As shown in FIG. 3 (g), the transparent insulating substrate 1 over the entire surface,
該半導体接合層8,ソース・ドレイン金属膜9を順次, The semiconductor junction layer 8, the source-drain metal film 9 successively,
積層する工程と,図3(h)に示すように,該ポジ型レジスト膜7を除去して, 該チャネル保護膜6上に成膜した該半導体接合層8,ソース・ドレイン金属膜9をリフトオフし,該透明絶縁記1上全面にドレインバス材料10 Liftoff laminating, as shown in FIG. 3 (h), to remove the positive resist film 7, the semiconductor junction layer 8 was formed on the channel protective film 6, the source-drain metal film 9 and, drain bus material 10 to the transparent insulation Symbol 1 over the entire surface
を被覆する工程と,図3(i)に示すように,レジスト膜11をマスクとして, 該ドレインバス材料10をエッチングし, 引続きエッチングマスクのレジスト膜を図示していないが,同様に,該ソース・ドレイン金属膜9をパターニングして, ソース電極13, 並びに, ドレイン電極14 A step of coating a, as shown in FIG. 3 (i), the resist film 11 as a mask, the drain bus material 10 is etched, although not continue illustrated resist film of the etching mask, similarly, the source drain metal film 9 is patterned, the source electrode 13, and the drain electrode 14
を形成する工程とを含むことにより,更に,半導体活性層5が 2,000Å以下の厚さのa-Si, また, 半導体接合層8が2,000Å以下の厚さの燐ドープa-Siからなることにより, ドレインバス材料10がAl, または, Alを主成分とする金属膜であることにより達成される。 By including a step of forming a further semiconductor active layer 5 is also less than a thickness of a-Si, 2,000 Å, the semiconductor junction layer 8 is made of phosphorus-doped a-Si in a thickness of less than 2,000 Å Accordingly, the drain bus material 10 Al, or is achieved by a metal film composed mainly of Al.

【0014】 [0014]

【作用】本発明では,極弱いパワーで成膜可能で,しかも,静電気を逃すに十分な導電率を有する半導体接合層を静電気除去膜として利用することにより,ソース・ドレイン及び,ドレインバス材料の成膜に静電気を伴うが生産性の良い方法を用いながら,TFT特性のしきい値シフトや耐圧劣化等の問題がなくプロセスマージンも大きいTFTマトリクスの製造工程を提供できる。 According to the present invention, be formed at a very weak power, moreover, by utilizing the semiconductor junction layer having sufficient conductivity to miss the electrostatic static electricity removing film, the source and drain and the drain bus material while accompanied by a static electricity with a good way productivity in film formation, it can provide a threshold shift and pressure process margin without problems such as deterioration is large TFT matrix manufacturing steps of the TFT characteristics.

【0015】 [0015]

【実施例】図1, 図2は本発明の原理説明図兼第一の実施例の工程順模式断面図,図3は本発明の原理説明図兼第二の実施例の工程順模式断面図である。 EXAMPLES 1, 2 principle diagram and schematic sectional views following step sequence of a first embodiment of the present invention, FIG. 3 is a principle explanatory view and schematic sectional views following step sequence of a second embodiment of the present invention it is.

【0016】本発明の第1の実施例について,図1,図2により工程順に説明する。 [0016] The first embodiment of the present invention, FIG. 1, will be described in the order of steps in FIG. 2. 図1(a)に示すように, As shown in FIG. 1 (a),
透明ガラス基板1上に, チタン(Ti)膜を800 Åの厚さにスパッタし, パターニングして, ゲートバス2に接続したゲート電極3を形成する。 On the transparent glass substrate 1, by sputtering titanium (Ti) film to a thickness of 800 Å, and patterned to form a gate electrode 3 connected to the gate bus 2.

【0017】図1(b)に示すように,透明ガラス基板1上全面に,ロードロック型プラズマCVD装置を用い,まず加熱チャンバでチャンバ内にセットした透明ガラス基板1をランプヒーターにより基板温度300 ℃に加熱し,次に第一成膜室に透明ガラス基板1を移し,各プロセスガスの容器から,シラン(SiH 4 ) 50 sccm, アンモニア(NH 3 ) 100 sccm, 窒素(N 2 ) 500 sccm, 水素(H 2 ) 3 [0017] As shown in FIG. 1 (b), a transparent glass substrate 1 on the entire surface, using a load-lock-type plasma CVD apparatus, a substrate temperature of 300 by the set were transparent glass substrate 1 a lamp heater in the chamber first in the heating chamber ℃ heated to, then transferred to the transparent glass substrate 1 in the first film-chamber, from the container of each of the process gases, silane (SiH 4) 50 sccm, ammonia (NH 3) 100 sccm, nitrogen (N 2) 500 sccm , hydrogen (H 2) 3
00 sccm の四元系プロセスガスをガス導入口よりガスシャワーを通してチャンバ内に導入し, 周波数13.56MHz, The 00 sccm of four-component process gas is introduced into the chamber through a gas shower from the gas inlet, frequency 13.56 MHz,
出力400W,チャンバ6内圧力 100Paの条件で,透明ガラス基板1上にゲート絶縁膜4として窒化シリコン(Si Output 400W, under the conditions of the chamber 6 in the pressure 100 Pa, the silicon nitride on a transparent glass substrate 1 as the gate insulating film 4 (Si
N:H)膜を,3,000 Åの厚さに形成する。 N: H) film is formed to a thickness of 3,000 Å.

【0018】次に,第2成膜室に透明ガラス基板1を移し,半導体活性層5としてアモルファスシリコン(a-Si) Next, the second film forming chamber to transfer the transparent glass substrate 1, the semiconductor active layer 5 as an amorphous silicon (a-Si)
層を基板温度 250℃で,各プロセスガスの容器から,Si The layers at the substrate temperature of 250 ° C., from the container of each process gas, Si
H 4 200 sccm, H 2 800sccm の二元系プロセスガスをガス導入口よりガスシャワーを通してチャンバ内に導入し, H 4 200 sccm, a binary process gas H 2 800 sccm was introduced into the chamber through the gas shower from the gas inlet,
周波数13.56MHz, 出力 80 W,チャンバ内圧力 100Paの条件で,透明ガラス基板1上に 150 Åの厚さに形成する。 Frequency 13.56 MHz, output 80 W, under the conditions of a pressure in a chamber 100 Pa, formed to a thickness of 0.99 Å on the transparent glass substrate 1.

【0019】更に, 第3成膜室に透明ガラス基板1を移し,チャネル保護膜6として, 基板温度 200℃で, 各プロセスガスの容器から,SiH 4 50sccm, 笑気(N 2 0)2,000 Furthermore, transferred to a transparent glass substrate 1 in the third deposition chamber, a channel protective film 6, at a substrate temperature of 200 ° C., from the container of each process gas, SiH 4 50 sccm, laughing gas (N 2 0) 2,000
sccmの二元系プロセスガスをガス導入口よりガスシャワーを通してチャンバ内に導入し, 周波数13.56MHz, 出力 The sccm of binary process gas is introduced into the chamber through a gas shower from the gas inlet, frequency 13.56 MHz, output
400W,チャンバ内圧力 100Paの条件で,透明ガラス基板1上にSiO 2膜を1,300 Åの厚さに積層する。 400W, under the condition of chamber pressure 100 Pa, laminating SiO 2 film in a thickness of 1,300 Å on the transparent glass substrate 1.

【0020】図1(c)に示すように,チャネル保護膜6上全面にポジ型レジスト膜7を塗布し, ゲート電極3 As shown in FIG. 1 (c), a positive resist film 7 is coated on the channel protective film 6 over the entire surface, the gate electrode 3
をマスクとして, 透明ガラス基板1の裏面よりポジ型レジスト膜7の全面露光を行い, 現像後, 形成されたポジ型レジスト膜7パターンをマスクとしてチャネル保護膜6のパターンエッチングを行う。 As a mask to perform overall exposure of the positive resist film 7 from the back surface of the transparent glass substrate 1, a pattern etching of the channel protective film 6 after development, formed a positive resist film 7 pattern as a mask.

【0021】図2(d)に示すように,透明ガラス基板1上全面に,半導体接合層8として燐ドープa-Si層をロードロックプラズマCVD装置を用い,加熱室で基板温度120 ℃にチャンバ内にセットした透明ガラス基板1をランプヒータにより加熱し,次に成膜室に移し, 各プロセスガスの容器から,SiH 4 200sccm, H 2 800sccm,PH 3 3 As shown in FIG. 2 (d), a transparent glass substrate 1 on the entire surface, a phosphorous-doped a-Si layer using a load lock plasma CVD device as the semiconductor junction layer 8, the chamber on the substrate temperature 120 ° C. in a heating chamber set the transparent glass substrate 1 within heated by the lamp heater, then transferred to the deposition chamber, the container of the process gas, SiH 4 200sccm, H 2 800sccm , PH 3 3
sccmの三元系プロセスガスをガス導入口よりガスシャワーを通してチャンバ内に導入し, 周波数13.56MHz,出力2 The ternary process gas sccm was introduced into the chamber through the gas shower from the gas inlet, frequency 13.56 MHz, output 2
00W,チャンバ内圧力700mTorrの条件で,透明ガラス基板1上に500 Åの厚さに形成し, ソース・ドレイン金属膜9としてTi膜を500 Åの厚さに, ドレインバス材料10 00W, under the condition of chamber pressure 700 mTorr, formed to a thickness of 500 Å on the transparent glass substrate 1, a Ti film as the source and drain metal film 9 to a thickness of 500 Å, a drain bus material 10
としてAl膜を6,000 Åの厚さにDCスパッタにより順次積層する。 Sequentially laminated by DC sputtering an Al film to a thickness of 6,000 Å as.

【0022】なお,プラズマCVDの成膜中加熱は,成膜室に常時設定しているシーズヒーターで行う。 [0022] The deposition during the heating of the plasma CVD is carried out in a sheath heater that is always set to the deposition chamber. 図2 Figure 2
(e)に示すように,レジスト膜11をマスクとして, ドレインバス材料10をパターンエッチングしてドレインバス12を形成する。 (E), the resist film 11 as a mask to form a drain bus 12 by pattern etching the drain bus material 10.

【0023】図2(f)に示すように,該ポジ型レジスト膜7,及びレジスト膜11を除去して, チャネル保護膜6上に成膜した半導体接合層8,ソース・ドレイン金属膜9をリフトオフし,該ソース・ドレイン金属膜9をパターニングして, ソース電極13, 並びに, ドレイン電極 As shown in FIG. 2 (f), the positive resist film 7, and the resist film 11 is removed, the semiconductor junction layer 8 was formed on the channel protective film 6, the source-drain metal film 9 lift-off, and patterning the source-drain metal film 9, the source electrode 13, and drain electrode
14を形成する。 14 to the formation.

【0024】次に,本発明の第2の実施例について, 図3により説明する。 Next, a second embodiment of the present invention will be described with reference to FIG. 最初の図1(a)から図1(c)までの工程は,本発明の第1の実施例と全く同様であるため,省略する。 Because the process from the first shown in FIG. 1 (a) to FIG. 1 (c), the is the same as the first embodiment of the present invention, it will be omitted.

【0025】図1(c)の工程に続いて,図3(g)に示すように,透明絶縁基板1上全面に,半導体接合層8 [0025] Following the step of FIG. 1 (c), as shown in FIG. 3 (g), the transparent insulating substrate 1 on the entire surface of the semiconductor junction layer 8
として, 燐ドープa-Si層を500 Åの厚さに,ソース・ドレイン金属膜9としてTi膜を500 Åの厚さに第1の実施例と同様な方法で順次, 積層する。 As a phosphorus-doped a-Si layer to a thickness of 500 Å, successively in the first embodiment a method similar to the Ti film as the source and drain metal film 9 to a thickness of 500 Å, stacked.

【0026】図3(h)に示すように,ポジ型レジスト膜7を除去して,チャネル保護膜6上に成膜した半導体接合層8,ソース・ドレイン金属膜9をリフトオフし, As shown in FIG. 3 (h), by removing the positive resist film 7, the semiconductor junction layer 8 was formed on the channel protective film 6, the source-drain metal film 9 is lifted off,
透明ガラス基板1上全面にドレインバス材料10としてAl Al as the drain bus material 10 on the transparent glass substrate 1 on the entire surface
膜を6,000 Åの厚さにスパッタ法, 或いは, 電子ビーム蒸着法により被覆する。 Sputtering a film thickness of 6,000 Å, or coated by an electron beam evaporation method.

【0027】図3(i)に示すように,レジスト膜11をマスクとして, ドレインバス材料10をエッチングし, ソース・ドレイン金属膜9をパターニングして, ソース電極13並びに, ドレイン電極14を形成する。 As shown in FIG. 3 (i), the resist film 11 as a mask, the drain bus material 10 is etched by patterning the source-drain metal film 9, the source electrode 13 and to form a drain electrode 14 .

【0028】 [0028]

【発明の効果】以上説明したように, 本発明によれば, As described in the foregoing, according to the present invention,
ソース・ドレイン及びドレインバス材料の成膜に静電気を伴うが生産性の良い方法を用い,TFT特性のしきい値シフトや耐圧劣化等の問題がなく,プロセスマージンも大きいTFTマトリクスの製造方法を提供でき,TF Involving static for the film forming source and drain and the drain bus material is used a good way productivity, no problems such as threshold shifts and breakdown voltage of the TFT characteristics, a manufacturing method also process margin large TFT matrix can, TF
Tマトリクスの品質向上に寄与するところが大きい。 Which greatly contributes to the quality improvement of the T matrix.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】 本発明の原理説明図(その1) [1] Principle illustration of the present invention (Part 1)

【図2】 本発明の原理説明図(その2) [Figure 2] a view for describing the principles of the present invention (Part 2)

【図3】 本発明の原理説明図(その3) [Figure 3] a view for describing the principles of the present invention (Part 3)

【図4】 従来例の説明図(その1) [4] Conventional Example illustration (part 1)

【図5】 従来例の説明図(その2) [5] Conventional Example illustration (part 2)

【符号の説明】 DESCRIPTION OF SYMBOLS

1 透明絶縁基板 2 ゲートバス 3 ゲート電極 4 ゲート絶縁膜 5 半導体活性層 6 チャネル保護膜 7 ポジ型レジスト膜 8 半導体接合層 9 ソース・ドレイン金属膜 10 ドレインバス材料 11 レジスト膜 12 ドレインバス 13 ソース電極 14 ドレイン電極 First transparent insulating substrate 2 gate bus 3 gate electrode 4 gate insulating film 5 semiconductor active layer 6 channel protection film 7 positive resist film 8 source-drain metal semiconductor junction layer 9 film 10 drain bus material 11 resist film 12 drain bus 13 source electrode 14 drain electrode

フロントページの続き (72)発明者 村田 祐司 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 渡部 純一 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 佐藤 精威 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 Of the front page Continued (72) inventor Yuji Murata Kawasaki City, Kanagawa Prefecture Nakahara-ku, Kamikodanaka 1015 address Fujitsu within Co., Ltd. (72) inventor Junichi Watanabe Kawasaki City, Kanagawa Prefecture Nakahara-ku, Kamikodanaka 1015 address Fujitsu within Co., Ltd. (72) invention person Sato TadashiTakeshi Kanagawa Prefecture, Nakahara-ku, Kawasaki, Kamikodanaka 1015 address Fujitsu within Co., Ltd.

Claims (4)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 透明絶縁基板上に不透明金属からなるゲート電極,ゲート絶縁膜,半導体活性層,接合層半導体を含むソース・ドレイン電極の順に膜形成され,ゲート電極上部にチャネル保護膜を有する下ゲートスタガー型薄膜トランジスタ(TFT)をスイッチング素子とするTFTマトリクス半導体装置の製造方法において, 透明絶縁基板(1) 上に, ゲートバス(2) に接続したゲート電極(3) を不透明金属により形成する工程と, 該透明絶縁基板(1) 上全面に,該ゲート電極(3) を覆って,ゲート絶縁膜(4),半導体活性層(5),チャネル保護膜 1. A gate electrode made of an opaque metal to a transparent insulating substrate, a gate insulating film, a semiconductor active layer, are film formed in this order of the source and drain electrodes comprising a bonding layer semiconductor, under which a channel protective film on the gate electrode upper Getosutaga type thin film transistors (TFT) in the manufacturing method of the TFT matrix semiconductor device according to a switching element, a transparent insulating on the substrate (1), gate bus forming by an opaque metal gate electrode connected to (2) (3) If, on the transparent insulating substrate (1) on the entire surface, covering the gate electrode (3), a gate insulating film (4), the semiconductor active layer (5), the channel protective film
    (6)を順次積層する工程と, 該チャネル保護膜(6) 上全面にポジ型レジスト膜(7) を塗布し, 該ゲート電極(3) をマスクとして, 該透明絶縁基板(1) の裏面より該ポジ型レジスト膜(7) の全面露光を行い, 現像後, 形成されたポジ型レジスト膜(7) パターンをマスクとして該チャネル保護膜(6) のエッチングを行う工程と, 該透明絶縁基板(1) 上全面に,該半導体接合層(8), ソース・ドレイン金属膜(9),ドレインバス材料(10)を順次, 積層する工程と, レジスト膜(11)をマスクとして, 該ドレインバス材料(1 A step of sequentially stacking (6), a positive resist film (7) is applied to the channel protective film (6) on the entire surface of the gate electrode (3) as a mask, the back surface of the transparent insulating substrate (1) more performs overall exposure of the positive resist film (7), a step of etching of the channel protective film (6) after the development, the formed positive resist film (7) pattern as a mask, the transparent insulating substrate (1) on the entire surface, the semiconductor junction layer (8), the source-drain metal layer (9), the drain bus material (10) sequentially laminating, a resist film (11) as a mask, the drain bus material (1
    0)をエッチングする工程と, 該レジスト膜(11)と同時に,該ポジ型レジスト膜(7) を除去して, 該チャネル保護膜(6) 上に成膜した該半導体接合層(8),ソース・ドレイン金属膜(9) をリフトオフし,該ソース・ドレイン金属膜(9) をパターニングして, ソース電極(13), 並びに, ドレイン電極(14)を形成する工程とを含むことを特徴とするTFTマトリクスの製造方法。 0) etching the, simultaneously with the resist film (11), the positive resist film (7) is removed to the semiconductor junction layer formed on the channel protective film (6) (8), the source-drain metal layer (9) is lifted off, and then patterning the source-drain metal film (9), a source electrode (13), as well as, and characterized in that it comprises a step of forming a drain electrode (14) TFT matrix method of manufacturing to.
  2. 【請求項2】 透明絶縁基板上に不透明金属からなるゲート電極,ゲート絶縁膜,半導体活性層,接合層半導体を含むソース・ドレイン電極の順に膜形成され,ゲート電極上部にチャネル保護膜を有する下ゲートスタガー型薄膜トランジスタ(TFT)をスイッチング素子とするTFTマトリクス半導体装置の製造方法において, 透明絶縁基板(1) 上に, ゲートバス(2) に接続したゲート電極(3) を不透明金属により形成する工程と, 該透明絶縁基板(1) 上全面に,該ゲート電極(3) を覆って,ゲート絶縁膜(4),半導体活性層(5),チャネル保護膜 2. A gate electrode made of an opaque metal to a transparent insulating substrate, a gate insulating film, a semiconductor active layer, are film formed in this order of the source and drain electrodes comprising a bonding layer semiconductor, under which a channel protective film on the gate electrode upper Getosutaga type thin film transistors (TFT) in the manufacturing method of the TFT matrix semiconductor device according to a switching element, a transparent insulating on the substrate (1), gate bus forming by an opaque metal gate electrode connected to (2) (3) If, on the transparent insulating substrate (1) on the entire surface, covering the gate electrode (3), a gate insulating film (4), the semiconductor active layer (5), the channel protective film
    (6)を順次, 積層する工程と, 該チャネル保護膜(6) 上全面にポジ型レジスト膜(7) を塗布し, 該ゲート電極(3) をマスクとして, 該透明絶縁基板(1) の裏面より該ポジ型レジスト膜(7) の全面露光を行い, 現像後, 形成されたポジ型レジスト膜(7) パターンをマスクとして該チャネル保護膜(6) のエッチングを行う工程と, 該透明絶縁基板(1) 上全面に,該半導体接合層(8), ソース・ドレイン金属膜(9) を順次, 積層する工程と, 該ポジ型レジスト膜(7) を除去して, 該チャネル保護膜 (6) sequentially, laminating, the positive resist film (7) is applied to the channel protective film (6) on the entire surface of the gate electrode (3) as a mask, the transparent insulating substrate (1) performs overall exposure of the positive resist film (7) from the back surface, after development, a step of etching of the channel protective film (6) the formed positive resist film (7) pattern as a mask, the transparent insulation the substrate (1) on the entire surface of the semiconductor junction layer (8), the source-drain metal layer (9) sequentially laminating, by removing the positive resist film (7), the channel protective film
    (6) 上に成膜した該半導体接合層(8), ソース・ドレイン金属膜(9) をリフトオフし,該透明絶縁基板(1) 上全面にドレインバス材料(10)を被覆する工程と, レジスト膜(11)をマスクとして, 該ドレインバス材料(1 (6) is deposited on the said semiconductor junction layer (8), a step of lifting off the source-drain metal film (9), covering the drain bus material (10) to the transparent insulating substrate (1) on the entire surface, resist film (11) as a mask, the drain bus material (1
    0)をエッチングし, 該ソース・ドレイン金属膜(9) をパターニングして, ソース電極(13), 並びに, ドレイン電極(14)を形成する工程とを含むことを特徴とするTFT 0) is etched, and patterning the source-drain metal film (9), a source electrode (13), and characterized in that it comprises a step of forming a drain electrode (14) TFT
    マトリクスの製造方法。 Method of manufacturing a matrix.
  3. 【請求項3】 前記半導体活性層(5) が 200nm以下の厚さのアモルファスシリコン, また, 前記半導体接合層 Wherein the semiconductor active layer (5) is 200nm or less of the thickness of the amorphous silicon, also, the semiconductor junction layer
    (8) が200nm以下の厚さの燐ドープアモルファスシリコンからなることを特徴とする請求項1或いは2記載のT (8) is T of claim 1 or 2, wherein the consisting of thick phosphorus-doped amorphous silicon 200nm
    FTマトリクスの製造方法。 Method of manufacturing the FT matrix.
  4. 【請求項4】 前記ドレインバス材料(10)がアルミニウム, または, アルミニウムを主成分とする金属膜であることを特徴とする請求項1或いは2記載のTFTマトリクスの製造方法。 Wherein said drain bus material (10) is aluminum or a method according to claim 1 or 2, wherein the TFT matrix, characterized in that aluminum is a metal film whose main component.
JP21402391A 1991-08-27 1991-08-27 Manufacture of tft matrix Withdrawn JPH0555567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21402391A JPH0555567A (en) 1991-08-27 1991-08-27 Manufacture of tft matrix

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Application Number Priority Date Filing Date Title
JP21402391A JPH0555567A (en) 1991-08-27 1991-08-27 Manufacture of tft matrix

Publications (1)

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JPH0555567A true JPH0555567A (en) 1993-03-05

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JP21402391A Withdrawn JPH0555567A (en) 1991-08-27 1991-08-27 Manufacture of tft matrix

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6552757B1 (en) 1999-10-19 2003-04-22 Sharp Kabushiki Kaisha Liquid crystal display element and method for manufacturing the same
US7131735B2 (en) 1998-06-04 2006-11-07 Seiko Epson Corporation Light source device, optical device, and liquid-crystal display device
US8657467B2 (en) 2004-09-24 2014-02-25 Epistar Corporation Illumination apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7131735B2 (en) 1998-06-04 2006-11-07 Seiko Epson Corporation Light source device, optical device, and liquid-crystal display device
US6552757B1 (en) 1999-10-19 2003-04-22 Sharp Kabushiki Kaisha Liquid crystal display element and method for manufacturing the same
US8657467B2 (en) 2004-09-24 2014-02-25 Epistar Corporation Illumination apparatus

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