JP2002151695A - Manufacturing method of thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the frequency at which a film sticking to the inside surface of a plasma CVD chamber is removed, related to formation of an ohmic contact layer comprising an n-type amorphous silicon of a thin-film transistor. SOLUTION: Phosphorus films 54a and 54b whose film thickness is about several Å are formed on both surfaces of an upper surface of a channel protective film 35 and on the upper surface of a semiconductor thin-film 34 on both sides of it, and a drain electrode 42 and a source electrode 43 comprising chrome are formed on each upper surface. When photoresist films 56 and 57 are peeled for thermal process, the upper surface side of the semiconductor thin-film 34 on both sides of the channel protective film 35 becomes an n-type amorphous silicon. The phosphorus films 54a and 54b are formed by a plasma CVD using a mixture gas of PH3 and H2. Here, since the very thin thickness of phosphorus films 54a and 54b is several Å, the stuck amount per film-forming is very small even if a phosphorus film sticks to the inside surface of the plasma CVD chamber.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a thin film transistor.

[0002]

2. Description of the Related Art FIG. 16 is a sectional view showing an example of a conventional thin film transistor. In this thin film transistor, a gate electrode 2 made of an aluminum-based metal is formed at a predetermined location on the upper surface of a glass substrate 1. On the entire upper surface of the glass substrate 1 including the gate electrode 2, a gate insulating film 3 made of silicon nitride is formed. A semiconductor thin film 4 made of intrinsic amorphous silicon is formed at a predetermined location on the upper surface of the gate insulating film 3. A channel protection film 5 made of silicon nitride is formed at a predetermined location on the upper surface of the semiconductor thin film 4.

Ohmic contact layers 6 and 7 made of n-type amorphous silicon are formed on both sides of the upper surface of the channel protective film 5 and on the upper surface of the semiconductor thin film 4 on both sides thereof. On the upper surface of one ohmic contact layer 6, a silicide layer 8 and a drain electrode 9 made of chromium are formed. On the upper surface of the other ohmic contact layer 7, a silicide layer 10 and a source electrode 11 made of chromium are formed.
Is formed. An overcoat film 12 made of silicon nitride is formed on the entire upper surface of the gate insulating film 3 including both the electrodes 9 and 11 and the like.

Next, a method of manufacturing the thin film transistor will be described. First, as shown in FIG. 17, a gate electrode 2 made of an aluminum-based metal is formed at a predetermined location on the upper surface of a glass substrate 1. Next, a gate insulating film 3 made of silicon nitride, an intrinsic amorphous silicon film 21 and a silicon nitride film 22 are continuously formed on the entire upper surface of the gate insulating film 3 including the gate electrode 2. Next, a photoresist film 23 for forming the channel protective film 5 shown in FIG. 16 is formed at a predetermined position on the upper surface of the silicon nitride film 22.

Next, when the silicon nitride film 22 is etched using the photoresist film 23 as a mask, the channel protective film 5 is formed under the photoresist film 23 as shown in FIG.
Is formed. Next, the photoresist film 23 is removed. Next, as shown in FIG. 19, an n-type amorphous silicon film 24 and a chromium film 25 are continuously formed on the entire upper surface of the intrinsic amorphous silicon film 21 including the channel protective film 5. In this case, a silicide layer 26 is formed between the chromium film 25 and the n-type amorphous silicon film 24. Next, at a predetermined position on the upper surface of the chromium film 25, FIG.
Photoresist films 27 and 28 for forming the drain electrode 9 and the source electrode 11 shown in FIG. 6 are formed.

Next, when the chromium film 25, the silicide layer 26, the n-type amorphous silicon film 24 and the intrinsic amorphous silicon film 21 are etched using the photoresist films 27 and 28 as a mask, the result is as shown in FIG.
That is, the drain electrode 9 under the photoresist film 27,
The silicide layer 8 and the ohmic contact layer 6 are formed, and the source electrode 11, the silicide layer 10, and the ohmic contact layer 7 are formed below the photoresist film 28. Further, the semiconductor thin film 4 is formed under both the ohmic contact layers 6 and 7 and under the channel protective film 5. Next, the photoresist films 27 and 28 are removed. Next, as shown in FIG. 16, an overcoat film 12 made of silicon nitride is formed on the entire upper surface of the gate insulating film 3 including the electrodes 9, 11, and the like. Thus, a conventional thin film transistor is manufactured.

[0007]

In the above-mentioned conventional method of manufacturing a thin film transistor, as described above, in the step shown in FIG. 19, the entire upper surface of the intrinsic amorphous silicon film 21 including the channel protective film 5 is n-type amorphous. A silicon film 24 is formed. This n-type amorphous silicon film 24 is formed by PH ₃ (phosphine),
It is performed by plasma CVD using a mixed gas of SiH ₄ (silane) and H ₂ (hydrogen). In this case, the thickness of the n-type amorphous silicon film 24 is set to about 250 °. By the way, when forming the n-type amorphous silicon film 24 by plasma CVD, the plasma C
Since the n-type amorphous silicon film is also adhered to the inner surface of the VD chamber, this adhered film is periodically removed. However, since the film thickness of the n-type amorphous silicon film 24 to be formed is relatively thick at about 250 °, First, there is a problem that the amount of adhesion per one time becomes relatively large, so that the frequency of removing the adhered film increases, and the productivity decreases. An object of the present invention is to reduce the frequency of removing an adhered film adhered to the inner surface of a plasma CVD chamber.

[0008]

SUMMARY OF THE INVENTION The first aspect of the present invention, the phosphorus film is formed by plasma CVD using a mixed gas of diluent gas and PH ₃ or PH ₃ on the semiconductor thin film, the heat treatment By doing so, an ohmic contact layer composed of an n-type semiconductor layer is formed at the interface between the phosphorus film and the semiconductor thin film. According to a second aspect of the present invention, in the first aspect of the present invention, the thickness of the phosphorus film is set to about several Å or less. The invention according to claim 3 is the invention according to claim 1 or 2
In the invention described in (1), the heat treatment is performed after forming a metal film on the phosphorus film. The invention according to claim 4 is the invention according to claim 3,
The heat treatment is performed at a film forming temperature when forming an overcoat film in a later step. According to a fifth aspect of the present invention, in the third aspect of the invention, the metal film is formed of a metal film that can be silicided. The invention according to claim 6 is the invention according to claim 5, wherein the metal film is removed after the heat treatment. The invention according to claim 7 is a method of manufacturing a thin film transistor, wherein a source electrode and a drain electrode are formed on a source region and a drain region of a semiconductor thin film via an ohmic contact layer and a silicide layer, respectively. phosphorus film is formed by plasma CVD using a mixed gas of diluent gas and PH ₃ or PH _3, heat treatment is performed after forming a silicide metal capable film on its upper surface, said semiconductor thin film and the phosphorus film An ohmic contact layer made of an n-type semiconductor layer is formed at an interface with the metal film, and a silicide layer is formed at an interface between the ohmic contact layer and the metal film capable of being silicided. According to an eighth aspect of the present invention, in the method of the seventh aspect, after forming the ohmic contact layer and the silicide layer, the metal film capable of being silicided near the channel region of the semiconductor thin film is etched. It was made. According to a ninth aspect of the present invention, in the invention of the seventh or eighth aspect, the thickness of the phosphorus film is set to about several Å or less.
Then, according to the invention described in claim 1, the phosphorus film is formed by plasma CVD using a mixed gas of diluent gas and PH ₃ or PH ₃ on the semiconductor thin film, by heat treatment, the phosphorus Since an ohmic contact layer made of an n-type semiconductor layer is formed at the interface between the film and the semiconductor thin film, even if a phosphorus film adheres to the inner surface of the plasma CVD chamber, the amount of the phosphorus film adhered to once should be extremely small. Therefore, the frequency of removing the adhered film adhered to the inner surface of the plasma CVD chamber can be reduced.

[0009]

(First Embodiment) FIG. 1 is a sectional view of a thin film transistor manufactured by a method for manufacturing a thin film transistor according to a first embodiment of the present invention. In this thin film transistor, a gate electrode 32 made of an aluminum-based metal is formed at a predetermined location on the upper surface of a glass substrate 31. On the entire upper surface of the glass substrate 31 including the gate electrode 32, a gate insulating film 33 made of silicon nitride is formed. A semiconductor thin film 34 made of intrinsic amorphous silicon is formed at a predetermined position on the upper surface of the gate insulating film 33. At a predetermined location on the upper surface of the semiconductor thin film 34, a channel protective film 35 made of silicon nitride is formed.

On the regions of the semiconductor thin film 34 on both sides of the channel protective film 35, that is, on the upper surfaces of the drain region and the source region, ohmic contact layers 36 and 37 and silicide layers 38 made of n-type amorphous silicon are formed.
39 are formed. Phosphor films 40 and 41 are formed on both sides of the upper surface of the channel protection film 35. A drain electrode 42 made of chromium is formed on the upper surface of one of the phosphorus film 40 and the silicide layer 38. The other phosphorus film 41
A source electrode 43 made of chromium is formed on the upper surface of the silicide layer 39. An overcoat film 44 made of silicon nitride is formed on the entire upper surface of the gate insulating film 33 including both the electrodes 42 and 43 and the like.

Next, a method of manufacturing the thin film transistor will be described. First, as shown in FIG. 2, a gate electrode 32 made of an aluminum-based metal is formed at a predetermined position on the upper surface of a glass substrate 31. Next, over the entire upper surface of the gate insulating film 33 including the gate electrode 32, a gate insulating film 33 made of silicon nitride having a thickness of about 4000 °, an intrinsic amorphous silicon film 51 having a thickness of about 250 ° and a film thickness of 1500 ° are formed by plasma CVD. The silicon nitride film 52 is formed continuously. Next, the silicon nitride film 52
The channel protective film 35 shown in FIG.
Is formed to form a photoresist film 53.

Next, using the photoresist film 53 as a mask,
When the silicon nitride film 52 is etched by
As described above, the channel protective film 35 is formed under the photoresist film 53.
Is formed. Next, the photoresist film 53 is removed.
You. Next, as shown in FIG.
Over the entire upper surface of the intrinsic amorphous silicon film 51.
₃And H₂By plasma CVD using a mixed gas of
A phosphorus film 54 is formed. In this case, the processing time is about 10 minutes
Degree. Then, the phosphor film 54 has a thickness of about several Å or less.
Deposited to lower film thickness.

Next, as shown in FIG. 5, a chromium film 55 having a thickness of about 1500 ° is formed on the upper surface of the phosphorus film 54 by sputtering. In this case, since the chromium film 55 is formed on the upper surface of the phosphorus film 54, almost no silicide layer is formed between the chromium film 55 and the phosphorus film 54 at this stage. Since the thickness is small, depending on the non-uniformity of the thickness of the phosphorus film 54 and the conditions of the sputtering of the chromium film 55, there is a possibility that a region where a silicide layer is formed may occur to some extent. However, the instability in forming the silicide layer does not cause any particular problem as shown in the following steps. Next, photoresist films 56 and 57 for forming the drain electrode 42 and the source electrode 43 shown in FIG. 1 are formed at predetermined positions on the upper surface of the chromium film 55.

Next, the chromium film 55, the phosphor film 54 and the intrinsic amorphous silicon film 51 are etched using the photoresist films 56 and 57 as masks, as shown in FIG. That is, the drain electrode 42 and the phosphorus film 54a are formed below the photoresist film 56, and the source electrode 43 and the phosphorus film 54b are formed below the photoresist film 57. Further, the semiconductor thin film 34 is formed under both the phosphorus films 54a and 54b and under the channel protection film 35. Next, the photoresist films 56 and 57 are removed.

Next, as shown in FIG.
An overcoat film 44 made of silicon nitride and having a thickness of about 2000 ° is formed on the entire upper surface of the gate insulating film 33 including 3 and the like by plasma CVD. In this case, since the deposition temperature of the overcoat film 44 is about 250 ° C., the heat treatment is performed at the same time. Then, by this heat treatment, the phosphorus forming the phosphorus films 54a and 54b is activated, and the semiconductor thin film 34 made of intrinsic amorphous silicon is activated.
Ohmic contact layers 36 and 37 made of n-type amorphous silicon are formed at the interface with the substrate. Since the chromium film 55 formed on the phosphorus films 54a and 54b is silicided in the vicinity of the interface, the silicide layers 38 and 39 are formed between the ohmic contact layers 36 and 37 and the electrodes 42 and 43. It is formed. Further, phosphorus films 40 and 41 are formed on both sides of the upper surface of the channel protection film 35. Thus, the thin film transistor according to this embodiment is manufactured.

As described above, in the method for manufacturing a thin film transistor according to this embodiment, as shown in FIG. 4, the intrinsic amorphous silicon film 51 is formed on the intrinsic amorphous silicon film 51 by plasma CVD using a mixed gas of PH ₃ and H _2. A phosphorus film 54 of about Å is formed, and as shown in FIG. 1, the upper surface side of the semiconductor thin film 34 made of intrinsic amorphous silicon is converted into n-type amorphous silicon by a heat treatment performed simultaneously with the formation of the overcoat film 44. Plasma CVD
Even if a phosphorus film adheres to the inner surface of the chamber, the amount of the phosphorus film 54 to be formed is extremely small, about several Å, so that the amount of adhesion per one time is extremely small. The frequency of removing the film can be reduced, and the productivity can be improved.

(Second Embodiment) FIG. 7 is a sectional view of a thin film transistor manufactured by a method for manufacturing a thin film transistor according to a second embodiment of the present invention.
In this figure, the same parts as those in FIG. In this thin film transistor, a gate electrode 32 made of an aluminum-based metal is formed at a predetermined location on the upper surface of a glass substrate 31. On the entire upper surface of the glass substrate 31 including the gate electrode 32, a gate insulating film 33 made of silicon nitride is formed. Gate insulating film 3
A semiconductor thin film 34 made of intrinsic amorphous silicon is formed at a predetermined position on the upper surface of the substrate 3. Semiconductor thin film 3
A channel protection film 35 made of silicon nitride is formed at a predetermined position on the upper surface of the substrate 4.

On the upper surface of the semiconductor thin film 34 on both sides of the channel protection film 35, ohmic contact layers 36 and 37 and silicide layers 38 and 39 made of n-type amorphous silicon are formed. One silicide layer 38
A drain electrode 42 made of an aluminum-based metal is formed at a predetermined position on the upper surface of the substrate. A source electrode 43 made of an aluminum-based metal is formed at a predetermined location on the upper surface of the other silicide layer 39. In this case, the silicide layer 3 on the channel protective film 35 and on both sides thereof
8 and 39, a drain electrode 42 and a source electrode 43
Is not formed. An overcoat film 44 made of silicon nitride is formed on the entire upper surface of the gate insulating film 33 including both the electrodes 42 and 43 and the like.

Next, a method of manufacturing the thin film transistor will be described. First, as shown in FIG. 8, a gate electrode 32 made of an aluminum-based metal is formed at a predetermined location on the upper surface of a glass substrate 31. Next, over the entire upper surface of the gate insulating film 33 including the gate electrode 32, a gate insulating film 33 made of silicon nitride having a thickness of about 4000 °, an intrinsic amorphous silicon film 51 having a thickness of about 250 ° and a film thickness of 1500 ° are formed by plasma CVD. The silicon nitride film 52 is formed continuously. Next, the silicon nitride film 52
The channel protection film 35 shown in FIG.
Is formed to form a photoresist film 53.

Next, when the silicon nitride film 52 is etched using the photoresist film 53 as a mask, the channel protective film 35 is formed under the photoresist film 53 as shown in FIG.
Is formed. Next, the photoresist film 53 is peeled off. Next, as shown in FIG. 10, the entire upper surface of the intrinsic amorphous silicon film 51 including the channel protection film 35 is covered with P
The phosphorus film 54 is formed by plasma CVD using a mixed gas of H ₃ and H ₂ . In this case, the processing time is 10
Minutes. Then, the film thickness of the phosphorus film 54 becomes about several Å or less.

Next, as shown in FIG. 11, a chromium film 55 having a thickness of about 1500 ° is formed on the upper surface of the phosphorus film 54 by sputtering. In this case, since the chromium film 55 is formed on the upper surface of the phosphorus film 54, a silicide layer is hardly formed between the chromium film 55 and the phosphorus film 54. Next, FIG.
As shown in FIG. 7, heat treatment is performed at a temperature of about 250 ° C. for about 1 hour. Then, by this heat treatment, an n-type amorphous silicon film 61 is formed at the interface between the phosphorus film 54 and the intrinsic amorphous silicon film 51 except for a portion below the channel protective film 35. Further, a silicide layer 62 is formed at the interface between the n-type amorphous silicon film 61 and the chromium film 55.

Next, the chromium film 55 is removed by wet etching, and then the phosphor film 5 on the channel protection film 35 is removed.
4 is removed by wet etching, and this state is shown in FIG.
3 is shown. Next, as shown in FIG. 14, a photoresist film 63 for forming the silicide layers 38 and 39 shown in FIG. 7 is continuously formed at a predetermined position on the upper surface of the silicide layer 62 including the channel protective film 35. Form. That is,
The photoresist film 63 is also formed on the entire upper surface of the channel protection film 35, and the photoresist films 56 and 57 shown in FIG.
Not separated like. However, the photoresist film 63 may be separated like the photoresist films 56 and 57 shown in FIG.

Next, a silicide layer 62 and an n-type amorphous silicon film 61 are formed using the photoresist film 63 as a mask.
When the intrinsic amorphous silicon film 51 is etched, the result is as shown in FIG. That is, the silicide layer 38 and the ohmic contact layer 36 are formed below the photoresist film 63 on the left side of the channel protective film 35, and the silicide layer 39 and the ohmic contact layer 37 are formed below the photoresist film 64 on the right side of the channel protective film 35. Is done. Further, a semiconductor thin film 34 is formed under both the ohmic contact layers 36 and 37 and under the channel protection film 35. Next, the photoresist film 63 is peeled off.

Next, as shown in FIG. 7, by patterning an aluminum-based metal film having a thickness of about 3000 ° formed by sputtering, one silicide layer 38 is formed.
A drain electrode 42 is formed at a predetermined location on the upper surface of the source electrode 4, and a drain electrode 42 is formed at a predetermined location on the upper surface of the other silicide layer 39.
Form 3 In this case, the drain electrode 42 and the source electrode 43 are not formed on the channel protective film 35 and on the silicide layers 38 and 39 on both sides thereof. next,
On the entire upper surface of the gate insulating film 33 including both the electrodes 42 and 43 and the like, an overcoat film 44 made of silicon nitride and having a thickness of about 2000 ° is formed by plasma CVD.
Thus, the thin film transistor according to this embodiment is manufactured.

As described above, in the method of manufacturing a thin film transistor according to this embodiment, as shown in FIG. 10, the intrinsic amorphous silicon film 51 is formed on the intrinsic amorphous silicon film 51 by plasma CVD using a mixed gas of PH ₃ and H _2. A phosphorus film 54 of about Å is formed, and as shown in FIG.
Since the upper surface side of the intrinsic amorphous silicon film 51 is converted into n-type amorphous silicon by a heat treatment after the formation of the film, even if a phosphorus film adheres to the inner surface of the plasma CVD chamber, the film thickness of the phosphorus film 54 to be formed. Is extremely thin, on the order of several tens of millimeters, so that the amount of adhesion per one time is extremely small, so that the frequency of removing the adhered film adhered to the inner surface of the plasma CVD chamber can be reduced, and the productivity can be improved.

In the conventional thin film transistor shown in FIG. 16, a part of each of the drain electrode 9 and the source electrode 11 is formed on both sides of the upper surface of the channel protective film 5. This is because, in the state shown in FIG.
If the opposed end faces of the semiconductor layers 7 and 28 are located outside the channel protective film 5, the semiconductor thin film 4 just outside the channel protective film 5 is etched, so that such a situation is prevented. As a result, the channel length is the distance S ₁ between the electrodes 9 and 11, the polymerization the length of section S ₂ of the drain electrode 9 and the channel protective film 5, the polymerization unit of the source electrode 11 and the channel protective film 5 the sum of the length S ₃ of the.
In a general method of manufacturing a thin film transistor, S
_Since the processing limit value of _{No. 1} is about 3 μm and the processing limit values of S ₂ and S ₃ are about 2 μm, the minimum channel length is about 7 μm. This is the first case shown in FIG.
The same applies to the thin film transistor of the embodiment.

On the other hand, in the thin film transistor of the second embodiment shown in FIG. 7, the drain electrode 9 and the source electrode 11 are not formed on the channel protective film 35 and on the silicide layers 38 and 39 on both sides thereof. Therefore, the channel length is the length of the channel protection film 35 in the channel length direction. Therefore, the minimum channel length is determined by the processing limit value of the channel protection film 35, and is about 3 μm in a general method of manufacturing a thin film transistor. As a result,
In the thin film transistor of the second embodiment shown in FIG.
6 and the first thin film transistor shown in FIG.
The channel length can be reduced as compared with the thin film transistor of the embodiment. When the channel length is reduced, stray capacitance can be reduced and the size of the thin film transistor can be reduced. If the channel width is the same, a high-performance thin film transistor capable of flowing more current can be obtained.

In each of the above embodiments, the plasma CV
The case where a mixed gas of PH ₃ and H ₂ is used as the reaction gas of D has been described. However, the present invention is not limited to this, and only PH ₃ may be used. Alternatively, argon, helium, neon, etc. other than PH ₃ and hydrogen Mixed gas with other diluent gas. Further, in each of the above embodiments, the case where chromium is used as the metal which can be silicided has been described.
However, the present invention is not limited to this, and may be another metal such as tantalum, molybdenum, titanium, nickel, or tungsten that can be silicided, or an alloy containing chromium. Further, the method for manufacturing a thin film transistor according to the present invention is not limited to the case where the semiconductor active layer is made of amorphous silicon, but is applicable to the case where the semiconductor active layer is made of polycrystalline silicon.

[0029]

As described in the foregoing, according to the present invention, the phosphorus film is formed by plasma CVD using a mixed gas of diluent gas and PH ₃ or PH ₃ on the semiconductor thin film, performing heat treatment As a result, since the ohmic contact layer made of an n-type semiconductor layer is formed at the interface between the phosphorus film and the semiconductor thin film, even if the phosphorus film adheres to the inner surface of the plasma CVD chamber, Therefore, the frequency of removing the adhered film adhered to the inner surface of the plasma CVD chamber can be reduced, and the productivity can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a thin film transistor manufactured by a method for manufacturing a thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing an initial step in manufacturing the thin film transistor shown in FIG.

FIG. 3 is a sectional view of a step following FIG. 2;

FIG. 4 is a sectional view of a step following FIG. 3;

FIG. 5 is a sectional view of a step following FIG. 4;

FIG. 6 is a sectional view of a step following FIG. 5;

FIG. 7 is a sectional view of a thin film transistor manufactured by a method for manufacturing a thin film transistor according to a second embodiment of the present invention.

FIG. 8 is a sectional view showing an initial step in manufacturing the thin film transistor shown in FIG. 7;

FIG. 9 is a sectional view of a step following FIG. 8;

FIG. 10 is a sectional view of a step following FIG. 9;

FIG. 11 is a sectional view of a step following FIG. 10;

FIG. 12 is a sectional view of a step following FIG. 11;

FIG. 13 is a sectional view of a step following FIG. 12;

FIG. 14 is a sectional view of a step following FIG. 13;

FIG. 15 is a sectional view of a step following FIG. 14;

FIG. 16 is a cross-sectional view of an example of a conventional thin film transistor.

FIG. 17 is a sectional view showing an initial step in manufacturing the thin film transistor shown in FIG. 16;

FIG. 18 is a sectional view of a step following FIG. 17;

FIG. 19 is a sectional view of a step following FIG. 18;

FIG. 20 is a sectional view of a step following FIG. 19;

[Explanation of symbols]

 Reference Signs List 31 glass substrate 32 gate electrode 33 gate insulating film 34 semiconductor thin film 35 channel protective film 36, 37 ohmic contact layer 38, 39 silicide layer 40, 41 phosphorus film 42 drain electrode 43 source electrode

Continued on the front page F-term (reference) 4K030 AA08 AA17 BA24 BB12 BB14 CA06 CA17 DA09 FA01 HA01 4M104 AA10 BB02 BB13 BB21 BB24 BB25 BB26 BB27 BB28 CC01 DD28 DD37 DD63 DD64 DD78 DD84 DD91 FF18 GG20 HH110 H07FF03 DD02 GG15 GG35 GG45 HK03 HK04 HK05 HK09 HK16 HK22 HK25 HK33 HK35 HK41 NN04 NN14 NN24 NN35 QQ09

Claims (9)

[Claims] A phosphorus film is formed on a semiconductor thin film by plasma CVD using PH ₃ or a mixed gas of PH ₃ and a diluent gas, and heat treatment is performed to form a phosphor film between the phosphorus film and the semiconductor thin film. A method for manufacturing a thin film transistor, comprising forming an ohmic contact layer made of an n-type semiconductor layer at an interface. 2. The method according to claim 1, wherein the thickness of the phosphorus film is about several Å or less. 3. The method according to claim 1, wherein the heat treatment is performed after forming a metal film on the phosphorus film. 4. The method according to claim 3, wherein the heat treatment is performed at a film forming temperature when forming an overcoat film in a later step. 5. The method according to claim 3, wherein the metal film is a metal film that can be silicided. 6. The method according to claim 5, wherein the metal film is removed after the heat treatment. 7. A method for manufacturing a thin film transistor in which a source electrode and a drain electrode are formed on a source region and a drain region of a semiconductor thin film via an ohmic contact layer and a silicide layer, respectively, wherein PH ₃ or PH is formed on the semiconductor thin film. _A phosphorus film is formed by plasma CVD using a mixed gas of No. ₃ and a diluting gas, a metal film capable of being silicided is formed on the upper surface thereof, and then heat treatment is performed, and an interface between the phosphorus film and the semiconductor thin film is formed. A method for manufacturing a thin film transistor, comprising: forming an ohmic contact layer made of an n-type semiconductor layer; and forming a silicide layer at an interface between the ohmic contact layer and the silicidable metal film. 8. The method according to claim 7, wherein after forming the ohmic contact layer and the silicide layer, the metal film capable of being silicided near a channel region of the semiconductor thin film is etched. A method for manufacturing a thin film transistor. 9. The method for manufacturing a thin film transistor according to claim 7, wherein the thickness of the phosphorus film is about several Å or less.