JPH0555462A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce manhours when forming a lower layer gate of an MOSFET of a double-layer gate by forming a lower layer electrode of a capacitor of a double-layer electrode structure at the same time. CONSTITUTION:A second layer conductive film is applied all over a substrate 1 and a first resist film 7 is formed in a formation region of an upper layer electrode 6C of a capacitor and an upper layer gate 6F of an FET. The upper layer electrode 6C of the capacitor and the upper layer gate 6F of the FET are formed by performing etching using the first resist film 7 as a mask. A formation part and an isolation region of a lower layer electrode 4C of the capacitor is covered with a second resist film 10, a lower layer gate 4F is formed by etching a pattern 4A on an FET region using the second resist film 10 as a mask and the lower layer electrode 4C of the capacitor is formed by etching a pattern 4B of the capacitor region. Thereby, it is possible to reduce manhours when a capacitor of a structure of double-layer gates 6F, 6C and double-layer electrodes 6C, 4C is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a composite process for forming a two-layer gate MOS FET and a two-layer electrode structure capacitor.

In recent years, as semiconductor device processes have become complex, the number of manufacturing steps has increased and the manufacturing cost has increased, so that simplification of the process is required. The present invention can be utilized as a manufacturing method that meets this demand.

[0003]

2. Description of the Related Art A general conventional example for forming a two-layer gate MOS FET and a two-layer electrode structure capacitor will be described.

FIGS. 3A to 3E are sectional views for explaining a conventional example. Below, the left side of each figure shows the capacitor section, and the right side shows the FET section. In FIG. 3A, a silicon dioxide (SiO ₂ ) film 2 is formed on a silicon (Si) substrate 1 as an isolation insulating film.

Next, SiO _{2 is} formed as a gate insulating film on the FET portion.
The film 3 is formed. Then, a first-layer polysilicon film 4 is grown on the entire surface of the substrate by a vapor phase growth (CVD) method and patterned to form a lower electrode 4C of the capacitor and a pattern 4A on the FET region.

Next, a SiO ₂ film 5 is formed as an insulating film to cover the lower electrode 4C of the capacitor and the pattern 4A on the FET region. In FIG. 3B, a second layer polysilicon film 6 is grown on the entire surface of the substrate.

Next, a resist film 7 for forming an upper layer electrode of the capacitor and an upper layer gate of the FET is formed on the second layer polysilicon film 6 by using ordinary lithography. Figure 3 (C)
Then, the second polysilicon film 6 is anisotropically etched using the resist film (first) 7 as an etching mask to form the upper electrode 6C of the capacitor and the upper gate 6F of the FET.

During this anisotropic etching, the sidewall 6S made of the second-layer polysilicon film 6 remains on the side surface of the lower electrode 4C of the capacitor. Next, the capacitor portion is covered with a resist film (second) 8 and the pattern 4A on the active region of the FET is aligned with the upper gate 6F and etched to form the upper gate 4F.

In FIG. 3D, a resist film (third) 9 for opening the capacitor region is formed on the substrate, and the side wall 6S is removed by etching using the resist film 9 as an etching mask.

Next, the resist film 9 is peeled off. Figure 3
In (E), the source-drain region 1A is formed by self-aligning with the gate and injecting ions into the FET substrate.

[0011]

In the conventional example, since the side wall made of the upper layer electrode material remains on the side surface of the lower layer electrode when the upper layer electrode of the capacitor is formed, a dedicated lithography process for removing the side wall is required. It was

Therefore, there is a problem that the number of man-hours and the manufacturing cost increase. An object of the present invention is to reduce man-hours and manufacturing cost when forming a two-layer gate MOS FET and a two-layer electrode structure capacitor.

[0013]

[Means for Solving the Problems] To solve the above problems, a step of forming an isolation insulating film (2) on a semiconductor substrate (1) and forming a gate insulating film (3) in a FET formation region, and then, Depositing a first conductive film (4) on the substrate and patterning the first conductive film to form a pattern (4B) on the capacitor region and a pattern (4A) on the FET region; Next, the pattern (4B) on the capacitor area and the pattern on the FET area
A step of forming an insulating film (5) covering (4A), and then,
A step of depositing a second conductive film (6) on the substrate, and then a first resist film (7) on the upper electrode forming region of the capacitor and the upper gate forming region of the FET on the second conductive film.
And patterning the second conductive film using the first resist film as an etching mask to form the upper electrode (6C) of the capacitor and the upper gate (6F) of the FET,
Then, the lower electrode formation region and the isolation region of the capacitor are covered with the second resist film (10), and the pattern on the FET region is formed by using the first and second resist films as an etching mask.
(4A) is etched to form the lower layer gate (4F), and at the same time, the pattern (4B) on the capacitor region is etched to form the lower electrode (4C) of the capacitor, and then the gate (6F) is formed. , (4F) self-aligning, and then implanting ions into the substrate in the FET region to form the source / drain region (1A).

[0014]

According to the present invention, the man-hours are reduced by forming the lower layer electrode of the capacitor having the double layer electrode structure at the same time when the lower layer gate of the two-layer gate MOS FET is formed.

FIGS. 1A to 1C are explanatory views of the principle of the present invention. As shown in FIG. 1 (A), as an isolation insulating film on the Si substrate 1.
The SiO ₂ film 2 is formed. Then, a SiO ₂ film 3 is formed as a gate insulating film on the FET part.

Then, a first conductive film 4 is deposited on the entire surface of the substrate and patterned to form a pattern 4B on the capacitor region.
And pattern 4A on the FET area is formed. Next, the insulating film 5 is formed so as to cover the pattern 4B on the capacitor region and the pattern 4A on the FET region.

Then, a second-layer conductive film 6 is deposited on the entire surface of the substrate. Then, using a normal lithography, a first resist film 7 is formed on the second conductive film 6 on the upper electrode of the capacitor and on the upper gate formation region of the FET.

Next, using the resist film 7 as an etching mask, the second conductive film 6 is anisotropically etched to form the upper electrode 6C of the capacitor and the upper gate 6F of the FET. During this anisotropic etching, the pattern on the capacitor area
The side wall 6S made of the second-layer polysilicon film 6 remains on the side surface of 4B.

In FIG. 1B, the lower electrode formation portion and the isolation region of the capacitor are covered with the second resist film 10, and the FET is
The pattern 4A on the region is etched to form the lower gate 4F, and at the same time, the pattern 4B on the capacitor region is etched to form the lower electrode 4C of the capacitor.

In FIG. 1C, the source / drain region 1A is formed by self-aligning with the gate and implanting ions into the substrate. As described above, the lithography process for removing the side wall can be reduced.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 2A to 2E are sectional views of an embodiment of the present invention. In FIG. 2 (A), a SiO ₂ film 2 having a thickness of 6000 to 8000Å is formed as a separation insulating film on the Si substrate 1 by thermal oxidation.

Next, a SiO ₂ film 3 having a thickness of 200 to 400 Å is formed as a gate insulating film on the FET portion by thermal oxidation. Then, a CVD method is used to grow a first-layer polysilicon film 4 having a thickness of 2000 to 3000Å as a first-layer conductive film on the entire surface of the substrate, and patterning is performed to form a pattern 4B on the capacitor region and a pattern 4A on the FET region. Form.

Next, the pattern 4B on the capacitor area
An SiO ₂ film 5 having a thickness of 200 to 350 Å is formed as an insulating film so as to cover the pattern 4A on the active region of the FET. In Fig. 2 (B), the thickness of 3000-4000Å as the second layer conductive film on the entire surface of the substrate.
The second-layer polysilicon film 6 is grown.

Then, a resist film 7 for forming an upper layer electrode of the capacitor and an upper layer gate of the FET is formed on the second layer polysilicon film 6 by using ordinary lithography. Figure 1 (C)
In the step 2, using the resist film 7 as an etching mask,
The upper polysilicon film 6 is anisotropically etched to form the upper electrode 6C of the capacitor and the upper gate 6F of the FET.

During this anisotropic etching, the side wall 6S made of the second-layer polysilicon film 6 remains on the side surface of the pattern 4B on the capacitor region. In Fig. 1 (D), the lower electrode formation part of the capacitor and the isolation region are covered with a resist film 10, and FE
The upper layer gate 4F is formed by self-aligning the pattern 4A on the T region with the upper layer gate 6F to form the upper layer gate 4F, and at the same time, etching the pattern 4B on the capacitor region to form the lower layer electrode 4C of the capacitor.

In FIG. 1 (E), after etching, the resist film is removed, and the source / drain region 1A is formed by self-aligning with the gate and implanting ions into the FET substrate.

[0027]

[Effects of the Invention] The number of steps for forming a two-layer gate MOS FET and a two-layer electrode structure capacitor has been reduced, and as a result, it has been possible to contribute to a reduction in manufacturing cost.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is a sectional view of an embodiment of the present invention.

FIG. 3 is a sectional view illustrating a conventional example.

[Explanation of symbols]

1 Semiconductor substrate Si substrate 2 Isolation insulating film SiO ₂ film 3 Gate insulating film SiO ₂ film 4 First layer conductive film 1st layer Polysilicon film 4A Pattern on active area of FET 4B Pattern on capacitor area 4C Capacitor lower layer electrode 4F FET lower gate 5 Insulating film SiO ₂ film 6 Second layer conductive film 2nd layer polysilicon film 6C Capacitor upper layer electrode 6F FET upper layer gate 6S Sidewall made of 2nd layer polysilicon film 7 First resist film 8, 9 Conventional resist film 10 Second resist film of Example

Claims (1)

[Claims] 1. A step of forming an isolation insulating film (2) on a semiconductor substrate (1) and forming a gate insulating film (3) in an FET formation region, and then, forming a first conductive film (3) on the substrate. 4) is applied and the first conductive film is patterned to form a pattern (4B) on the capacitor region and a pattern (4A) on the FET region, and then a pattern (4B) on the capacitor region. ) And a step of forming an insulating film (5) so as to cover the pattern (4A) on the FET region, then a step of depositing a second conductive film (6) on the substrate, and then, The first resist film is formed on the capacitor upper layer electrode formation region and the FET upper layer gate formation region on the second conductive film.
(7) is formed, the second resist film is patterned using the first resist film as an etching mask to form the upper electrode (6C) of the capacitor and the upper gate (6F) of the FET, and , A pattern on the FET region where the lower electrode formation region of the capacitor and the isolation region are covered with a second resist film (10) and the first and second resist films are used as an etching mask.
(4A) is etched to form the lower gate (4F), and at the same time, the pattern (4B) on the capacitor region is etched to form the lower electrode (4C) of the capacitor, and then the gate (6F) And (4F) are self-aligned to implant the ions into the substrate in the FET region to form the source / drain region (1A).