JPH0555412A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0555412A JPH0555412A JP21489491A JP21489491A JPH0555412A JP H0555412 A JPH0555412 A JP H0555412A JP 21489491 A JP21489491 A JP 21489491A JP 21489491 A JP21489491 A JP 21489491A JP H0555412 A JPH0555412 A JP H0555412A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor device
- resin
- sealing resin
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
熱ストレスにより生じる故障を防止する半導体装置に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device which prevents a failure caused by thermal stress.
【０００２】[0002]
【従来の技術】従来、この種の半導体装置は、図４に示
すように、半導体素子１を樹脂ペースト２等の接着層を
もうけ半導体素子１をリードフレーム３の半導体素子搭
載部４に固着し、その後、樹脂ペースト２等を加熱硬化
させ、リードフレーム３の内部リード５上に施されたＡ
ｇ等のめっき部６とボンディングパッド７とを金属細線
８で結線する。2. Description of the Related Art Conventionally, in this type of semiconductor device, as shown in FIG. 4, a semiconductor element 1 is provided with an adhesive layer such as a resin paste 2 and the semiconductor element 1 is fixed to a semiconductor element mounting portion 4 of a lead frame 3. After that, the resin paste 2 and the like are heated and hardened, and A applied on the inner leads 5 of the lead frame 3
The plated portion 6 such as g and the bonding pad 7 are connected by a thin metal wire 8.
【０００３】その後、封止金型にリードフレーム３ごと
にサンドイッチ状にセットし、封止樹脂９を金型に加熱
注入することで半導体装置のボディを形成し、図示しな
いリードフレーム３の不要な部分が切り落とされリード
フレーム３の外部リード１０を所定の形状に加工し製造
されていた。After that, the lead frames 3 are set in a sandwich shape in a sealing die, and the sealing resin 9 is heated and injected into the die to form the body of the semiconductor device. The portion was cut off and the outer lead 10 of the lead frame 3 was manufactured by processing it into a predetermined shape.
【０００４】[0004]
【発明が解決しようとする課題】この従来の半導体装置
において、図５（ａ），（ｂ）に示すように、半導体素
子１の表面には、ＳｉＯ2 等の絶縁層１１，Ａｌ等の配
線１２，Ａｌ等の配線１２を保護するＳｉ3 Ｎ4 等のカ
バー層１３が形成されている。In this conventional semiconductor device, as shown in FIGS. 5A and 5B, on the surface of the semiconductor element 1, an insulating layer 11 made of SiO 2 or the like and wiring made of Al or the like are formed. 12, a cover layer 13 of Si 3 N 4 or the like is formed to protect the wiring 12 of Al or the like.
【０００５】これらの材質の熱膨張係数及び封止樹脂９
の熱膨張係数，半導体素子の基体であるＳｉ１４の熱膨
張係数には大きな差が見られ熱応力が発生する。特に、
半導体素子１の基本であるＳｉ１４は３．０×１０-7／
℃程度の熱膨張係数であるのに対して封止樹脂９の熱膨
張係数は、（１．４〜２．０）×１０-5／℃でその相違
は大きい。したがって、仮に１７５℃で樹脂封止された
半導体装置であれば、１７５℃からの冷却の段階で熱応
力が発生する。特に、Ａｌ等の配線１２が形成されてい
る半導体素子１表面のコーナ部１５では過大なストレス
が発生する。このため、温度サイクル試験（温度範囲１
５０℃から−６５℃）のような過激な試験では、半導体
素子１表面のコーナ部１５からＳｉ3 Ｎ4 等のカバー層
１３にクラック１７が発生したり、カバー層１３と封止
樹脂界面に剥離１６が生じる欠点がある。Thermal expansion coefficient and sealing resin 9 of these materials
There is a great difference in the coefficient of thermal expansion of Si and the coefficient of thermal expansion of Si14, which is the base of the semiconductor element, and thermal stress occurs. In particular,
Si14, which is the basis of the semiconductor device 1, is 3.0 × 10 −7 /
The thermal expansion coefficient of the sealing resin 9 is (1.4 to 2.0) × 10 −5 / ° C., whereas the thermal expansion coefficient is approximately 0 ° C., which is a large difference. Therefore, if the semiconductor device is resin-sealed at 175 ° C., thermal stress is generated during the cooling from 175 ° C. In particular, excessive stress occurs in the corner portion 15 on the surface of the semiconductor element 1 where the wiring 12 made of Al or the like is formed. Therefore, a temperature cycle test (temperature range 1
In a radical test such as 50 ° C. to −65 ° C., cracks 17 are generated in the cover layer 13 such as Si 3 N 4 from the corner portion 15 on the surface of the semiconductor element 1, or the interface between the cover layer 13 and the sealing resin is generated. There is a drawback that peeling 16 occurs.
【０００６】さらに、温度サイクルの繰り返し数が増し
ていくとＡｌ等の配線１２が半導体素子１の内側へ変形
していく。これらのカバー層１３と封止樹脂９の剥離１
６部分には封止樹脂９が吸収した水分が留まり、回路の
リーク不良や前述の水分と封止樹脂９内や半導体装置の
外部から材料界面を通して侵入してきたＣｌ- ，Ｎａ+
等のイオン性不純物によりクラック１７部分のＡｌの腐
食を発生させ断線不良が起こる欠点があった。Further, as the number of repeated temperature cycles increases, the wiring 12 made of Al or the like deforms inside the semiconductor element 1. Peeling off these cover layer 13 and sealing resin 9 1
Moisture absorbed by the encapsulation resin 9 stays at the 6th portion, and circuit leakage defects and the above-mentioned moisture and Cl − and Na + that have entered from the inside of the encapsulation resin 9 and the outside of the semiconductor device through the material interface.
However, there is a defect that the corrosion of Al in the crack 17 portion occurs due to ionic impurities such as the above and a disconnection failure occurs.
【０００７】また、温度サイクル繰返し数が増して行く
と、Ａｌ等の配線１２の変形のため、特に、Ａｌ等の配
線１２が隣接して設けられている場合には、隣接し合う
Ａｌ等の配線１２が接触してショート不良や回路の誤動
作が発生する欠点があった。Further, when the number of temperature cycle repetitions increases, the wirings 12 made of Al or the like are deformed. In particular, when the wirings 12 made of Al or the like are provided adjacent to each other, the wirings of Al or the like adjacent to each other are formed. There is a defect that the wiring 12 comes into contact with each other and a short circuit defect or a circuit malfunction occurs.
【０００８】本発明の目的は、配線の断線不良やショー
ト不良や回路の誤動作のない半導体装置を提供すること
にある。An object of the present invention is to provide a semiconductor device which is free from wiring disconnection defects, short circuit defects, and circuit malfunctions.
【０００９】[0009]
【課題を解決するための手段】本発明は、 （１）半導体素子搭載部とインナーリードを備えたリー
ドフレームと、前記半導体素子搭載部にＡｇペーストを
含む接着層にて固着された半導体素子と、該半導体素子
のボンディングパッドと前記インナーリードを結線する
金属細線と、前記半導体素子を封止する封止樹脂とを有
する半導体装置において、前記封止樹脂の前記半導体素
子の４コーナの外側近傍と対応する位置に貫通孔を設け
る。According to the present invention, (1) a lead frame having a semiconductor element mounting portion and an inner lead, and a semiconductor element fixed to the semiconductor element mounting portion with an adhesive layer containing Ag paste. A semiconductor device having a thin metal wire for connecting the bonding pad of the semiconductor element and the inner lead, and a sealing resin for sealing the semiconductor element, in the vicinity of the four corners of the semiconductor element of the sealing resin. Through holes are provided at corresponding positions.
【００１０】（２）前記貫通孔がフッ素系ポリマーとポ
リイミドのうちいずれか一方の樹脂で充填されている。(2) The through hole is filled with either one of a fluoropolymer and a polyimide.
【００１１】[0011]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【００１２】図１は本発明の第１の実施例の一部切欠き
斜視図である。FIG. 1 is a partially cutaway perspective view of the first embodiment of the present invention.
【００１３】第１の実施例は、図１に示すように、従来
と同様に半導体素子１を樹脂ペースト２等によりリード
フレーム３の半導体素子搭載部４に固着し、その後、樹
脂ペースト２等を加熱硬化させ、リードフレーム３の内
部リード５上に施こされたＡｇ等のめっき部６と半導体
素子１のボンディングパッド７とを金属細線８で結線す
る。In the first embodiment, as shown in FIG. 1, the semiconductor element 1 is fixed to the semiconductor element mounting portion 4 of the lead frame 3 by the resin paste 2 or the like as in the conventional case, and then the resin paste 2 or the like is attached. A metal thin wire 8 connects the plated portion 6 of Ag or the like applied to the inner lead 5 of the lead frame 3 and the bonding pad 7 of the semiconductor element 1 by heating and hardening.
【００１４】その後、封止金型にリードフレーム３ごと
サンドイッチ状にセットする。After that, the lead frame 3 and the lead frame 3 are set in a sandwich mold in a sealing mold.
【００１５】図２は本発明の第１の実施例の樹脂封止方
法を説明する断面図である。FIG. 2 is a sectional view for explaining the resin sealing method of the first embodiment of the present invention.
【００１６】第１の実施例の樹脂封止方法は、図２に示
すように、まず、半導体素子１の４コーナの外側近傍と
対応する下金型１８に金型突起部１９を植立しておく。
金型突起部１９は上金型２０に設けられた穴にかん合す
る。また、イジェクタピン２１を上下金型に具備させ金
型開口時に半導体装置の封止樹脂９表面を押し離型する
ようにする。尚、封止樹脂９は図示しない流入口から金
型内部に流し込まれ加熱硬化させるのである。In the resin encapsulation method of the first embodiment, as shown in FIG. 2, first, a mold projection 19 is planted in a lower mold 18 corresponding to the outer vicinity of the four corners of the semiconductor element 1. Keep it.
The mold protrusion 19 fits into a hole provided in the upper mold 20. Further, the ejector pins 21 are provided in the upper and lower molds so that the surface of the sealing resin 9 of the semiconductor device is pushed and released when the mold is opened. In addition, the sealing resin 9 is poured into the inside of the mold from an inflow port (not shown) and is cured by heating.
【００１７】このような金型を用いて樹脂封止を行なう
ことで半導体素子１の外側近傍の４コーナに貫通孔２２
を備えることができる。By performing resin sealing using such a mold, the through holes 22 are formed at four corners near the outside of the semiconductor element 1.
Can be provided.
【００１８】次に、リードフレーム３の不要な部分が切
り落とされ、リードフレーム３の外部リード１０を所定
の形状に加工し、第１の実施例の半導体装置を得る。Next, unnecessary portions of the lead frame 3 are cut off, and the external leads 10 of the lead frame 3 are processed into a predetermined shape to obtain the semiconductor device of the first embodiment.
【００１９】図３は、本発明の第２の実施例の一部切欠
き斜視図である。FIG. 3 is a partially cutaway perspective view of the second embodiment of the present invention.
【００２０】第２の実施例は、図３に示すように、ま
ず、従来の金型で封止した後、半導体装置を位置決め
し、ドリルで貫通孔２２をもうける。In the second embodiment, as shown in FIG. 3, first, after sealing with a conventional mold, the semiconductor device is positioned and a through hole 22 is made with a drill.
【００２１】次に、フッ素系ポリマーやポリイミドのよ
うな弾性率が低い樹脂２３で貫通孔２２を充填する。Next, the through hole 22 is filled with a resin 23 having a low elastic modulus such as a fluoropolymer or polyimide.
【００２２】その後、リードフレーム３の不要な部分が
切り落され、リードフレーム３の外部リード１０を所定
の形状に加工し、第２の実施例の半導体装置を得る。After that, unnecessary portions of the lead frame 3 are cut off, and the external leads 10 of the lead frame 3 are processed into a predetermined shape to obtain the semiconductor device of the second embodiment.
【００２３】第１の実施例と比較し、第２の実施例は、
貫通孔２２をもうけ、弾性率の低い樹脂２３で充填され
ているため、レーザー等を利用すれば半導体装置表面全
体のどこでも捺印ができる利点がある。また、半導体装
置の熱放散性も損うこともない利点がある。Compared to the first embodiment, the second embodiment
Since the through hole 22 is provided and the resin 23 having a low elastic modulus is filled, there is an advantage that marking can be performed anywhere on the entire surface of the semiconductor device by using a laser or the like. Further, there is an advantage that the heat dissipation of the semiconductor device is not impaired.
【００２４】図６は本発明の実施例と従来の半導体装置
の温度サイクル試験結果の累積ショート不良率の特性図
である。FIG. 6 is a characteristic diagram of the cumulative short circuit defect rate as a result of the temperature cycle test of the embodiment of the present invention and the conventional semiconductor device.
【００２５】１６０ピンクワッドフラットパッケージ
（ＱＦＰ）にＳｉ基体上にＳｉＯ2 １μｍ厚，Ａｌ１μ
ｍ厚，Ｓｉ3 Ｎ4 １μｍ厚の構造を有するテスト用半導
体素子を搭載したサンプルで温度サイクル（−６５℃か
ら１５０℃）試験をし、Ａｌ配線のショート不良率を示
した。Ａｌ配線の間隔は２μｍで、くし刃状に半導体素
子周囲１００μｍから５本配置している。In a 160 pink quad flat package (QFP), SiO 2 on a Si substrate 1 μm thick, Al 1 μm
The temperature cycle (-65 ° C to 150 ° C) test was performed on a sample equipped with a test semiconductor element having a structure of m thickness and Si 3 N 4 1 μm thickness, and the short circuit failure rate of Al wiring was shown. The interval between the Al wirings is 2 μm, and five pieces are arranged in a comb-like shape from 100 μm around the semiconductor element.
【００２６】従来の半導体装置は、２００サイクルから
ショート不良が発生しているのに対し、本発明の第１，
第２の実施例では、６００サイクルまでショート不良が
発生していない。In the conventional semiconductor device, a short circuit defect has been generated from 200 cycles, whereas
In the second embodiment, no short circuit failure has occurred up to 600 cycles.
【００２７】従来の半導体装置の場合は、半導体装置の
コーナ部の周囲から２００μｍ程度のエリアでショート
不良が多発するが、第１，第２の実施例では半導体素子
のコーナに貫通孔がもうけられているか、または、貫通
孔をもうけ弾性率の低い樹脂で埋められているため、半
導体素子のコーナ部のストレスが著しく緩和されるため
にカバー層のクラックの発生も認められず、また、Ａｌ
変形も発生しない。In the case of the conventional semiconductor device, short circuit defects frequently occur in an area of about 200 μm from the periphery of the corner portion of the semiconductor device, but in the first and second embodiments, a through hole is provided in the corner of the semiconductor element. Or the through hole is filled with a resin having a low elastic modulus, the stress at the corner of the semiconductor element is remarkably relieved, and no crack is observed in the cover layer.
No deformation occurs.
【００２８】尚、封止樹脂の常温での弾性率は通常１０
００〜２０００ｋｇ／ｍｍ2 であるのに対し、常温での
フッ素系ポリマーは０．５〜１０ｋｇ／ｍｍ2 であり、
ポリイミドは１００〜５００ｋｇ／ｍｍ2 である。The elastic modulus of the sealing resin at room temperature is usually 10
Whereas a 00~2000kg / mm 2, a fluorine-based polymer at room temperature is 0.5 to 10 / mm 2,
Polyimide is 100 to 500 kg / mm 2 .
【００２９】[0029]
【発明の効果】以上説明したように本発明は、封止樹脂
の半導体素子の４コーナの外側近傍と対応する位置に貫
通孔を有しているか、または、貫通孔がフッ素系ポリマ
ーやポリイミド等の弾性率が低い樹脂で埋められている
ので、半導体素子表面のストレスを緩和するため水分が
留まることによる回路のリーク不良，水分と樹脂封止内
や半導体装置の外部から材料界面を通して侵入してきた
Ｃｌ- ，Ｎａ+ 等のイオン性不純物により、Ａｌの腐食
が発生することによる断線不良，温度サイクル繰返し数
が増した時に発生するＡｌ等の配線の変形によるショー
ト不良，回路の誤動作等を防止するという効果を有す
る。As described above, according to the present invention, through-holes are provided at positions corresponding to the outer periphery of the four corners of the semiconductor element of the encapsulating resin, or the through-holes are a fluorine-based polymer, polyimide or the like. Since it is filled with a resin having a low elastic modulus, the circuit leaks due to moisture remaining in order to relieve the stress on the surface of the semiconductor element. Prevents disconnection failure due to Al corrosion caused by ionic impurities such as Cl − and Na + , short circuit failure due to deformation of wiring such as Al that occurs when the number of temperature cycle repetitions increases, and circuit malfunction. Has the effect.
【図１】本発明の第１の実施例の一部切欠き斜視図であ
る。FIG. 1 is a partially cutaway perspective view of a first embodiment of the present invention.
【図２】本発明の第１の実施例の樹脂封止方法を説明す
る断面図である。FIG. 2 is a sectional view illustrating a resin sealing method according to the first embodiment of the present invention.
【図３】本発明の第２の実施例の一部切欠き斜視図であ
る。FIG. 3 is a partially cutaway perspective view of a second embodiment of the present invention.
【図４】従来の半導体装置の一例の一部切欠き斜視図で
ある。FIG. 4 is a partially cutaway perspective view of an example of a conventional semiconductor device.
【図５】従来の半導体装置の温度サイクル試験前後のコ
ーナ部の断面図で、（ａ）は温度サイクル試験前の断面
図、（ｂ）は温度サイクル試験後の断面図である。5A and 5B are sectional views of a corner portion of a conventional semiconductor device before and after a temperature cycle test, in which FIG. 5A is a sectional view before the temperature cycle test and FIG. 5B is a sectional view after the temperature cycle test.
【図６】本発明の実施例と従来の半導体装置の温度サイ
クル試験結果の累積ショート不良率の特性図である。FIG. 6 is a characteristic diagram of a cumulative short circuit defect rate as a result of a temperature cycle test of an example of the present invention and a conventional semiconductor device.
１ 半導体素子 ２ 樹脂ペースト ３ リードフレーム ４ 半導体素子搭載部 ５ 内部リード ６ Ａｇ等のめっき部 ７ ボンディングパッド ８ 金属細線 ９ 封止樹脂 １０ 外部リード １１ 絶縁層 １２ 配線 １３ カバー層 １４ Ｓｉ １５ コーナ部 １６ 剥離 １７ クラック １８ 下金型 １９ 金型突起部 ２０ 上金型 ２１ イジェクタピン ２２ 貫通孔 ２３ 弾性率の低い樹脂 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Resin paste 3 Lead frame 4 Semiconductor element mounting part 5 Internal lead 6 Plating part such as Ag 7 Bonding pad 8 Metal fine wire 9 Sealing resin 10 External lead 11 Insulating layer 12 Wiring 13 Cover layer 14 Si 15 Corner part 16 Peeling 17 Crack 18 Lower mold 19 Mold protrusion 20 Upper mold 21 Ejector pin 22 Through hole 23 Resin with low elastic modulus
Claims (2)
えたリードフレームと、前記半導体素子搭載部にＡｇペ
ーストを含む接着層にて固着された半導体素子と、該半
導体素子のボンディングパッドと前記インナーリードを
結線する金属細線と、前記半導体素子を封止する封止樹
脂とを有する半導体装置において、前記封止樹脂の前記
半導体素子の４コーナの外側近傍と対応する位置に貫通
孔を設けたことを特徴とする半導体装置。1. A lead frame having a semiconductor element mounting portion and an inner lead, a semiconductor element fixed to the semiconductor element mounting portion with an adhesive layer containing Ag paste, a bonding pad of the semiconductor element, and the inner lead. In a semiconductor device having a thin metal wire that connects the semiconductor element and a sealing resin that seals the semiconductor element, a through hole is provided at a position corresponding to the vicinity of the outside of the four corners of the semiconductor element of the sealing resin. Characteristic semiconductor device.
ミドのうちいずれか一方の樹脂で充填されていることを
特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the through hole is filled with a resin of either one of a fluoropolymer and a polyimide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21489491A JPH0555412A (en) | 1991-08-27 | 1991-08-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21489491A JPH0555412A (en) | 1991-08-27 | 1991-08-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0555412A true JPH0555412A (en) | 1993-03-05 |
Family
ID=16663327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21489491A Pending JPH0555412A (en) | 1991-08-27 | 1991-08-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0555412A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090129531A1 (en) * | 2007-11-15 | 2009-05-21 | The State Of Or Acting By And Through The State System Of Higher Education On Behalf Of Or State U | Submerged containment vessel for a nuclear reactor |
| US9870838B2 (en) | 2007-11-15 | 2018-01-16 | Nuscale Power, Llc | Evacuated containment vessel for a nuclear reactor |
-
1991
- 1991-08-27 JP JP21489491A patent/JPH0555412A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090129531A1 (en) * | 2007-11-15 | 2009-05-21 | The State Of Or Acting By And Through The State System Of Higher Education On Behalf Of Or State U | Submerged containment vessel for a nuclear reactor |
| US8687759B2 (en) | 2007-11-15 | 2014-04-01 | The State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University | Internal dry containment vessel for a nuclear reactor |
| US9870838B2 (en) | 2007-11-15 | 2018-01-16 | Nuscale Power, Llc | Evacuated containment vessel for a nuclear reactor |
| US10186334B2 (en) | 2007-11-15 | 2019-01-22 | Nuscale Power, Llc | Internal dry containment vessel for a nuclear reactor |
| US11594342B2 (en) | 2007-11-15 | 2023-02-28 | Nuscale Power, Llc | Evacuated containment vessel for nuclear reactor |
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