JPH0551921B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital control device that tracks a standby side CPU of a process control device or the like in which central processing units are multiplexed.

A conventional control device of this type is shown in FIG. In the figure, 1 is a control device, and 2 is a process controlled by this control device 1.

The control device 1 includes a redundant A-system central processing unit (hereinafter referred to as CPu-A system) 3, a B-system central processing unit (hereinafter referred to as CPu-B system) 4, and a process input/output unit (hereinafter referred to as PIO). unit) 5, an input/output I/O bus 6 that connects the two CPu-A systems 3, CPu-B system 4 and a process input/output device (hereinafter referred to as PIO) 5, and a dual system switching circuit 7.
It consists of

The dual system switching circuit 7 includes the CPu-A system 3 and the CPu
- The emergency relay output from the B system 4 is input, and its output is connected to the PIO unit 5.

The CPu-A system 3 and the CPu-B system 4 have exactly the same hardware configuration and consist of three devices: an arithmetic processing unit 8, a computer coupling device 9, and a bus driver 10.

A computer coupling device (hereinafter referred to as CLA) 9 is connected to the CLA 9 in the other CPU, and a bus driver 10 is connected to the I/O bus 6.

PIO unit 5 has bus receiver 11 and PIO 12
The bus receiver 11 is composed of an I/O bus 6
Furthermore, the PIO 12 is connected to the process 2 and the dual system switching circuit 7.

Next, the operation will be explained. CPu-A series 3,
The CPu-B system 4 performs control calculations based on the process input/output values input from the PIO unit 5 and the output state of the dual system switching circuit 7, and outputs the results to the PIO unit 5.

The I/O bus 6 has a multi-port property that allows two or more bus drivers 10 and bus receivers 11 to be connected at the same time.
The B system 4 can freely input/output access to the PIO unit 5.

The dual system switching circuit 7 outputs a control command or a standby command to the CPu from the respective emergency relay outputs of the CPu-A system 3 and the CPu-B system 4. The CPu-A system 3 and the CPu-B system 4 can read the output signals of these dual system switching circuits 7 via the PIO unit 5.

The CPu-A system 3 and the CPu-B system 4 have completely the same software configuration. This is shown in Figure 2.

Software is operating system 20
and two tasks, namely control task 21,
It consists of a CLA reception task 22.

The control task 21 is periodically activated by the operating system (hereinafter referred to as OS) 20 at every predetermined control period, and performs PIO input processing and control calculation processing. Furthermore, the double system switching circuit 7
When outputting control commands to CPU, PIO output processing and control data transmission processing are performed. Conversely, when a standby command is output to the own system CPU,
PIO output processing and control data transmission processing are bypassed, and only CLA reception data acquisition processing is performed.

The CLA reception task 22 is activated by a CLA input interrupt that occurs when control data is transmitted from another system CPU.

Next, the operation of the software is controlled by the dual system switching circuit 7.
sends a control command to CPu-A system 3, and CPu-B system 4
A case will be explained in which a standby command is output to. At this time, in the CPu-A system 3, the under-control flag 23 shown in FIG. 2 becomes "YES" and the waiting flag 24 becomes "NO", and conversely, in the CPu-B system 4, the under-control flag 23 becomes "NO". The standby flag 24 is set to "YES". Therefore, CPu-A
System 3 executes PIO input processing, control calculation processing, PIO output processing, and control data CLA transmission processing.
In other words, the CPu-A system 3 controls the process 2, and also transfers and outputs all control calculation data (PIO input value, logical intermediate value, analog intermediate value, PIO output value) to the CPu-B system 4 via the CLA 9. are doing. Note that the intermediate value is an intermediate result in the control calculation process. For example, a flip-flop is set by the logical product of two PIO input values and reset by another PIO input value, and the logical sum of the other PIO input value and the flip-flop output becomes one PIO. If we pay attention to the case where the output value is an output value, the above-mentioned logical product and flip-flop output are intermediate values.

On the other hand, in the CPu-B system 4, as the CPu-A system 3 executes control data CLA transmission processing, the CLA
When an input interrupt occurs, the CLA reception task is activated, and the control calculation data from the CPU-A system 3 is sent to the CLA.
The received data is stored in the buffer area 25.
PIO input processing and control calculation processing are also executed in control task 21 of CPU-B system 4, but after execution, CLA
Received data import processing is performed. The CLA reception data import process is a process for importing the contents of the CLA reception data buffer area 25 into the control calculation data area.
- Control calculation data possessed by B system 4 and CPu-A system 3
is exactly equal to that of . That is, CPU−
Since the B system 4 executes PIO input processing and control calculation processing, it is expected that the control data held by the CPU-B system 4 is equal to that of the CPU-A system 3. However, due to some factors, such as turning off the power to the standby system for maintenance, or turning off the PIO
Differences may occur in the control calculation data of both systems due to differences in input processing timing. Even in those cases, this process ensures that the differences are resolved. Therefore, even if the CPu-A system 3 goes down, the CPu-B system 4 can back up control to the pump press.

The emergency relays of each CPUu-A system 3 and CPU-B system 4 are set when an error is detected by a self-diagnosis function such as occurrence of a memory parity error, invalid instruction, or watchdog timer overflow. The dual system switching circuit 7 connects each CPu-A system 3, CPu
The control command and standby command for each CPU are calculated from the set/reset state of the emergent relay of the -B system 4, and the operation is shown in FIGS. 3A and 3B. FIG. 3A is a block diagram showing the command system of the input and output states of the dual system switching circuit 7, and FIG.
3 is a logic diagram showing the functions of the heavy system switching circuit 7. FIG.
The function shown in FIG. 3B outputs the abnormal state of each CPu in response to the states of the A and B system emergency relay outputs of the CPu-A system 3 and CPu-B system 4, respectively.

As described above, in the control device 1, the standby CPU
Since the control CPU is always tracked via the CLA9, even if the control CPU goes down, the standby CPU can automatically back up control, and the switchover is bumpless. , the reliability of the control device itself can be improved.

Since this type of conventional digital control device is configured as described above, all control calculation data must be transferred from the controlling CPU to the standby CPU, and for this reason, control data CLA transmission processing As a result, there are drawbacks such as the inability to reduce the activation period of the control task, that is, the sampling period of the control.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above. In other words, among the calculated values, it is the one that will be used the next time the control task operation is executed.For example, if we focus on the part consisting of the AND, flip-flop, and OR mentioned above, the flip-flop output This is software for controlling processes activated in the control calculation process of a control task, such as the above-mentioned AND, The part consisting of a flip-flop and an OR is one arithmetic circuit.) An analog intermediate value that stores the past value of
From the CPU that is controlling only logical intermediate values to the CPU that is waiting
The object of the present invention is to provide a digital control device that can speed up the control sampling period by transmitting the data to the computer.

An embodiment of the present invention will be described below with reference to the drawings.

The hardware configuration is exactly the same as the conventional one shown in FIG. In addition, the software configuration is the fourth
It consists of the flowchart shown in the figure.

In the control data CLA transmission process shown in FIG. 4, while the conventional one transmits all control data to the CLA 9, in the embodiment of the present invention, the control calculation data includes, for example, the integrator circuit output value, flip-flop output value, timer It is programmed in advance to select and transmit CLA only analog intermediate values and digital intermediate values in which past calculation values such as count values are stored.

Which of the analog intermediate value and digital intermediate value should be transferred to the standby system as a past value?
Since this is known at the time of creating the arithmetic circuit, it is possible to program the control data CLA transmission process to select and transmit only past values, as described above. Moreover, if only past values are collected in a specific area in the area storing intermediate values, the transmission process will be further speeded up. The number of past values required varies depending on the system to which the device is applied. Therefore, which past value in the past value area should be selected is set in the past value selection table, and in the control data CLA transmission process, the table is referred to and only the necessary past values are transmitted. If configured, a flexible device can be configured according to the system to which it is applied. At this time, the past value receiving side refers to the past value selection processing table and sets the received past value in the corresponding part of the intermediate value CLA reception data buffer area.

Similarly, regarding the CLA reception data import process, the intermediate value CLA reception data buffer area 25
The program has been modified to take in the intermediate value stored in the memory at a predetermined address.

Next, the operation of such a software configuration will be described. Note that the hardware operations such as the dual system switching circuit 7 and PIO 5 are the same as in the conventional system. In addition, regarding the software configuration, OS20, control task 2
1a, intermediate value CLA reception task 22a, and other configurations are basically the same as in the past, but the operation of the software will be explained in detail.

The CPU under control executes PIO input processing, control calculation processing, PIO output processing, and control data CLA transmission processing. In other words, the controlling CPU controls process 2 and sends only predetermined logical intermediate values and analog intermediate values to the waiting CPU.
Transfer output via CLA9. These intermediate values to be transferred may be analog intermediate values that store past values of arithmetic circuits that require past values, or logical intermediate values such as integration circuit outputs, flip-flop outputs, and timer count values.

On the other hand, in the waiting CPU, the intermediate value CLA reception task 22a is activated and stores the intermediate value data from the controlling CPU in the intermediate value CLA reception buffer area 25. Control tasks can also be performed on standby CPUs.
PIO input processing and control calculation processing are executed, but after execution, CLA reception data import processing is performed, and the integration circuit output, flip-flop output value, timer count value, etc. are the control data received from the controlling CPU via CLA9. Refreshed to value.
Then, the next control calculation process is executed based on the refreshed control data value, that is, the past value data of the CPU under control.

Since PIO unit 5 has two ports, if the control period is sufficiently small compared to the time constant of process 2, the process input values of the controlling CPU and the standby CPU are almost the same, and Since calculations that require past values are performed based on data received from the controlling CPU, the controlling CPU
The contents of the calculation data between the standby CPU and the standby CPU are always exactly the same, so the backup switching operation of the standby CPU can be performed bumplessly.

As described above, according to the digital control device of the present invention, data transfer between CPUs is performed only for past value data of arithmetic circuits that require past values, so transfer time can be shortened and control can be controlled. This has the effect of providing a control device with a short calculation cycle, that is, with high controllability.

[Brief explanation of drawings]

Figure 1 shows a basic hardware configuration diagram of a digital control device, Figure 2 shows a conventional software configuration diagram applied to this digital control device, and Figure 3A shows a diagram of a conventional software configuration applied to a digital control device. Figure 3B is a block diagram showing the input/output relationship of the dual system switching circuit.
The figures each show a software configuration diagram according to an embodiment of the present invention. 1...Digital control device, 2...Process,
3...CPu-A series, 4...CPu-B series, 5...
PIO unit, 6...I/O bus, 7...Double system switching circuit, 8...CPu, 9...CLA, 10...
driver. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1 Acts as the main system in response to control commands and performs input processing to input process input values from the process, control calculation processing to perform control calculations based on the process input values, and output processing to output the results of the control calculations. On the other hand, two central processing units 3 and 4 having the same configuration perform the input processing and control calculation processing as a standby system in response to a standby command, and supply the results of the control calculation to the process, and input the process input. a process input/output unit 5 which supplies values to the two central processing units 3 and 4; and a process input/output unit 5 which receives state signals from the two central processing units 3 and 4 and corresponds to the signal indicating a normal state among these state signals. In the digital control device, the dual system switching circuit 7 provides the control command to one of the central processing units 3, 4 and provides a standby command to the other central processing unit 3, 4. Each of the central processing units 3 and 4 has a computer coupling device 9 for transmitting and receiving data with the other central processing unit 4 and 3, and in addition to the input processing, control processing and output processing,
a control task 21a that executes a process of transmitting the past values saved by the arithmetic circuit that requires past values for the next calculation to the standby system via the computer coupling device 9 when the arithmetic circuit becomes the main system; , a receiving task 22 that receives the past values via the computer coupling device 9.