JPS6316781B2 - - Google Patents
Info
- Publication number
- JPS6316781B2 JPS6316781B2 JP58076160A JP7616083A JPS6316781B2 JP S6316781 B2 JPS6316781 B2 JP S6316781B2 JP 58076160 A JP58076160 A JP 58076160A JP 7616083 A JP7616083 A JP 7616083A JP S6316781 B2 JPS6316781 B2 JP S6316781B2
- Authority
- JP
- Japan
- Prior art keywords
- computer
- level
- computers
- main
- slave
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005540 biological transmission Effects 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000007935 neutral effect Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000003745 diagnosis Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は上位マルチ構成、下位分散構成をとる
計算機間の伝送ラインの切換装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a switching device for transmission lines between computers having an upper multi-configuration and a lower-level distributed configuration.
従来の切換装置は伝送ラインを一括して上位計
算機システムの主系に接続していた。このため、
下位計算機を分散構成にした場合、分散した各計
算機毎に上位マルチ計算機システムの主系・従系
に選択して接続できない欠点があつた。
Conventional switching devices connect the transmission lines all at once to the main system of the host computer system. For this reason,
When the lower-level computers were configured in a distributed configuration, there was a drawback that each distributed computer could not be selectively connected to the main system or slave system of the upper-level multi-computer system.
本発明の目的は、分散構成をとつた下位の計算
機が、計算機毎に上位マルチ計算機システムの任
意の計算機側に接続できる装置を提供するにあ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide a device in which lower-level computers in a distributed configuration can be connected to any computer side of a higher-level multi-computer system.
本発明の要点は上位側マルチ計算機システムが
各計算機毎に、計算機ダウン情報としてWDT
に、下位側の複数の計算機の個別の接続情報とし
て下位側の各計算機毎にそれぞれ、DO1ビツト
を出力し、下位側の各計算機は、このWDTと自
計算機と対応したDOとのADD条件成立側の上位
の計算機に伝送ラインを切換える計算機間伝送ラ
イン切換装置を介して接続するにある。
The main point of this invention is that the upper multi-computer system uses the WDT as computer down information for each computer.
Then, each lower-level computer outputs the DO1 bit as individual connection information for multiple lower-level computers, and each lower-level computer determines whether the ADD condition is satisfied between this WDT and the DO corresponding to its own computer. The computer is connected to the host computer via an intercomputer transmission line switching device that switches the transmission line.
以下、本発明を第1図ないし第5図により説明
する。
The present invention will be explained below with reference to FIGS. 1 to 5.
第1図は切換装置であり、上位側計算機システ
ムはA系計算機1、B系計算機2から構成したデ
ユープレツクス方式マルチ計算機システムであ
り、A系・B系共に下位側複数計算機10,20
との情報を伝達する計算機間伝送ライン3,4
と、各計算機ダウン情報として、下位側計算機一
括にウオツチドツグタイマ(WDT)5,6と、
下位側計算機と対応した個別接続情報としてプロ
セス入出力装置のデイジタル出力(DO)7,8
を備えている。計算機間伝送ラインは下位側の各
計算機毎に伝送ライン切換装置11,21を介し
て各計算機と接続され、上位側計算機A系・B系
から出力するWDT5,6とDO7,8とのAND
条件の成立で、A系又はB系の伝送ラインを接続
し、条件不成立ではニユートラル状態となる。 Figure 1 shows a switching device, and the upper computer system is a duplex multi-computer system consisting of an A-system computer 1 and a B-system computer 2, and both the A-system and B-system have multiple lower-order computers 10, 20.
Inter-computer transmission lines 3 and 4 that transmit information with
And, as each computer down information, watchdog timer (WDT) 5, 6 is sent to the lower computer all at once.
Digital output (DO) 7, 8 of the process input/output device as individual connection information corresponding to the lower-level computer
It is equipped with The inter-computer transmission line is connected to each computer on the lower side via transmission line switching devices 11 and 21, and is an AND between WDT5, 6 and DO7, 8 output from the upper side computers A system and B system.
If the condition is satisfied, the A-system or B-system transmission line is connected, and if the condition is not satisfied, a neutral state is established.
第2図、第3図は切換装置の動作例のタイムチ
ヤートである。第2図は上位マルチ計算機の主系
側計算機に下位側計算機を接続する場合、第3図
は上位マルチ計算機の従系側計算機に下位側計算
機を接続する場合を示す。両図共に時刻100で
上位計算機のA系を主系、B系を従系として立上
げたことを示す。時刻101では主系であるA系
計算機がダウンし、B系が主系に切換わる。時刻
102はダウンしたA系が回復し、従系となつて
動作し、B系は主系のままであることを示す。
WDTは計算機動作中でオン、ダウンでオフとな
る。 FIGS. 2 and 3 are time charts of an example of the operation of the switching device. FIG. 2 shows a case where a lower-order computer is connected to the main computer of a higher-order multi-computer, and FIG. 3 shows a case where a lower-order computer is connected to a slave-side computer of a higher-order multi-computer. Both figures show that the A system of the host computer was started up as the main system and the B system as the slave system at time 100. At time 101, the A-system computer, which is the main system, goes down, and the B-system is switched to the main system. Time 102 indicates that the A system that went down has recovered and operates as a slave system, and the B system remains as the main system.
WDT is on when the computer is operating and off when the computer is down.
第2図は下位側計算機を主系側の上位計算機と
接続させるので、A系DO7をオンとし、B系
DO8をオフとして、主系であるA系の条件が成
立し接続される。次に、時刻101でA系ダウン
となると、A系WDT5がオフとなり、構成制御
によつてB系が主系に切換わり、B系DO8をオ
ンとすることにより、B系に接続される。以降、
時刻102でA系がダウン状態から回復し、従系
となるが、主系であるB系に接続されたままであ
る。 In Figure 2, the lower computer is connected to the upper computer on the main side, so turn on A system DO7 and
When DO8 is turned off, the conditions for system A, which is the main system, are met and connection is established. Next, when the A system goes down at time 101, the A system WDT 5 is turned off, the B system is switched to the main system by configuration control, and is connected to the B system by turning on the B system DO8. onwards,
At time 102, system A recovers from the down state and becomes a slave system, but remains connected to system B, which is the main system.
第3図は下位側計算機を従系の上位計算機と接
続し、テスト等の業務を行なう例を示す。時刻1
00では従系であるB系DO8をオンとし、主系
であるA系DO7をオフとすることにより、条件
はB系が成立し接続される。次に、時刻101で
A系がダウンすると、構成制御が動作し、B系が
主系となるため、DO8をオフとすることによ
り、A系・B系共に条件不成立となり切換装置は
従系が無いため、ニユートラル状態となる。次
に、時刻102でA系が従系に回復すると、DO
7およびWDT5をオンとすることにより、条件
が成立し、切換装置は従系であるA系に接続さ
れ、テスト等の業務も回復する。 FIG. 3 shows an example in which a lower-level computer is connected to a subordinate higher-level computer to perform tasks such as testing. Time 1
At 00, the B system DO8, which is the slave system, is turned on, and the A system DO7, which is the main system, is turned off, so that the condition for the B system is established and the connection is established. Next, when the A system goes down at time 101, the configuration control is activated and the B system becomes the main system, so by turning off DO8, the condition is not satisfied for both the A system and the B system, and the switching device becomes the slave system. Since there is no one, the state is neutral. Next, when system A recovers to the slave system at time 102, DO
By turning on WDT 7 and WDT 5, the conditions are met, the switching device is connected to the slave system A, and operations such as testing are restored.
次に、下位側計算機の管理と上位側デユープレ
ツクス方式マルチ計算機システムの構成制御を第
4図で述べる。下位側計算機の接続先は上位側計
算機で、下位側計算機1台毎に第4図aの下位側
計算機接続モード遷移図に示すモードにより管理
し、このモードの移行指示は人が判断し操作す
る。切離モードは下位側計算機を上位側のいずれ
にも接続せず切換装置をニユートラルとするモー
ドであり、従系接続モードは下位側計算機を上位
側従系計算機に接続するモードであり、プログラ
ムの開発・テスト時に使用する。主系接続モード
は下位側計算機を上位側主系計算機に接続するモ
ードであり、通常のオンライン業務のモードであ
る。これら3種のモードを下位の各計算機に対応
させて、上位側計算機の共有メモリ内に置き管理
する。 Next, the management of lower-level computers and the configuration control of the upper-level duplex type multi-computer system will be described with reference to FIG. The connection destination of the lower-level computer is the higher-level computer, and each lower-level computer is managed by the mode shown in the lower-level computer connection mode transition diagram in Figure 4a, and instructions for switching to this mode are determined and operated by humans. . The isolation mode is a mode in which the switching device is set to neutral without connecting the lower computer to any of the upper computers, and the slave connection mode is the mode in which the lower computer is connected to the upper slave computer, and the program Used during development and testing. The main system connection mode is a mode in which a lower-order computer is connected to an upper-layer main computer, and is a mode for normal online business. These three types of modes are associated with each lower-level computer, and are stored and managed in the shared memory of the higher-level computer.
第4図bに示した構成制御流れ図は、プログラ
ムとして上位側の各計算機に格納し、計算機起動
時・デユープレツクス方式マルチの系切換時(従
系から主系への切換時等)及び下位側計算機接続
モード移行指示操作時に動作する。 The configuration control flowchart shown in Figure 4b is stored as a program in each higher-level computer, and is used when starting up the computer, when switching systems in duplex multi-systems (such as when switching from the slave system to the main system), and when the lower-level computer Operates when instructing to switch to connection mode.
第2図、第3図で時刻100の場合、A系計算
機は主系のため構成制御50を実行し、B系計算
機は従系のため構成制御51を実行する。次に、
時刻101ではB系が従系から主系に切換わるこ
とにより、B系計算機は構成制御50を実行す
る。時刻102ではA系が従系で起動されるた
め、A系計算機で構成制御51を実行する。以上
により、上位側で管理している下位側計算機接続
モードの状態と構成制御によつて出力するDOが
決定し、第2図、第3図タイムチヤートのDO
7,DO8の通りの動作を行ない希望する主系・
従系の計算機へ下位側計算機個別に接続できる。 At time 100 in FIGS. 2 and 3, the A-system computer is the main system and therefore executes the configuration control 50, and the B-system computer is the slave system and therefore executes the configuration control 51. next,
At time 101, the B system is switched from the slave system to the main system, so that the B system computer executes the configuration control 50. At time 102, since the A system is activated as a slave system, the configuration control 51 is executed on the A system computer. As described above, the DO to be output is determined by the state of the lower-level computer connection mode managed by the higher-level side and the configuration control, and the DO shown in the time charts in Figures 2 and 3 is determined.
7. Do the desired main system as per DO8.
Lower-level computers can be individually connected to subordinate computers.
デユープレツクス方式マルチ計算機は、計算機
毎にそれぞれ主系・従系・ダウン状態の各モード
を持ち、通常は主系・従系で動作し相互診断を行
なう。主系で異常が発見された場合、ダウンし、
待機していた従系が主系に切換わり負荷を担う。 In a duplex type multi-computer, each computer has a main mode, a slave mode, and a down mode, and normally operates in the main mode and the slave mode and performs mutual diagnosis. If an abnormality is detected in the main system, it will go down and
The slave system that was on standby switches to the main system and takes on the load.
なお、第5図は切換装置の接続先と上位側計算
機の出力条件の対応表であり、A系・B系の出力
したこの表の条件により切換装置の接続先が決定
される。 Note that FIG. 5 is a correspondence table between the connection destination of the switching device and the output conditions of the host computer, and the connection destination of the switching device is determined by the conditions in this table output from the A system and B system.
なお、下位側計算機10,20を同一処理と
し、デユアル方式マルチ計算機として動作させて
も、実施例と同一構成で、下位側計算機の信頼性
が向上し、第6図に示すように上位側計算機を3
台系とし、複数の下位側計算機をそれぞれ分散さ
せて、A系、B系、C系へ接続すれば、上位側計
算機はロードシエア方式のマルチ計算機で動作す
る。 Note that even if the lower-level computers 10 and 20 perform the same processing and operate as a dual-system multi-computer, the reliability of the lower-level computers improves with the same configuration as in the embodiment, and as shown in FIG. 3
If a plurality of lower-level computers are distributed and connected to the A, B, and C systems, the upper-level computers will operate as multi-computers in a load sharing system.
本発明によれば下位側計算機を個別に上位側マ
ルチ計算機システムの任意の計算機に接続でき
る。
According to the present invention, lower level computers can be individually connected to any computer in the upper level multi-computer system.
第1図は伝送ライン切換装置の系統図、第2図
は主系側の上位計算機に下位側計算機を接続した
例を示すタイムチヤート、第3図は従系の上位計
算機に下位側計算機を接続した例を示すタイムチ
ヤート、第4図は上位側で管理する下位側計算機
接続モードの遷移図a及び切換装置に関する上位
側デユープレツクス方式マルチ計算機の構成制御
の流れ図b、第5図は切換装置接続先対応図、第
6図は本発明の変形例の系統図である。
1,2……上位側マルチ計算機A系及びB系、
3,4……計算機間伝送ライン、5,6……ウオ
ツチドツグタイマー信号、7,8……PI/Oデ
イジタル出力信号、11,21……計算機間伝送
ライン切換装置、10,20……下位側計算機、
50,51,52……構成制御処理。
Figure 1 is a system diagram of the transmission line switching device, Figure 2 is a time chart showing an example of connecting a lower-level computer to the upper-level computer of the main system, and Figure 3 is a diagram of connecting the lower-level computer to the higher-level computer of the slave system. Figure 4 is a transition diagram of the lower-level computer connection mode managed by the higher-level side, b is a flowchart of the configuration control of the upper-level duplex type multi-computer regarding the switching device, and Figure 5 is the connection destination of the switching device. The corresponding diagram, FIG. 6, is a system diagram of a modification of the present invention. 1, 2...Upper side multi-computer A system and B system,
3, 4... Inter-computer transmission line, 5, 6... Watchdog timer signal, 7, 8... PI/O digital output signal, 11, 21... Inter-computer transmission line switching device, 10, 20... ...lower side calculator,
50, 51, 52... Configuration control processing.
Claims (1)
位側の複数の計算機を結ぶ伝送ラインと前記下位
側計算機に台数分の点数を持つプロセス入出力装
置のデイジタル出力と計算機稼動情報としてウオ
ツチドツグタイマを備えたマルチ計算機と、この
マルチ計算機の複数の前記伝送ラインを切換え、
前記下位側計算機の接続先を決定する切換装置に
おいて、 前記下位側の計算機毎に、前記マルチ計算機の
出力する前記下位側計算機の前記デイジタル出力
と前記ウオツチドツグタイマのAND条件成立側
に前記伝送ラインを接続することを特徴とする計
算機間伝送ライン切換装置。[Claims] 1. A transmission line connecting a plurality of lower-level computers for each computer as an upper-level computer system, and digital output and computer operation information of a process input/output device having the same number of points as the lower-level computers. switching a multi-computer equipped with a watchdog timer and the plurality of transmission lines of the multi-computer;
In the switching device for determining the connection destination of the lower-level computer, for each lower-level computer, the digital output of the lower-level computer outputted from the multi-computer and the watchdog timer are connected to the side where an AND condition is satisfied. An inter-computer transmission line switching device characterized by connecting transmission lines.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58076160A JPS59202566A (en) | 1983-05-02 | 1983-05-02 | Transmission line switching device between computers |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58076160A JPS59202566A (en) | 1983-05-02 | 1983-05-02 | Transmission line switching device between computers |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59202566A JPS59202566A (en) | 1984-11-16 |
JPS6316781B2 true JPS6316781B2 (en) | 1988-04-11 |
Family
ID=13597301
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58076160A Granted JPS59202566A (en) | 1983-05-02 | 1983-05-02 | Transmission line switching device between computers |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59202566A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6385966U (en) * | 1986-11-26 | 1988-06-04 | ||
JPH02280497A (en) * | 1989-04-20 | 1990-11-16 | Sanyo Electric Co Ltd | Remote controller |
-
1983
- 1983-05-02 JP JP58076160A patent/JPS59202566A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6385966U (en) * | 1986-11-26 | 1988-06-04 | ||
JPH02280497A (en) * | 1989-04-20 | 1990-11-16 | Sanyo Electric Co Ltd | Remote controller |
Also Published As
Publication number | Publication date |
---|---|
JPS59202566A (en) | 1984-11-16 |
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