JPH10124338A - Parallel processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cope with not only a fault of a ring bus and a processor, but also a fault of a processor for input and output. SOLUTION: The parallel processor is equipped with a 1st ring bus which connects processors 2(P0, P1, P2, and P3) and 1st nodes 1(0A, 3A, 2A, and 1A) connected to the respective processors on a ring through 1:1 unidirectional bus connections and a 2nd ring bus which connects 2nd nodes 1(0B, 1B, 2B, and 3B) connected to the respective processors on a ring reversely to the order through 1:1 unidirectional bus connections. Some processors (P1 and P3) among the processors are connected to an input/output bus 4 and the processors (P1 and P3) for input and output performs input from and output to the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a parallel computer composed of a plurality of processors for processing, which can continue processing when a single failure occurs, thereby achieving high reliability. The present invention relates to a parallel processing device.

[0002]

2. Description of the Related Art FIG.
This will be described with reference to FIG. FIG. 6 shows, for example, Ole Kjolle
r et al. “SCI Dual Ring Architecture with Self-Recove
ry ”,“ The Fourth International Workshop on SCI-b
FIG. 33 is a diagram showing a conventional parallel processing device shown in Sponsored by SCIzzL, ased-High-Performance Low-Cost Computing, pp. 33-37, 1995.

In FIG. 6, reference numeral 1 denotes a node (communication node) interposed between a processor and another processor to communicate with each other, 2 denotes a processor, and 3 denotes a unidirectional node for exchanging data between the nodes. This is a data transfer line (communication bus). Note that node 1 has nodes 0A, 1A,
Eight locations of 2A, 3A, 0B, 1B, 2B, 3B are shown. Further, the processor 2 has P0, P1, P2, P
Three of three are shown.

Next, the operation of the conventional parallel processing apparatus will be described with reference to FIG.

FIG. 6 shows four parallel processors P0,
This shows a parallel computer composed of P1, P2, and P3, where each processor is connected to two nodes 1 each, and each node 1 is connected to a ring configuration.

That is, the processor P0 has the node 0A
And two nodes 1 of the node 0B. The processor P1 has two nodes 1A and 1B.
Nodes 1 are connected. The processor P2
Is connected to two nodes 1 of a node 2A and a node 2B. Further, the processor 3 has a node 3A.
And two nodes 1 of the node 3B are connected. Note that nodes with an A at the end of each node 1 are connected to the ring in descending order of the number (or in ascending order). The same applies to B, although the connection order is reversed.

If a failure occurs in any node 1 or data transfer line 3, the ring including that node 1 or data transfer line 3 is invalidated, and the other ring is used. , Enabling continuous processing.

[0008]

The conventional parallel processing device as described above is configured as described above.
When a failure occurs in the node 1 or the data transfer line 3, the failure can be dealt with. However, when a failure occurs in the processor 2 itself, or when a failure occurs in a part performing data transfer with the outside. Had a problem that it could not cope with those obstacles.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to provide a plurality of processors for input / output and cope with a case where a failure occurs in a portion for performing data transfer with the outside. It is an object of the present invention to provide a parallel processing device that can continuously perform processing without affecting processing being executed even when a failure occurs in a processor.

[0010]

According to the present invention, there is provided a parallel processing apparatus comprising a plurality of processors and a first node connected to each processor which are sequentially connected on a ring by a one-to-one unidirectional bus connection. A parallel processing apparatus comprising: one ring bus; and a second ring bus in which second nodes connected to each processor are connected on the ring in a direction opposite to the above by a one-to-one unidirectional bus connection. , A part of the plurality of processors is connected to an input / output bus, and the input / output processor performs input / output with an external device.

Further, in the parallel processing device according to the present invention, the input / output processor includes first and second input / output processors, and the first input / output processor includes a second input / output processor.
When the status information from the second input / output processor does not arrive, it is determined that a failure has occurred in the second input / output processor, and the input / output processing performed by the second input / output processor is substituted. Is what you do.

Further, in the parallel processing apparatus according to the present invention, any one of the plurality of processors has a state monitoring mechanism of an adjacent processor on a ring, and information of a task executed by the adjacent processor is provided. When the adjacent processor fails, the arbitrary processor logically disconnects the adjacent processor and re-executes a task that was scheduled to be executed by the adjacent processor. .

Further, in the parallel processing apparatus according to the present invention, any one of the plurality of processors has a state monitoring mechanism of an adjacent processor on a ring, and a task among the tasks executed by the adjacent processor. Information of the high-priority task is stored in advance, the arbitrary processor executes the high-priority task at the same time as the adjacent processor, and when a failure occurs in the adjacent processor, To logically separate the processor to be executed.

Further, in the parallel processing apparatus according to the present invention, any one of the plurality of processors has a state monitoring mechanism of an adjacent processor on a ring and is equivalent to a task executed by the adjacent processor. Information of a task having a shorter execution time than that of the task, and the arbitrary processor logically disconnects the adjacent processor when the adjacent processor fails, In this case, the task that is to be executed by the processor to be executed is substituted by the task having a short execution time.

Further, in the parallel processing apparatus according to the present invention, the plurality of processors sends a token indicating their respective states on a ring bus, and a predetermined master processor among the plurality of processors sends the token to the ring bus. Investigation is to logically separate the failed processor.

Further, in the parallel processing device according to the present invention, the master processor previously stores information of a task having a function equivalent to a task executed by the plurality of processors and having a shorter execution time than the task, When a failure occurs in the processor, the master processor substitutes a task scheduled to be executed by the failed processor for the task with a short execution time.

Furthermore, the parallel processing device according to the present invention is
A predetermined master processor among the plurality of processors includes first and second master processors, and the first master processor is configured to perform the second master processor when the second master processor fails. It replaces the master processor.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. The configuration of the parallel processing device according to the first embodiment of the present invention will be described with reference to FIG. FIG.
1 is a diagram showing a configuration of a parallel processing device according to Embodiment 1 of the present invention. In the drawings, the same reference numerals indicate the same or corresponding parts.

In FIG. 1, reference numeral 1 denotes a node (communication node) interposed between a processor and a processor for communication with another processor, 2 denotes a processor, 2A denotes an input / output processor, and 3 denotes data between the nodes. Is a unidirectional data transfer line (communication bus) for exchanging data. further,
Reference numeral 4 denotes an input / output bus for inputting / outputting data between the input / output processor 2A and the outside. Node 1
Are nodes 0A, 1A, 2A, 3A, 0B, 1B, 2
Eight positions B and 3B are shown. Processor 2
Indicates two of P0 and P2, and two processors P1 and P3 are shown for the input / output processor 2A, and a total of four processors are shown.

Next, the operation of the parallel processing apparatus according to the first embodiment will be described with reference to FIG.

The entire operation except for input and output is the same as that described in the description of the conventional example. In the first embodiment, a function dedicated to data input / output is newly provided in, for example, the processors P1 and P3. External data input is normally performed only via the processor P3, for example.
Data output to the outside also goes through the processor P3.

On the other hand, the processor P1 is
Is constantly monitored. That is, the processor P3
Sends its state periodically to the processor P1. If the periodic signal from the processor P3 has not arrived, the processor P1 determines that the processor P3 has gone down. After that, the processor P1
3 is performed instead of the input / output processing performed.

Thus, in the configuration shown in FIG. 1, even if a fault occurs at any point, it is separated from the fault.
Processing can be continued.

According to the first embodiment, in a parallel processing device having a plurality of processors 2 and 2A, two nodes 1 for coupling with other processors 2 and 2A are connected to each processor 2 and 2A. , All processors 2, 2A
Is connected on the ring by a one-to-one unidirectional bus connection, and the other node is also connected by a one-to-one unidirectional bus connection. By providing a plurality of processors 2A that perform input / output, even if a failure occurs in any part of the ring 3, the node 1, the processor 2, and the input / output processor 2A, the processing can be automatically separated and continued. .

That is, the parallel processing device according to the first embodiment includes a plurality of identical processors that perform processing, and connects two nodes to each processor. One node connected to each processor is sequentially connected by a one-to-one bus, and the nodes are connected on a ring. Further, another node of each processor is connected in the reverse direction by another one-to-one bus in order, and is connected in a ring shape. For example, currently available SCI (Scalable Coherent Interface) bus [ANSI / IE
EE Std 1596-1992] corresponds to this ring bus. Since the input / output processor 2A and the input / output bus 4 are provided, not only the failure of the ring bus 3 but also the failure of the processor 2 and the failure of the input / output processor 2A can be dealt with.

Embodiment 2 FIG. The configuration of a parallel processing device according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 2 is a diagram illustrating a parallel processing device according to a second embodiment of the present invention, in which a part of the entire configuration diagram shown in FIG. 1 is enlarged.

In the case of a ring bus configuration, each processor 2, 2A is connected to an adjacent processor. Therefore, it is efficient if the adjacent processors also perform fault monitoring of each processor.

Thus, as shown in FIG. 2, for example, the processor P0 monitors the state of the processor P1. At this time, the status information of the processor P1 is periodically sent to the processor P0. That is, the processor P1 performs a self-diagnosis or the like by itself, and sends the result to the processor P0. Apart from this, the processor P1 always sends information on the task to be executed to the processor P0 prior to the execution of the task.

The processor P0 determines a state periodically sent from the processor P1, and determines whether the processor P1 is operating normally. If the status report itself is not sent within a predetermined time due to a report of the occurrence of a fault or an internal fault of the processor P1, the processor may operate normally. P0 is determined to be a failure.

After that, the processor P0
1 is disconnected from the entire system. In other words, the other processors P2 and P2 cannot be physically separated.
3 is notified of the case of the processor P1 in which the fault has occurred, and thereafter, it is logically separated and handled.

However, the task processing of the processor P1 which was operating at the time of the occurrence of the fault needs to be reprocessed. Therefore, using the task information sent to the processor P0 prior to the execution of the task, the processor P0 re-executes the same task after the occurrence of a failure. As a result, after the processor P1 is disconnected, the task can be re-executed, and continuous processing can be performed as a whole.

This procedure can be performed in a distributed manner because each processor can perform the processing on the adjacent processor, and the distance between the rings is short, so that the measures against the failure can be efficiently performed.

According to the second embodiment, the parallel processing apparatus according to the first embodiment includes the components of the first embodiment, and an arbitrary processor P0 is a state monitoring mechanism of an adjacent processor P1 on a ring. By storing information on tasks being executed by the processor P1, when a failure occurs in the processor P1, the processor P0 detects the failure and logically disconnects the processor P1 from the system. By re-executing the task that was being executed by the processor P1 on the processor P0, the processing can be continued even when a failure occurs in any processor.

That is, in addition to the configuration (means) of the parallel processing device according to the first embodiment, the parallel processing device according to the second embodiment is capable of monitoring the state of a certain processor 2A by, for example, an adjacent processor The processor 2A includes a mechanism for holding task information being executed by the processor 2A and a mechanism for holding task information being executed by the processor 2A.
When the failure of A occurs, the processor 2A can be disconnected from the ring from the adjacent processor 2. In the second embodiment, the failures are detected in a distributed manner between the adjacent processors 2 and 2A. Therefore, it is possible to efficiently detect a failure suitable for a ring bus connecting the processors between the adjacent processors.

Embodiment 3 FIG. Third Embodiment A parallel processing device according to a third embodiment of the present invention will be described with reference to FIG. FIG. 3 is a diagram showing a task list of a processor of a parallel processing device according to Embodiment 3 of the present invention.

In FIG. 3, reference numeral 5 denotes an example of a task list executed by the processor P1, and reference numeral 6 denotes a task list executed by the processor P0.

The base configuration of the third embodiment is the same as that of the second embodiment, and FIG. 2 is used as it is. That is, the state of the processor P1 is monitored by the processor P0, and if a failure occurs in the processor P1, this is disconnected.

In the second embodiment, after a failure occurs in the processor P1, the processor P0 attempts to execute the same task again based on the task information. However, depending on the application, this may not be enough in time. is there. In other words, in a case where the processing must be completed by a certain time, if the processing is re-executed after the failure of the processor P1, it will not be in time.

In the third embodiment, in the above case, the important tasks among the execution tasks of the processor P1 are similarly executed in advance by the processor P0 monitoring the failure. Then, this is used when a failure occurs.

In FIG. 3, it is assumed that six tasks A, B, C, D, E, and F are executed in the processor P1 monitored for a fault, as shown in a task list 5. At this time, a certain threshold (Threshold) is determined. For example, in this example, tasks A and B and task C,
A threshold was set where D, E, and F were distinguished. In short, it is assumed that tasks A and B above this threshold have a high priority, and tasks C, D, E and F have a low priority.

In the processor P0, the tasks A and B having a higher priority are executed at the same time as other tasks of the own processor P0 from among the processors P1 to be monitored. This is shown in task list 6 in FIG. The processor P0 is originally supposed to execute the tasks X, Y, and Z. Here, the tasks A and B having the higher priority of the processor P1 are simultaneously executed.

As described in the second embodiment, when a failure occurs in the processor P1, the processor P0 detects and isolates the failure, and the processor A0 executes the backup tasks A, The result of B is taken as the execution result of the separated processor P1. As a result, even if a failure occurs, the real-time processing result is not impaired,
Execution can continue.

According to the third embodiment, the parallel processing apparatus (parallel computer) according to the second embodiment includes the means according to the second embodiment, and further includes, among tasks executed by an arbitrary processor P1, For a task having a higher priority than a predetermined priority, the processor P0 adjacent to the processor P1 executes the tasks at the same time, so that when a failure occurs in the processor P1, the processor P0 detects the failure and the processor P1 Is logically separated from the system, and the execution result of the high-priority task, which was to be executed by the processor P1, is taken out from the processor P0, so that the processing can be continued even when a failure occurs in any processor.

That is, the parallel processing device according to the third embodiment includes, in addition to the means of the second embodiment, for example, a task executed by a processor P1 adjacent in a clockwise direction.
The high-priority task has a mechanism to be executed simultaneously in the processor P0. Therefore,
Even if the processor P1 breaks down, a process to be performed within a predetermined time can be executed as it is.

Embodiment 4 Embodiment 4 A parallel processing apparatus according to Embodiment 4 of the present invention will be described with reference to FIG. FIG. 4 is a diagram showing a task flow of the processor of the parallel processing device according to Embodiment 4 of the present invention.

In FIG. 4, reference numeral 7 denotes a general task flow.
Reference numeral 8 denotes a task flow when a failure occurs.

The task flow 7 in FIG. 4 shows that there are four tasks A, B, C, and D to be executed sequentially by a certain processor P1, and these tasks must be completed by time T. ing.

Now, in this processor P1,
It is assumed that a failure occurs while processing task A as shown in FIG. Further, as in the second embodiment, the processor P1
Is monitored in advance by the processor P0.
Suppose you know all the tasks that 1 performs.

As in the second embodiment, the processor P
After a failure has occurred at 1, the processor P0 detects this. After that, in the processor P0, the original task A,
Task A ', which requires less execution time than B, C and D,
B ', C', and D 'are prepared in advance, and are sequentially executed in the processor P0.

For example, the tasks A ′, B ′, C ′, and D ′ have the same processing contents as the tasks A, B, C, and D, but the execution time is reduced by lowering the processing accuracy. Are shortened. With this,
If task A was re-executed, the time T
The processing that cannot be made in time can be made in time by the processing of the same function.

According to the fourth embodiment, the parallel processing device (parallel computer) of the second embodiment includes the means of the second embodiment, and is equivalent to each task executed by an arbitrary processor P1. However, by preparing each task having a short execution time in the adjacent processor P0 due to low processing accuracy or the like, when a failure occurs in the processor P1, the processor P0 detects the failure. Then, the processor P1 is logically disconnected from the device (system), and the execution of the task scheduled to be executed by the processor P1 is performed by the processor P0 with a reduced processing time but with a shorter processing time of the same function. Thus, when a failure occurs in an arbitrary processor P1,
The processing can be continued continuously, and the processing can be completed within a predetermined time.

That is, in the parallel processing device according to the fourth embodiment, in addition to the means of the second embodiment, a high-speed execution version is prepared for all tasks in which the processing accuracy is reduced and the execution time is shortened. It has a mechanism. Therefore, even if the processor P1 breaks down, the processing performed within a predetermined time can be functionally executed, although the processing accuracy is slightly reduced.

Embodiment 5 A parallel processing device according to a fifth embodiment of the present invention will be described with reference to FIG. FIG. 5 is a diagram showing a token specifying a failure state from a processor of the parallel processing device according to the fifth embodiment of the present invention.

A token indicating the state of each processor P0, P1, P2, P3 is sent to the ring bus constituted by the communication bus 3 shown in FIG. For example, as shown in FIG. 5, each processor P0, P1, P2, P3
Executes the self-diagnosis program by itself and checks the internal state. As a result, if there is no abnormality inside, “1” is returned if abnormality is found, and “0” is returned to the token's own processor. Write to the location.

This token is always rotating on the ring bus. Each time the processors P0, P1, P2, P3 receive this token, they write the latest state at the position corresponding to the own processor, and then send it.

All processors P0, P1, P2, P
3, one processor, for example, processor P0
Is the master. The master processor P0 checks this content after the token has been sent, and if a faulty processor P1 is found,
The signal is transmitted to the other processors P2 and P3 so as to logically separate the processor P1. After that, the same processing is repeated in the remaining processors.

According to the fifth embodiment, the parallel processing apparatus (parallel computer) of the first embodiment includes the means of the first embodiment, and each processor can describe its state in a corresponding field. The token is continuously transferred on the ring bus via each processor, and a predetermined master processor checks this token and logically disconnects the failed processor from the device (system).

That is, in addition to the means of the first embodiment, the parallel processing device according to the fifth embodiment records the state of each processor in the presence or absence of a failure, It has a master processor with a mechanism for monitoring the token and disconnecting the failed processor. Therefore, the master processor can easily detect a failure of another processor by using the advantage of the ring bus data transfer.

Embodiment 6 FIG. Sixth Embodiment A parallel processing device according to a sixth embodiment of the present invention will be described with reference to FIGS. For the drawings, FIGS. 4 and 5 similar to those shown in the above-described fourth and fifth embodiments are used.

As described in the fifth embodiment, FIG.
The master processor knows the state of each processor by using the token shown in (1). Thereafter, if the failed processor is, for example, the processor P1, it is disconnected.

Here, a processor P in which a fault has occurred
It is assumed that there are four tasks A, B, C, and D to be executed in order at 1, and they must be completed by time T. It is also assumed that the master processor monitoring all processors knows in advance all the tasks executed by all processors.

As in the second embodiment, the processor P
After a failure has occurred at 1, the master processor P0 detects this. Thereafter, in the master processor P0, tasks A ', B', C ', and D' whose execution times are shorter than those of the original tasks A, B, C, and D are prepared in advance, and these are prepared by the master processor P0. Execute sequentially in P0.

For example, the tasks A ′, B ′, C ′, and D ′ have the same processing contents as the tasks A, B, C, and D, but the execution time is reduced by lowering the processing accuracy. Are shortened. With this,
If task A was re-executed, the time T
The processing that cannot be made in time can be made in time by the processing of the same function.

According to the sixth embodiment, the parallel processing apparatus (parallel computer) according to the fifth embodiment includes the means according to the fifth embodiment, and has the same function as each task executed by each processor. However, by preparing each task having a short execution time in a predetermined master processor due to low processing accuracy or the like, if a failure occurs in any processor, the master Upon detection, the failed processor is logically disconnected from the device, and the execution of the task scheduled to be executed by the processor is performed by the master processor, which has reduced accuracy and the like but has a shorter processing time of the same function. Thus, when a failure occurs in an arbitrary processor, the processing can be continued continuously, and the processing can be completed within a predetermined time.

That is, in the parallel processing apparatus according to the sixth embodiment, in addition to the means of the first embodiment, a high-speed execution version in which the processing accuracy is reduced and the execution time is reduced for all tasks is prepared. It has a mechanism. Therefore, using the advantage of the ring bus data transfer,
The master processor can easily detect failures of other processors, and perform processing performed within a certain period of time, even if the processor fails, although there is a slight decrease in processing accuracy, but functionally Is possible.

Embodiment 7 A parallel processing device according to Embodiment 7 of the present invention will be described with reference to FIG. For the figure, FIG. 5 similar to that shown in the above-described fifth embodiment is used.

In the fifth embodiment, one master processor is assumed for the entire parallel processing apparatus. In the seventh embodiment, two master processors are prepared. Fifth Embodiment
If one of the master processors becomes unusable due to a failure when making the determination of the token shown in the above, the other master processor detects this and one of the master processors Inspect the token.

According to the seventh embodiment, in the parallel processing apparatus (parallel computer) of the sixth embodiment, two master processors are prepared, and if one of the master processors fails, The other master processor can make that change.

That is, the parallel processing apparatus according to the seventh embodiment includes a processor which is a substitute for the master processor in addition to the means of the fifth embodiment. Therefore, the master processor can easily detect a failure of another processor by using the advantage of the data transfer of the ring bus, and can continue processing even if a failure occurs in the master processor.

[0070]

As described above, in the parallel processing apparatus according to the present invention, a plurality of processors and the first node connected to each processor are sequentially connected on the ring by a one-to-one unidirectional bus connection. A first ring bus and a second node connected to each processor are connected to the first ring bus in a direction opposite to the above order.
A parallel processing device comprising a second ring bus coupled on a ring by a one-to-one unidirectional bus connection, wherein a part of the plurality of processors is connected to an input / output bus; Since the processor performs input / output with the outside, it is possible to cope with not only the failure of the ring bus but also the failure of the processor and the failure of the input / output processor.

Further, in the parallel processing device according to the present invention, as described above, the input / output processor includes first and second input / output processors, and the first input / output processor includes When the status information from the second input / output processor does not arrive, it is determined that a failure has occurred in the second input / output processor, and the input / output processing performed by the second input / output processor is substituted. So do
In addition to the failure of the ring bus, it is possible to deal with the failure of the processor and the failure of the input / output processor.

Further, as described above, in the parallel processing device according to the present invention, any one of the plurality of processors has a state monitoring mechanism of an adjacent processor on the ring, and the adjacent processor has a state monitoring mechanism. The information of the task to be executed is stored, and when a failure occurs in the adjacent processor, the arbitrary processor logically disconnects the adjacent processor and re-executes the task scheduled to be executed by the adjacent processor. Since the execution is performed, it is possible to detect failures in a distributed manner between adjacent processors, and it is possible to efficiently detect a failure suitable for a ring bus connecting processors between adjacent processors.

Further, in the parallel processing device according to the present invention, as described above, any one of the plurality of processors has a state monitoring mechanism of an adjacent processor on the ring, and the adjacent processor has a state monitoring mechanism. Information of a high-priority task among tasks to be executed is stored in advance, and the arbitrary processor executes the high-priority task at the same time as the adjacent processor, and a failure occurs in the adjacent processor. In this case, the adjacent processors are logically separated from each other, so that there is an effect that the processing performed within a predetermined time can be directly executed even if the processor fails.

Further, as described above, in the parallel processing apparatus according to the present invention, any one of the plurality of processors has a state monitoring mechanism of an adjacent processor on a ring, and the adjacent processor has a state monitoring mechanism. Information of a task having a function equivalent to the task to be executed and having a shorter execution time than the task is stored in advance, and the arbitrary processor logically disconnects the adjacent processor when a failure occurs in the adjacent processor. The task that is scheduled to be executed by the adjacent processor is separated and replaced by the task with a short execution time, so that the processing performed within a predetermined time is slightly reduced even if the processor fails. Although the accuracy is reduced, there is an effect that the function is executable.

Further, as described above, in the parallel processing apparatus according to the present invention, the plurality of processors flow tokens indicating their states on the ring bus, and the predetermined master processor among the plurality of processors is provided. Since the token is examined to logically separate the failed processor, the master processor can easily detect the failure of another processor by using the advantage of the data transfer of the ring bus.

As described above, in the parallel processing device according to the present invention, the master processor has information equivalent to a task executed by the plurality of processors and has a function equivalent to a task executed by the plurality of processors and has a shorter execution time than the task. When the processor fails, the master processor takes over the task scheduled to be executed by the failed processor with the task having a shorter execution time, so that the data transfer of the ring bus is performed. With the advantage of the above, the master processor can easily detect the failure of another processor, and even if the processor fails, the processing performed within a predetermined time is slightly reduced in processing accuracy. This has the effect of being functionally executable.

Further, the parallel processing device according to the present invention
As described above, the defined master processor of the plurality of processors includes the first and second master processors, and the first master processor is configured to execute when the second master processor fails. Since the second master processor is substituted, the master processor can easily detect the failure of another processor by using the advantage of the data transfer of the ring bus, and can continue even if the failure occurs in the master processor. This has the effect of enabling processing.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a parallel processing device according to Embodiment 1 of the present invention.

FIG. 2 is a diagram illustrating a part of a configuration of a parallel processing device according to a second embodiment of the present invention;

FIG. 3 is a diagram showing a task list of a parallel processing device according to Embodiment 3 of the present invention.

FIG. 4 is a diagram showing a task flow of a parallel processing device according to Embodiment 4 of the present invention.

FIG. 5 is a diagram showing tokens of a parallel processing device according to Embodiment 5 of the present invention.

FIG. 6 is a diagram showing a configuration of a conventional parallel processing device.

[Explanation of symbols]

1 node (communication node), 2 processors, 2A input / output processor, 3 data transfer lines (communication bus),
4 I / O bus.

Claims (8)

[Claims] A first ring bus in which a plurality of processors, a first node connected to each processor are sequentially connected on a ring by a one-to-one unidirectional bus connection, and a first ring bus connected to each processor. A second ring bus in which two nodes are connected on the ring by a one-to-one unidirectional bus connection in a direction opposite to the order, wherein a part of the plurality of processors Connected to an input / output bus, and the input / output processor performs input / output with an external device. 2. The input / output processor includes first and second input / output processors, wherein the first input / output processor is configured to receive the status information from the second input / output processor. , The second
2. The parallel processing device according to claim 1, wherein it is determined that a failure has occurred in the input / output processor and the input / output processing performed by the second input / output processor is performed instead. 3. An arbitrary processor among the plurality of processors has a state monitoring mechanism of an adjacent processor on a ring, and stores information on a task executed by the adjacent processor. 2. The method according to claim 1, wherein, when a failure occurs in the adjacent processor, the adjacent processor is logically separated and the task scheduled to be executed by the adjacent processor is executed again.
The parallel processing device as described in the above. 4. An arbitrary processor among the plurality of processors has a state monitoring mechanism of an adjacent processor on the ring, and transmits information on a task having a higher priority among tasks executed by the adjacent processor. It is stored in advance, and the arbitrary processor executes the high-priority task at the same time as the adjacent processor, and logically disconnects the adjacent processor when a failure occurs in the adjacent processor. The parallel processing device according to claim 1, wherein: 5. An arbitrary processor among the plurality of processors has a state monitoring mechanism of an adjacent processor on the ring, has a function equivalent to a task executed by the adjacent processor, and has a function equivalent to that of the task. The information of a task having a short execution time is stored in advance, and the arbitrary processor is to logically disconnect the adjacent processor and execute the adjacent processor when a failure occurs in the adjacent processor. 2. The parallel processing apparatus according to claim 1, wherein the task is substituted by the task having a short execution time. 6. The plurality of processors flow tokens indicating their states on a ring bus, and a predetermined master processor among the plurality of processors examines the tokens and logically determines a failed processor. The parallel processing device according to claim 1, wherein the parallel processing device is separated. 7. The master processor has a function equivalent to a task executed by the plurality of processors and previously stores information of a task having a shorter execution time than the task, and the master processor has a fault in the processor. 7. The parallel processing device according to claim 6, wherein, when the error occurs, the task scheduled to be executed by the failed processor is substituted by the task with a short execution time. 8. A predetermined master processor among the plurality of processors includes a first and a second master processor, wherein the first master processor is configured to operate when a failure occurs in the second master processor. 8. The parallel processing device according to claim 6, wherein said second master processor is substituted.