JPS60110001A - Method and device for data control of multiplex controller - Google Patents

Abstract

PURPOSE:To improve both responsiveness and reliability of a multiplex controller by executing the arithmetic processing of the next unit step based on the middle result of operation selected every arithmetic processing of each prescribed step. CONSTITUTION:Processors CPU-A-C transfer the middle result of operation of each step of a series of data processing procedures to an arithmetic middle result collator 304 via data transfer buses 301-303 respectively. A collator 304 selects a middle result of operation which is possibly correct and sends it back to each of CPU-A-C. The collation is carried out every step on the basis on the data which is considered correct although the deviation between a feedback signal and the signal of the processor CPU produced by an open loop is increased by an integration processing. In this way, the stable working of a multiplex controller is ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data processing method and apparatus for a multiplex control device applied to a control device of a plant or the like that requires high reliability and high availability.

[Background of the invention]

Generally, in control systems that require a high degree of reliability,
By multiplexing the processing devices and comparing their outputs, it is possible to detect whether or not there is an abnormality in the processing device, and to always output a control signal for a normal processing device. In the case of a double system, a process of logical producting of digital information, a process of selecting a high value or a low value of analog information, etc. are applied as the output matching method, and in the case of a triple system, a majority vote process of digital information is applied, Processing that takes an intermediate value or average value of analog information is applied.

FIG. 1 shows an example of the configuration of a triplex control device.

As shown in the figure, input information 1 from the plant process
01 denotes each processing unit CPU-A of the triplexed multiprocessing unit 103 via the distribution circuit 102.

It is distributed to CPU-B and CPU-C. The output signals of each processing device CPU-A-C are collated by an output collation circuit 104, and any one output signal selected thereby is outputted to the process as a control signal 105.

On the contrary, considering the feedback control loop in the above configuration, a closed loop is formed for the processing device (for example, CPU-A) that outputs the output signal Vm selected as the control signal 105. but,
The other processing units CPU-B and CPU-C are in an open loop. Therefore, if the control processing of the processing units CPU-A-C includes an integral element, the processing units CPU-B and CPU-CK in the open loop have their own output signal and the corresponding one. The absolute value of the control deviation from the input information from the process is not reduced,
As shown in FIG. 2, the output signals Via and Vc are increased and diverged, so that multiplexing becomes meaningless. In addition, in such a state, as shown in FIG. 3, if the output signal to be selected at tL is switched to the output signal of the CPU-C due to the occurrence of an abnormality in the CPU-C, for example,
The control amount will change drastically. As described above, the conventional method has the disadvantage that stable and reliable feedback control is not guaranteed. That is, for example, suppose that the matching method is a process that takes an intermediate value, and at a certain point in time, CPU-A takes the intermediate value and CPU-A takes the intermediate value.
If B outputs a high-value output signal and CPU-C outputs a low-value output signal, for CPU-B and C, there will be a time deviation between the feedback signal from the plant and their own output signal. And those deviations are.

Since each output signal is integrated and becomes an output signal with a gradually larger control amount, it is always the output signal of the CPU-A that is selected by the output comparison circuit 104. If CPU-A outputs an abnormal output signal in such a case, the selected output signal is switched to that of CPU-B or CPU-C, resulting in the above-mentioned drawback.

As a solution to these drawbacks, for example, conventionally,
As shown in FIG. It is known that the system was designed to perform analysis, diagnosis, etc. However, according to this, the processing load increases due to information transmission processing and collation processing between CPU-A and CPU-C, and the control response speed decreases significantly. The disadvantage is that the processing software becomes much larger than the original control processing.

Another known method is to provide minor feed bank circuits 107a to 107C for each processing unit CPU-A"-C as shown in FIG. -11558 publication.

JP-A-57-36304). That is, each processing device C
The output signal representing the process including the integral element in PU-A-C is inverted to form a minor feedback signal, and the deviation between the control signal 105 and the feedback signal 108 is added to the input information. However, although this method eliminates the above-mentioned drawbacks, it requires as many feedback circuits as the number of outputs of each processing unit CPU-A-C and the number of control signals 105 of the output comparison circuit 104. [Object of the Invention] The object of the present invention is to provide multiplexed control that has excellent control responsiveness and can guarantee stable and reliable feedback control. [Summary of the Invention] The present invention provides a data processing method for a device, and a data processing device. One intermediate calculation result is selected from among the intermediate results by a predetermined collation selection procedure, and each processing device executes the calculation process f of the next unit step based on the selected intermediate calculation result. Furthermore, by forming the device using hardware, the present invention attempts to achieve its own objectives.

[Embodiments of the invention]

The present invention will be explained below based on an example device.

FIG. 5 and FIG. 6 are block diagrams of a triplex control device according to an embodiment of the present invention.

In the drawings, parts with the same reference numerals as those in the example shown in FIG. 1 have the same functions and configurations.

As shown in FIG. 5, each of the processing units CPU-A to CPU-C is connected to a computation intermediate result collation device 304 via data transfer buses 301 to 303, respectively, and performs a predetermined series of data processing procedures. The intermediate calculation results for each unit step are transferred to the calculation intermediate result comparison device 304 as if they were transferred to the work area of the memory within the own processing device. Intermediate calculation result comparison device 30
4 has the block configuration shown in Fig. 6, and each CPU
- Check the intermediate results of A-C and find that it is correct 1
In other words, the intermediate results transferred from each CPU-A to C are sent to the input storage section via the input/output control circuit 401. 402, and then stored in the matching circuit 40.
3, a well-known method (for example, 2 out of 3) is used to compare and select, and one normal intermediate result of the operation is stored in the output storage section 404. Note that the human output control circuit 401 performs write address designation of the input storage section 402 and read address control of the output storage section 404, etc., and each CPU-A to C is connected to the input/output control circuit 40.
1, the intermediate calculation results stored in the output storage unit 404 are accessed and taken in. Here, specific data examples will be further explained. If the CPU
- The intermediate results of the calculations of A and C are each “111”.

“111” @110”, the input storage unit 402 stores “111” in the area corresponding to each CPU.
”, “111”, and “110”. If we take 20ut □f 3 of these three data, it becomes 111',
The output storage section includes a CPU-A.

Regardless of whether B or C accesses, "111°" is stored so as to be read. In this way, the consistency of the multiplexed CPU processing data is maintained.

Therefore, according to this embodiment, even if the deviation between the signal of the processing unit CPU which becomes an open loop and the feedback signal is increased by the integral processing, the data is compared for each unit step, and one data that is considered to be correct is used in the next step. Since each processing device C will perform control processing based on
The divergence of the control amount of the PU is suppressed, and even if the processing unit CPU is switched due to different reasons, etc., stable control can be performed without sudden changes in the control amount, and the reliability of control can be improved. Further, even if errors are included in the arithmetic processing of the control system including the processing unit CPU, there is an effect that the accumulation of errors accompanying the above-mentioned integral processing can be suppressed.

In addition, in the embodiment shown in FIGS. 5 and 6,
If a means for detecting an abnormality in each processing device CPU-A to CPU-C and switching between them is provided, as shown in FIG. 7, a processing device abnormality signal 5 generated from each processing device
A verification mode switching control circuit 502 that receives 01 as an input is provided, which causes the input/output control circuit 401 to prevent input/output of data to and from the abnormality processing device CPU, and accordingly causes the verification circuit 403 to select verification mode. Output a command to change the method. For example, if an abnormality occurs in the processing device CPU-C, the 2 out of 3 processing in the triple system described above is switched to the logic f8i result processing in the dual system.

In addition, FIG. 8 and FIG.
An example will be shown in which a function is provided to deal with an abnormality that occurred in 2004. As shown in FIG. 8, an input storage abnormality detection circuit 601 and an output storage abnormality detection circuit 602, each consisting of a well-known parity check or the like, are provided at one output end of the input storage section 402 and the output storage section 404, respectively. These abnormality detection signals are output to error status logic 605.

The error status logic 605 also includes a verification circuit abnormality detection signal 603 output from an abnormality detection circuit (not shown) provided in the verification circuit 403 and a timing signal (not shown) provided in the computation intermediate result verification device 304. A circuit abnormality detection signal 604 is input. When any abnormality detection signal is input, the error status logic 605 sends an input/output prevention signal 60 to the input/output control circuit 401.
6, and also sends an abnormality detection signal 607 of the mid-computation result comparison device to each processing device cPU-A-C. Each processing unit CPU-A- that received this
C is a crowd buffer control circuit 7 as shown in FIG.
By controlling the crowd cover 702 of 04, the arithmetic circuit 7
01 and the data transfer buses 301 to 303, and the arithmetic circuit 701 is switched to access the intermediate result of the arithmetic operation stored in the local memory 703. As a result, an abnormality in the computation intermediate result collation device 304, which is a common part of each processing unit CPU-A-C, can be detected.
It is possible to prevent this from spreading to the point where the entire control device goes down.

By the way, in the embodiment illustrated in FIG. 3, the multiplexed processing units CPU-A-C generally operate asynchronously, but when operating the multiplexed control unit asynchronously (especially when the calculation results ), the output timing of the control signal will be matched to the system that is the most delayed. Unfortunately, it will not be possible to apply this process unless you have enough time to do so. Therefore, in order to improve the responsiveness to changes in the process even slightly, it is desirable to synchronize the processing bags f&cPU=A to C.

FIG. 10 shows an embodiment in which the computation intermediate result comparison device 304 is provided with a computation synchronization control function for a plurality of processing units CPU-A-C. As shown in the figure, a timing generation circuit 801 that generates a synchronization signal is provided, and this synchronization signal 80
2 is outputted to each processing unit CPU-A to C1, the manual storage section 40, the output storage section 404, and the collation circuit 403 to synchronize them. With such a configuration, the arithmetic processing and input/output processing of the processing units CPU-A-C are synchronized, and data input/output and verification processing, etc. in the computation intermediate result verification device 304 are synchronized. With this i'+, it is possible to increase the processing speed of the multiplex control device.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to guarantee stable and highly reliable feedback control with excellent control responsiveness, and the device can be formed with simple hardware, resulting in significantly reduced software. It has the effect of being able to be used as a light liquid.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a multiplexing control device to which the present invention can be applied, FIGS. 2 and 3 are diagrams for explaining the operation of the example shown in FIG. 1, and FIG. 4 (A) , (B) is a block diagram of a conventional example, FIG. 5 is an overall block diagram of an embodiment of the present invention, FIG. 6 is a diagram of a main part of the embodiment shown in FIG. 5, and FIGS. The figures are block diagrams of other embodiments of the present invention. 304... Intermediate calculation result matching device, 401... Input/output control circuit, 402... Input storage section, 403... Verification circuit, 404... Output storage section. Agent Patent attorney Tatsuyuki Unuma 1st mouth lθ3 $ 2 solid / θ5 hay 3 polished′θs t. Chi 6- eyes lρ8 $, f Figure 1θ3 Chi 7 Month 3θ4 0υt 3θj

Claims (1)

[Scope of Claims] 1. A plurality of processing devices that take in input information given from a process, perform the same control processing in parallel, and output each, and a signal output from each processing device according to a predetermined selection procedure. A data processing method for a multiplexing control device, comprising: a collation circuit that selects a signal based on the control signal and outputs it as one control signal; Multiplexing characterized in that the intermediate calculation results of the devices are collated according to a predetermined selection procedure and one is selected, and each processing device executes the control processing of the next step based on the selected intermediate calculation result. Control device data processing method. 2. A plurality of processing devices that take in input information given from a process, perform the same control processing in parallel, and output each, and select signals output from each processing device based on a predetermined selection procedure. a collation circuit that outputs one control signal as a data processing unit of a multiplexing control device, and stores intermediate calculation results for each predetermined unit step of a series of control processing in each of the processing devices. an input storage section; an operation intermediate result matching circuit that reads intermediate operation results in the input storage section, collates them according to a predetermined selection procedure, and selects one; and an external output storage section that can be accessed simultaneously from each processing device, and each of the processing devices transfers the intermediate calculation results for each unit step to the input storage section, and 1. A data processing device for a multiplex control device, characterized in that the data processing device is configured to read an intermediate calculation result stored in an output storage section and execute a next step control process. 3. In the invention as set forth in claim 2, the computation intermediate result collation device includes means for blocking the import of the computation intermediate results transferred from the processing device based on the input processing device abnormality detection signal. A data processing device for a multiplexing processing device, characterized in that it has means for switching the selection procedure of the intermediate result comparison circuit. 4. Permissible In the invention as set forth in claim 2 or 3, the computation intermediate result collation device detects an abnormality in itself and prevents the processing device from accessing the output storage section, and also detects the abnormality. It has means for sending a signal to each of the processing devices, and each processing device that receives the abnormality detection signal is configured to execute the next step control processing based on the intermediate calculation result of the processing device. A data processing device for a multiplex control device, characterized by: