JPH0547511A - Chip varistor - Google Patents

Abstract

PURPOSE:To provide a chip varistor with which the concentration of electric field at the corner part of an internal electrode can be prevented, and also surge resistivity can be improved. CONSTITUTION:A semiconductor ceramic layer 2 and an internal electrodes 3 are laminated alternately in such a manner that the ceramic layer 2 is pinched by the internal electrodes 3, they are integrally sintered, an external electrode 5, on which one edge face 3b only of the internal electrodes 3 is brought into contact with both edge faces 4a and 4b of the sintered body 4, is formed and a chip varistor 1 is constituted. The side of the other edge face 3b of the internal electrodes 3 is formed into a circular arc, and the overlapping part A of the internal electrodes 3 is formed into an oval shape.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip varistor functioning as a voltage non-linear resistor, and more particularly to a structure capable of improving surge withstand capability by avoiding concentration of an electric field on internal electrodes.

[0002]

2. Description of the Related Art Generally, a varistor is a resistor element whose resistance value changes non-linearly according to an applied voltage, and is used as, for example, a surge absorbing element for preventing an overvoltage from being applied to an electronic circuit. Further, in recent years, as electronic parts are made into chips, there is an increasing demand for ultra-miniaturization and low voltage in the above varistor in order to improve the mounting density. In order to meet such a demand, a laminated chip varistor as shown in FIGS. 4 and 5 has been conventionally proposed (for example, see Japanese Patent Publication No. 58-23921). This chip varistor 20 has semiconductor ceramic layers 21 and internal electrodes 22 alternately laminated and integrally sintered, and has left and right end faces 23a and 23b of the sintered body 23 only one end face 22a of the internal electrode 22. Are formed by alternately forming external electrodes 24. In such a chip varistor 20, about 10 to 20 layers of the internal electrodes 22 are laminated in order to obtain a surge resistance of 50 to 100 A, for example.

[0003]

In the above chip varistor 20, as shown in FIG.
The varistor characteristics are obtained at the overlapping portion A. However, in the above-mentioned conventional chip varistor 20, since the shape of the internal electrode 22 is rectangular, the electric field is likely to concentrate at the corner portion a of the internal electrode 22. Therefore, the corner portion a has a high voltage and a thick current. A path is formed. As a result, with the progress of the varistor effect in which the current sharply increases with a slight increase in voltage, the current is further concentrated in the corner portion a. As a result, the surge withstand current, which is the maximum impulse current that can be processed by the varistor, is reduced.
0A is the limit.

The present invention has been made in view of the above conventional circumstances, and an object of the present invention is to provide a chip varistor capable of avoiding the concentration of an electric field on an internal electrode and improving surge withstand capability.

[0005]

Therefore, according to the present invention, semiconductor ceramic layers and internal electrodes are alternately laminated so that the internal electrodes overlap with each other with the ceramic layers sandwiched therebetween and integrally sintered,
A chip varistor in which external electrodes to which only one end surface of the internal electrode is connected are formed on both end surfaces of the sintered body,
It is characterized in that the overlapping portions of the internal electrodes are curved.

[0006]

According to the chip varistor of the present invention, since the overlapping portion of the internal electrodes is formed into a curved shape such as a circle or an ellipse, when a surge current is applied, the current concentrates on the corners of the internal electrodes. Without it, it will be dispersed over almost the entire surface, and the surge resistance can be improved accordingly.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are views for explaining a chip varistor according to an embodiment of the present invention. In the figure, reference numeral 1 is a multilayer chip varistor of this embodiment. This varistor 1
Is a rectangular parallelepiped, and the semiconductor ceramic layers 2 containing ZnO as a main component and the internal electrodes 3 made of an Ag-Pd alloy are alternately laminated, and the dummy ceramic layers 6 are stacked on the upper and lower surfaces thereof. It is configured by integrally sintering and thereby forming a sintered body 4. In addition, the above-mentioned sintered body 4
The left and right end surfaces 4a and 4b of the above are coated with external electrodes 5 made of Ag-Pd alloy.

One end face 3a of each internal electrode 3 is alternately exposed to the left and right end faces 4a and 4b of the sintered body 4, and the one end face 3a is electrically connected to the external electrode 5. Has been done. Further, the peripheral end faces other than the one end face 3a of the internal electrode 3 are located inside the ceramic layer 2,
As a result, it is embedded in the sintered body 4.

The other end surface 3b side of each internal electrode 3 is formed in an arc shape, so that the overlapping portion A of each internal electrode 3 sandwiching the ceramics layer 2 has an elliptical shape.

Next, a method of manufacturing the chip varistor 1 of this embodiment will be described. First, ZnO (97.8 mol%) was the main component, and Bi ₂ O ₃ (0.5 mol%) and MnO (0.5 m
ol%), Co ₂ O ₃ (0.5mol%), Sb ₂ O ₃ (0.7mol%)
Are mixed to form a ceramic material. This ceramic material is formed into a ceramic green sheet having a predetermined thickness by the doctor blade method, and the green sheet is punched into a rectangular shape to form a large number of semiconductor ceramic layers 2 and dummy ceramic layers 6.

Next, on the upper surface of each ceramic layer 2,
The internal electrode 3 is formed by screen-printing an electrode paste made of an Ag-Pd alloy. In this case, only one end face 3 of the internal electrode 3 is formed to extend to the edge of the ceramic layer 2, the other peripheral end faces are located inside, and the other end face 3b side of the internal electrode 3 is formed in an arc shape. ..

Then, as shown in FIG. 3, the ceramic layers 2 and the internal electrodes 3 are alternately overlapped, and one end face 3a of each internal electrode 3 is alternately exposed to the left and right edges of the ceramic layer 2. It is laminated, and the dummy ceramics layer 6 is further laminated on the upper and lower surfaces thereof, and this is pressed by a press,
Crimping is performed to form a laminated body. As a result, the overlapping portion A of the other end surface 3b of each internal electrode 3 with the ceramics layer 2 sandwiched therebetween has an elliptical shape, and only one end surface 3a is exposed on the left and right end surfaces of the laminated body.

Next, the above laminated body is heated and baked at a high temperature to obtain a sintered body 4. Next, the left and right end faces 4 of this sintered body 4
An electrode paste made of an Ag-Pd alloy is applied to a and 4b and then baked to form the external electrode 5. As a result, the chip varistor 1 of this embodiment is manufactured.

As described above, according to this embodiment, the other end surface 3b of each internal electrode 3 is formed in an arc shape, and the overlapping portion A sandwiching the ceramic layer 2 on the other end surface 3b side is formed in an elliptical shape. The concentration of current when a surge current is applied can be relaxed, and the surge resistance can be improved accordingly.

[0015]

[Table 1]

Table 1 shows the results of tests conducted to confirm the effects of this embodiment. In this test, a chip varistor was created by the manufacturing method described in this example, and the varistor voltage V _1mA , nonlinear coefficient α, electrostatic capacitance pF, and surge withstand amount A were measured. The surge resistance was measured by applying a shock wave of 8/20 μsec twice at 5 minute intervals and measuring the limiting current value at which the varistor voltage did not change by ± 10% or more. For comparison, a similar test was conducted on a conventional chip varistor having a rectangular internal electrode. As is clear from the table, in the case of the conventional sample, V _1mA was 30.8V, the nonlinear coefficient was 40, and the electrostatic capacitance was 219pF, which were satisfactory values for each of these characteristics, but surge resistance Then 100A
The current is concentrated at the corners. On the other hand, in the case of the sample of this example, V _1mA is 31.0V, the nonlinear coefficient is 41, the electrostatic capacity is 224pF, and the surge withstand is 150A, which is 1.5 times higher than that of the conventional sample. I understand.

[0017]

As described above, according to the chip varistor of the present invention, since the overlapping portion of the internal electrodes 3 is formed into a circle or an ellipse, the concentration of current when a surge current is applied can be alleviated, and that much. It has the effect of improving surge resistance.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a chip varistor according to an embodiment of the present invention.

FIG. 2 is a perspective view of the chip varistor of the above embodiment.

FIG. 3 is an exploded perspective view showing a method of manufacturing the chip varistor of the above embodiment.

FIG. 4 is a sectional plan view showing a conventional chip varistor.

FIG. 5 is an exploded perspective view of a conventional chip varistor.

[Explanation of symbols]

 1 Chip Varistor 2 Semiconductor Ceramic Layer 3 Internal Electrode 3a One End Surface of Internal Electrode 4 Sintered Body 5 External Electrode A Overlapping Part of Internal Electrode

Claims (1)

[Claims] 1. A semiconductor ceramic layer and an internal electrode,
In a chip varistor in which the internal electrodes are alternately laminated so as to overlap with each other with a ceramics layer sandwiched therebetween and integrally sintered, and external electrodes to which only one end face of the internal electrode is connected are formed on both end faces of the sintered body. A chip varistor in which the overlapping portion of the internal electrodes is curved.