JPH09129416A - Laminated ceramic device - Google Patents
Laminated ceramic deviceInfo
- Publication number
- JPH09129416A JPH09129416A JP28123095A JP28123095A JPH09129416A JP H09129416 A JPH09129416 A JP H09129416A JP 28123095 A JP28123095 A JP 28123095A JP 28123095 A JP28123095 A JP 28123095A JP H09129416 A JPH09129416 A JP H09129416A
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- JP
- Japan
- Prior art keywords
- internal electrode
- electrode pattern
- inner electrode
- ceramic
- laminated
- Prior art date
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は積層セラミックス素
子に属し、特に、大電流が表面上に流れる性質をもつ積
層セラミックス素子に属する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated ceramic element, and more particularly to a laminated ceramic element having a property that a large current flows on its surface.
【0002】[0002]
【従来の技術】従来の積層セラミックス素子は、図6に
示すように、長方形を呈する有効内部電極1を含む内部
電極パターン4と、この内部電極パターン4の外側に設
けたセラミックスグレーンシート3とを有している。2. Description of the Related Art As shown in FIG. 6, a conventional laminated ceramic element includes an internal electrode pattern 4 including a rectangular effective internal electrode 1 and a ceramic grain sheet 3 provided outside the internal electrode pattern 4. Have
【0003】有効内部電極1には角部分が存在してい
る。そして、この種の積層セラミックス素子には、急峻
なサージが入ったとき大電流は表面上に流れる性質をも
っており、全電極面がオン状態になる前に電極部分の角
部分に一時的に流れ込む。The effective internal electrode 1 has a corner portion. In a multilayer ceramic element of this type, when a steep surge is applied, a large current flows on the surface, and temporarily flows into a corner portion of the electrode portion before all the electrode surfaces are turned on.
【0004】また、従来の積層セラミックス素子は、図
7に示すように、理論上の内部電極パターン7から、角
取りによる湾曲された素体端部と内部電極パターン4端
部の最短距離t1を考慮している。Further, in the conventional laminated ceramics element, as shown in FIG. 7, the shortest distance t1 between the theoretical end portion of the body and the end portion of the inner electrode pattern 4 which is curved by chamfering is calculated from the theoretical inner electrode pattern 7. I am considering.
【0005】さらに、積層セラミックス素子は、角取り
による素体の形状において、図8に示すように酸化亜鉛
6素体に角部分が残っており外部電極5の膜厚t4が薄
くなっている。この外部電極5の膜厚t4の薄い部分
(t4<t5の関係)がある。Furthermore, in the laminated ceramics element, in the shape of the element body obtained by chamfering, as shown in FIG. 8, the corner portion remains in the zinc oxide 6 element body, and the film thickness t4 of the external electrode 5 is thin. There is a portion where the thickness t4 of the external electrode 5 is small (the relationship of t4 <t5).
【0006】従来技術としては、特開平2−5501号
公報に酸化亜鉛を主成分としたシート間に内部電極を設
けて積層した積層型チップバリスタが開示されている。As a prior art, Japanese Patent Laid-Open Publication No. Hei 2-5501 discloses a multilayer chip varistor in which internal electrodes are provided and laminated between sheets mainly composed of zinc oxide.
【0007】[0007]
【発明が解決しようとする課題】しかしながら、図6に
示した積層セラミックス素子は、全電極面がオン状態に
なる前に電極部分の角部分に一時的に流れ込んでしまう
局部的な電流集中及びコロナ放電破壊を引き起こすとい
う問題がある。However, in the laminated ceramics element shown in FIG. 6, the local current concentration and the corona which temporarily flow into the corners of the electrode portion before all the electrode surfaces are turned on. There is a problem of causing discharge breakdown.
【0008】また、図7に示した積層セラミックス素子
は、長方形の内部電極パターン4の形成位置を素体の内
側へシフトするために有効内部電極面積を減少させると
いう問題がある。Further, the laminated ceramics element shown in FIG. 7 has a problem that the effective internal electrode area is reduced because the formation position of the rectangular internal electrode pattern 4 is shifted to the inside of the element body.
【0009】さらに、図8に示した積層セラミックス素
子は、酸化亜鉛素体6に角部分が残っていると外部電極
5の膜厚t4が薄くなり、この外部電極5の膜厚t4の
薄い部分は半田付け性が弱くなるという問題がある。Further, in the laminated ceramics element shown in FIG. 8, if the corner portion remains in the zinc oxide element body 6, the film thickness t4 of the external electrode 5 becomes thin, and the film thickness t4 of the external electrode 5 becomes thin. Has a problem that solderability becomes weak.
【0010】それ故に本発明の課題は、局部的電流集中
及びコロナ放電破壊を防止でき、また、有効内部電極面
積を増大させることができるとともに精度の上がった均
一で厚い外部電極の膜厚を得ることで半田付け性を向上
させることができる積層セラミックス素子を提供するこ
とにある。Therefore, an object of the present invention is to prevent local current concentration and corona discharge destruction, to increase the effective internal electrode area, and to obtain a uniform and thick external electrode film with improved accuracy. Accordingly, it is an object of the present invention to provide a multilayer ceramic element capable of improving solderability.
【0011】[0011]
【課題を解決するための手段】本発明によれば、有効内
部電極を含む内部電極パターンと、この内部電極パター
ンの外側に設けたセラミックスグレーンシートとを有し
ている積層セラミックス素子の内部電極形成において、
前記有効内部電極を素体形状の湾曲に合わせたた形状に
したことを特徴とする積層セラミックス素子が得られ
る。According to the present invention, an internal electrode formation of a laminated ceramic element having an internal electrode pattern including an effective internal electrode and a ceramic grain sheet provided outside the internal electrode pattern. At
A laminated ceramics element is obtained in which the effective internal electrode has a shape that matches the curvature of the body shape.
【0012】また、本発明によれば、有効内部電極を含
む内部電極パターンと、この内部電極パターンの外側に
設けたセラミックスグレーンシートとを有している積層
セラミックス素子の内部電極形成において、前記セラミ
ックスグリーンシート上に形成される前記内部電極パタ
ーンを素体形状の湾曲に合わせた電極パターンに形成し
たことを特徴とする積層セラミックス素子が得られる。Further, according to the present invention, in forming an internal electrode of a laminated ceramic element having an internal electrode pattern including an effective internal electrode, and a ceramic grain sheet provided outside the internal electrode pattern, the ceramic is formed. A laminated ceramics element is obtained in which the internal electrode pattern formed on the green sheet is formed into an electrode pattern conforming to the curvature of the body shape.
【0013】また、本発明によれば、前記内部電極パタ
ーンが長方形であってかつ角部が湾曲していることを特
徴とする積層セラミックス素子が得られる。Further, according to the present invention, there is provided a multilayer ceramic element wherein the internal electrode pattern is rectangular and the corners are curved.
【0014】[0014]
【発明の実施の形態】積層セラミックス素子の代表的な
製造方法は、まず主成分の酸化物に数種類の副成分を添
加した粉末を、混合し、仮焼した後、再粉砕を施して混
合粉末とする。次に、この混合粉末に数種類の有機溶媒
を加え、スラリー状にして成膜する。この膜に内部電極
を印刷した後、打ち抜き、これを一枚毎に左右反転させ
ながら適当枚数重ねて積層構造とした後、熱プレスをし
て圧着させる。更に、これを規定の大きさに切断し、脱
脂、焼結して焼結体を得て角取りを行う。これに外部電
極を塗布、焼付けをして積層セラミックス素子を得る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A typical method of manufacturing a multilayer ceramic element is as follows. First, a powder obtained by adding several kinds of subcomponents to an oxide as a main component is mixed, calcined, and then reground to obtain a mixed powder. And Next, several kinds of organic solvents are added to the mixed powder to form a slurry and form a film. After printing an internal electrode on this film, punching it out, stacking an appropriate number of these while reversing left and right one by one to form a laminated structure, and then pressing by hot pressing. Further, this is cut into a predetermined size, degreased and sintered to obtain a sintered body and to perform corner cutting. An external electrode is applied and baked to obtain a multilayer ceramic element.
【0015】本発明では、このような製造工程中、内部
電極を形成する工程において、セラミックスグリーンシ
ート上に形成される電極パターンを素体形状の湾曲に合
わせた電極パターン形成するものである。In the present invention, an electrode pattern formed on the ceramic green sheet is formed in accordance with the curvature of the elementary body in the step of forming the internal electrode during such a manufacturing process.
【0016】以下、本発明の積層セラミックス素子の第
1の実施の形態例について図を参照して説明する。本実
施の形態例は、積層セラミックチップバリスタとした場
合の例を示している。The first embodiment of the laminated ceramic element of the present invention will be described below with reference to the drawings. The present embodiment shows an example in which a multilayer ceramic chip varistor is used.
【0017】図1を参照して、積層セラミックス素子
は、長方形を呈する有効内部電極1を含む内部電極パタ
ーン2と、この内部電極パターン2の外側に設けたセラ
ミックスグレーンシート3とを有している。Referring to FIG. 1, the laminated ceramic element has an internal electrode pattern 2 including an effective internal electrode 1 having a rectangular shape, and a ceramic grain sheet 3 provided outside the internal electrode pattern 2. .
【0018】この積層セラミックス素子は、セラミック
スグリーンシート3上に形成される内部電極パターン2
を素体形状の湾曲に合わせた電極パターン2に形成され
ている。The laminated ceramic element is formed by an internal electrode pattern 2 formed on a ceramic green sheet 3.
Are formed in the electrode pattern 2 which is adapted to the curvature of the element shape.
【0019】積層セラミックス素子を形成するには、素
体形状の湾曲に合わせた内部電極パターン2をセラミッ
クスグリーンシート3に印刷する。そして、このセラミ
ックスグリーンシート3及び内部電極パターン2の無い
セラミックスグリーンシート3を所要枚数積層し、全体
を加熱プレスし、脱脂、焼結、角取り、外部電極塗布等
の必要な工程を経ると、図4に示すような積層セラミッ
クチップバリスタが得られる。In order to form a multilayer ceramic element, an internal electrode pattern 2 conforming to the curvature of the element body is printed on a ceramic green sheet 3. Then, when a required number of the ceramic green sheets 3 and the ceramic green sheets 3 without the internal electrode patterns 2 are laminated, and the whole is subjected to necessary steps such as hot pressing, degreasing, sintering, chamfering, and external electrode coating, A multilayer ceramic chip varistor as shown in FIG. 4 is obtained.
【0020】なお、この積層セラミックチップバリスタ
は、図7に示した従来の内部電極パターン4と比較して
有効内部電極1に角部分がないため、急峻なサージが入
ったとき、全電極面がオン状態になり、電極の一部分に
流れ込んでしまう局部的電流集中及びコロナ放電破壊を
防止することから、従来の内部電極パターン4では電流
波形8/20μsの場合にサージ耐量にサージ耐量が6
0A〜100Aであるのに対してサージ耐量は100A
以上を有する。In this multilayer ceramic chip varistor, since the effective internal electrode 1 has no corners as compared with the conventional internal electrode pattern 4 shown in FIG. 7, all electrode surfaces are exposed when a sharp surge occurs. In order to prevent the local current concentration and the corona discharge breakdown that are turned on and flow into a part of the electrode, the conventional internal electrode pattern 4 has a surge withstand capability of 6 or 6 when the current waveform is 8/20 μs.
0A to 100A, but surge withstand 100A
It has the above.
【0021】また、第1の実施の形態例の内部電極形成
において、図2に示すように、従来の内部電極パターン
4の端部とセラミックスグリーンシート3の端部までの
距離t2の350μmを基準に、内部電極パターン2の
端部とセラミックスグリーンシート3の端部までの距離
t1′及びt3′とは全て350μmとして素体形状の
湾曲に合わせた内部電極パターン2を形成する。図5に
この時の有効内部電極1の寸法を示しており、有効内部
電極1の面積S′=2.4mm2 となり、図9に示した
従来の有効内部電極S=2.2mm2 と比較して面積比
が1.1倍となるため、サージ耐量が1.1倍となる。
従来のサージ耐量が10Aの積層チップバリスタの場合
は11Aとなり、従来に比較して約10%のサージ耐量
向上となる。In the formation of the internal electrodes according to the first embodiment, as shown in FIG. 2, the distance t2 between the end of the conventional internal electrode pattern 4 and the end of the ceramic green sheet 3 is 350 μm. Then, the distances t1 'and t3' between the end of the internal electrode pattern 2 and the end of the ceramic green sheet 3 are all 350 μm to form the internal electrode pattern 2 conforming to the curvature of the elementary body. FIG. 5 shows the size of the effective internal electrode 1 at this time, and the area S ′ of the effective internal electrode 1 is 2.4 mm 2 , which is compared with the conventional effective internal electrode S = 2.2 mm 2 shown in FIG. Since the area ratio is 1.1 times, the surge withstand capability is 1.1 times.
In the case of a conventional multilayer chip varistor having a surge withstand capability of 10 A, the surge immunity is 11 A, which is approximately 10% higher than the conventional surge varistor.
【0022】さらに、第1の実施の形態例の内部電極形
成において、有効内部電極の面積が従来と同じになるよ
うに内部電極パターン2を形成し、角取りを遠心バレル
にて従来30分の処理を50分処理することで、図3に
示すように酸化亜鉛6素体に極端な凸部分がないため、
外部電極5の膜厚精度が上がり、図8に示した従来の外
部電極5の膜厚t4,t5=10μm〜40μmと比較
して、均一で厚い外部電極5の膜厚t4′,t5′=3
0μm〜40μmが得られるため、半田付けのときに従
来、外部電極膜厚10μm〜20μm部分で発生してい
た電極喰われを防止できる。Further, in the formation of the internal electrodes of the first embodiment, the internal electrode pattern 2 is formed so that the area of the effective internal electrodes is the same as that of the prior art, and the corners are cut with a centrifugal barrel for 30 minutes. By performing the treatment for 50 minutes, the zinc oxide hexagonal body has no extremely convex portions as shown in FIG.
The film thickness accuracy of the external electrode 5 is improved, and the film thickness t4 ', t5' of the external electrode 5 is uniform and thicker than the film thickness t4, t5 = 10 μm to 40 μm of the conventional external electrode 5 shown in FIG. Three
Since 0 μm to 40 μm can be obtained, it is possible to prevent electrode erosion which has conventionally occurred at the external electrode film thickness of 10 μm to 20 μm during soldering.
【0023】[0023]
【発明の効果】本発明は以上説明したように、セラミッ
クスグリーンシート上に形成される内部電極パターンを
素体形状の湾曲に合わせた内部電極パターン形成するこ
とにより、有効内部電極に角部分がなくなり、局部的電
流集中及びコロナ放電破壊を防止することが可能とな
る。As described above, according to the present invention, the internal electrode pattern formed on the ceramic green sheet is formed in accordance with the curvature of the element body, so that the effective internal electrode has no corner portion. It is possible to prevent local current concentration and corona discharge breakdown.
【0024】また、従来、内部電極パターン形成してい
ない部分にも内部電極パターンを形成し、有効内部電極
面積を増大させることが可能となるため、一例として、
有効内部電極の場合、有効内部電極面積は従来パターン
と比較して1.1倍となるため、サージ耐量が向上す
る。Further, since it is possible to increase the effective internal electrode area by forming an internal electrode pattern in a portion where no internal electrode pattern is conventionally formed, for example,
In the case of the effective internal electrode, the effective internal electrode area is 1.1 times as large as that of the conventional pattern, so that the surge withstand capability is improved.
【0025】また、従来より内部電極パターン形成位置
を考慮し、かつ有効内部電極面積比を減らさずに素体の
角取りを充分処理することが可能となり、極端な凸部分
がないため、従来より外部電極膜厚の精度が上がり、均
一で厚い外部電極膜厚を得ることが可能となるため、積
層セラミックス素子の半田付け性を向上させるという効
果がある。In addition, since it is possible to sufficiently treat the corners of the element body without taking the internal electrode pattern formation position into consideration and without reducing the effective internal electrode area ratio, there is no extremely convex portion. Since the accuracy of the external electrode film thickness is improved and a uniform and thick external electrode film thickness can be obtained, there is an effect that the solderability of the multilayer ceramic element is improved.
【0026】さらに、前記の実施例は積層セラミックチ
ップバリスタのみについて記述しているが、これ以外に
同様の構造をもつ積層セラミックス部品であれば同様の
効果があることは明らかである。Although the above embodiment describes only the multilayer ceramic chip varistor, it is apparent that other multilayer ceramic parts having the same structure have similar effects.
【図1】本発明の一実施の形態例におけてセラミックス
グリーンシート上に内部電極形成した状態を示す平面図
である。FIG. 1 is a plan view showing a state in which internal electrodes are formed on a ceramic green sheet according to an embodiment of the present invention.
【図2】図1において、従来の内部電極パターンの端部
と素体端部までの最短距離t2を基準に内部電極パター
ンの端部と素体端部までの距離は全てt2として素体形
状の湾曲に合わせた内部電極形成した状態を示す平面図
である。In FIG. 1, the distance between the end of the internal electrode pattern and the end of the body is defined as t2 based on the shortest distance t2 between the end of the conventional internal electrode pattern and the end of the body. FIG. 4 is a plan view showing a state in which internal electrodes are formed in accordance with the curvature of FIG.
【図3】本発明の一実施の形態例の積層セラミックチッ
プバリスタを示す横断面図である。FIG. 3 is a cross-sectional view showing a multilayer ceramic chip varistor according to one embodiment of the present invention.
【図4】積層セラミックチップバリスタの斜視断面図で
ある。FIG. 4 is a perspective sectional view of a multilayer ceramic chip varistor.
【図5】本発明の一実施例の有効内部電極寸法を示す説
明図である。FIG. 5 is an explanatory diagram showing effective internal electrode dimensions according to an embodiment of the present invention.
【図6】従来のセラミックスグリーンシート上に内部電
極を形成した状態を示す横平面図である。FIG. 6 is a horizontal plan view showing a state in which internal electrodes are formed on a conventional ceramics green sheet.
【図7】従来のセラミックスグリーンシート上に内部電
極を形成した状態及び理論上の形成位置を示す平面図で
ある。FIG. 7 is a plan view showing a state in which internal electrodes are formed on a conventional ceramic green sheet and a theoretical formation position.
【図8】従来の積層セラミックチップバリスタの横断面
図である。FIG. 8 is a cross-sectional view of a conventional monolithic ceramic chip varistor.
【図9】従来の有効内部電極寸法を示す説明図である。FIG. 9 is an explanatory diagram showing conventional effective internal electrode dimensions.
【符号の説明】 1 有効内部電極 2、4 内部電極パターン 3 セラミックスグリーンシート 5 外部電極 6 酸化亜鉛素体 7 理論上のパターン[Explanation of symbols] 1 Effective internal electrode 2, 4 Internal electrode pattern 3 Ceramic green sheet 5 External electrode 6 Zinc oxide element 7 Theoretical pattern
Claims (3)
と、この内部電極パターンの外側に設けたセラミックス
グレーンシートとを有している積層セラミックス素子の
内部電極形成において、前記有効内部電極を素体形状の
湾曲に合わせたた形状にしたことを特徴とする積層セラ
ミックス素子。1. In forming an internal electrode of a laminated ceramic element having an internal electrode pattern including an effective internal electrode and a ceramic grain sheet provided outside the internal electrode pattern, the effective internal electrode is formed into a body shape. A laminated ceramics element characterized by being shaped to match the curvature of the.
と、この内部電極パターンの外側に設けたセラミックス
グレーンシートとを有している積層セラミックス素子の
内部電極形成において、前記セラミックスグリーンシー
ト上に形成される前記内部電極を素体形状の湾曲に合わ
せた内部電極パターンに形成したことを特徴とする積層
セラミックス素子。2. In forming an internal electrode of a laminated ceramic element having an internal electrode pattern including an effective internal electrode and a ceramic grain sheet provided outside the internal electrode pattern, the internal electrode pattern is formed on the ceramic green sheet. A laminated ceramics element, wherein the internal electrode is formed into an internal electrode pattern that matches the curvature of the element shape.
おいて、前記内部電極パターンが長方形であってかつ角
部が湾曲していることを特徴とする積層セラミックス素
子。3. The multilayer ceramic element according to claim 2, wherein the internal electrode pattern is rectangular and the corners are curved.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7281230A JP2770850B2 (en) | 1995-10-30 | 1995-10-30 | Multilayer ceramic element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7281230A JP2770850B2 (en) | 1995-10-30 | 1995-10-30 | Multilayer ceramic element |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09129416A true JPH09129416A (en) | 1997-05-16 |
JP2770850B2 JP2770850B2 (en) | 1998-07-02 |
Family
ID=17636184
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7281230A Expired - Lifetime JP2770850B2 (en) | 1995-10-30 | 1995-10-30 | Multilayer ceramic element |
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JP (1) | JP2770850B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6704997B1 (en) | 1998-11-30 | 2004-03-16 | Murata Manufacturing Co., Ltd. | Method of producing organic thermistor devices |
CN115938700A (en) * | 2022-12-26 | 2023-04-07 | 深圳顺络电子股份有限公司 | Laminated piezoresistor and electronic equipment |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61146904U (en) * | 1985-03-04 | 1986-09-10 | ||
JPH0547511A (en) * | 1991-08-20 | 1993-02-26 | Murata Mfg Co Ltd | Chip varistor |
-
1995
- 1995-10-30 JP JP7281230A patent/JP2770850B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61146904U (en) * | 1985-03-04 | 1986-09-10 | ||
JPH0547511A (en) * | 1991-08-20 | 1993-02-26 | Murata Mfg Co Ltd | Chip varistor |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6704997B1 (en) | 1998-11-30 | 2004-03-16 | Murata Manufacturing Co., Ltd. | Method of producing organic thermistor devices |
CN115938700A (en) * | 2022-12-26 | 2023-04-07 | 深圳顺络电子股份有限公司 | Laminated piezoresistor and electronic equipment |
Also Published As
Publication number | Publication date |
---|---|
JP2770850B2 (en) | 1998-07-02 |
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