JPH0546540A - Conflict arbitration system with inhibition time - Google Patents

Abstract

PURPOSE:To surely process the periodical processing request of the highest priority in a conflict arbitration system with inhibition time by setting the request inhibition time bands before and after the processing request of the highest priority and inhibiting the reception of other processing requests in those set time bands. CONSTITUTION:The processing execution mode signal generating circuits 1 are provided in number equal to the processing requests to be accepted. At the same time, an inhibition time bend 21 is set by an inhibition time generating circuit 2 based on the processing request of the highest priority. Thus other circuits 1 are prevented to accept the processing requests in the band 21. Then a circuit 1 accepts the periodical processing request of the highest priority and transmits a processing execution mode signal. The circuit 2 sets the bands 21 before and after a prescribed time point based on the time when the periodical processing request is received. Thus other circuits 1 are inhibited from accepting other processing requests.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a competitive arbitration system with prohibition time for processing a processing request having the highest priority.

[0002]

2. Description of the Related Art Conventionally, when a plurality of processing requests occur simultaneously, a circuit for controlling a plurality of processing requests determines a priority order for each request and performs processing, or sequentially changes the priority order. It was supposed to be processed.

[0003]

Therefore, for example, as shown in FIG.
When the processing shown in (b) of FIG. 3 is performed under the circuit configuration of (a), the processing request signal R which is periodically generated.
Q A is an irregular processing request signal RQ If it occurs before the processing of B is completed, the processing request signal RQ of the highest priority is given. There is a problem that the processing of A (processing request A2 here) cannot be performed. The circuit and operation of FIG. 3 will be described below.

In FIG. 3A, the processing request signal RQ
A, RQ B is a signal requesting processing, and processing execution
Medium signal A CYC, B CYC is the processing request signal RQ
A, RQ It is a signal that the process of B is being executed, and the reset signal
Issue-RST A CYC, -RST B CYC is a reset
Signal to be set.

According to the circuit of FIG. 3B, the processing request signal RQ A or processing request signal RQ The next process is not accepted until the process of the one requested to be processed faster is started and the process ends.

In FIG. 3B, the processing request signal RQ
A is a processing request of the highest priority, which is a processing that occurs periodically and requires a processing time tA. Processing request signal RQ B is a process that occurs irregularly and requires a processing time tB.

Now, at the timing shown in the figure, the highest priority is given to the regular
Processing request signal RQ A is called A1, A2, A3 ...
Generated irregularly, and the irregular processing request signal RQ B is B1
Occurs. The first regular A1 occurred is shown in Fig. 3.
(A) Processing request signal RQ Accepted as A and processing time
It takes tA to process, and the second irregular occurrence
B1 is the processing request signal RQ shown in FIG. Received as B
In addition, the processing is performed for a processing time tB. But this
Second RQ By the time the processing of B is completed, the best
Previous A2 has occurred, and this highest priority A2 can be processed
There is a problem that there is no.

According to the present invention, the request prohibition time tNB is set before and after the processing request to be processed with the highest priority, and other processing requests are not accepted in this time zone, so that the periodical highest-priority processing request is surely performed. It is intended to be processed.

[0009]

[Means for Solving the Problems] Means for solving the problems will be described with reference to FIG. In FIG. 1, a processing execution signal generating circuit 1 receives a processing request and sends a processing execution signal.

The prohibition time generation circuit 2 generates a prohibition time 21 on the basis of a periodical processing request having the highest priority, and prohibits another processing execution signal generation circuit 1 from accepting the processing request. ..

[0011]

As shown in FIG. 1, the present invention responds to the fact that the processing-in-progress signal generating circuit 1 receives the highest-priority periodic processing request and sends out the processing-in-progress signal. 2 generates a prohibition time 21 from a predetermined time before to a predetermined time after the time when this periodic processing request is made, and notifies the other processing execution signal generating circuit 1 of the prohibition time 21 to notify the other processing execution signal. The generation circuit 1 prohibits the reception of other processing requests during the prohibition time 21.

Therefore, the prohibition time tNB is set before and after the processing request to be processed with the highest priority, and other processing requests are not accepted in this time zone, so that the periodical processing request with the highest priority is not waited. Therefore, it is possible to surely perform the processing with the highest priority.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of an embodiment of the present invention will be described in detail with reference to FIGS.

In FIG. 1, a signal generation circuit 1 during processing is being executed.
Is provided in response to a processing request, receives a processing request signal exclusively, and is processing-in-progress signal (for example, A CYC) generating circuit. When receiving the signal of the prohibition time 21 from the prohibition time generation circuit 2, the processing-in-progress signal generation circuit 1 prohibits the reception of the processing request signal.

The prohibition time generating circuit 2 generates a prohibition time 21 so as to surely receive the highest priority periodic processing request, and prohibits another processing execution signal generating circuit 1 from accepting the processing request. It is a thing. This prohibition time 21
Is based on the time when a regular processing request is received, and another processing request (for example, RQ B) a processing request (for example, RQ) that preferentially performs the processing from the time tB before the time required by B) to perform the processing. A) is the time until the elapse of the time tA required for processing.

The processing request signal is a signal requesting processing. Here, RQ A is the highest priority periodic processing request, and RQ B is an irregular processing request. The processing in-progress signal is a signal in which the processing request is accepted and the processing is being executed. A CYC is the processing request signal RQ A, B CY
C is the processing request signal RQ It corresponds to B.

The reset signal is a signal for receiving the processing request, starting the processing, and resetting the processing-in-progress signal when the processing is completed. Next, the operation of the configuration shown in FIG. 1A will be described with reference to FIG. Here, the processing request signal RQ A is the highest priority periodic processing request signal, and the processing request signal RQ B is an aperiodic processing request signal. In addition, the processing request signal RQ Processing request signal RQ for A The prohibition time 21 for B is tNB in the figure.

(1) Processing request signal RQ The processing execution signal generating circuit (A) 1 of FIG. 1 receives the first A1 of A (highest priority periodic signal), and the processing execution signal A
CYC is output, and a processing unit (not shown) starts processing. After a lapse of a predetermined number of clocks (for example, 3 clocks), the reset signal is input to the in-process signal generation circuit (A) 1 and the in-process signal A Reset CYC. This allows
Processing request signal RQ The process of the first A1 of A is completed.

(2) Subsequently, the processing request signal RQ Since the B (aperiodic signal) has passed the prohibition time tNB here, the processing-in-progress signal generation circuit (B) 1 in FIG. CYC is output, and a processing unit (not shown) starts processing. After a lapse of a predetermined number of clocks (for example, 3 clocks), the reset signal is input to the in-process signal generation circuit (B) 1 and the in-process signal B is input. Reset CYC. As a result, the processing request signal RQ The process of the first B1 of B is ended.

(3) When starting the processing of (2), the processing request signal RQ If B is within the prohibition signal tNB, that is, the highest priority periodic processing request RQ T before A
B (Processing request signal RQ The processing request RQ from within the time of (B) is the time required to execute the processing. TA after A
(Processing request signal RQ A is within the time required to execute the processing), the processing request signal RQ The processing start of B is prohibited, and execution is started after the prohibition time 21 has elapsed.

As described above, the prohibition time 21 is set as the highest priority periodic processing request signal (RQ in this case). The time tA is set after the time tB before (A), and another processing request (here, RQ) is performed within the prohibited time 21. By prohibiting the reception of B), it becomes possible to reliably receive the processing request with the highest priority and perform the processing.

FIG. 2 is a diagram showing the configuration and operation of the first embodiment of the present invention. Where RQ A is a regular processing request signal having the highest priority. RQ B is an aperiodic processing request signal.

A CYC is RQ This is the signal under processing of A. B CYC is RQ This is a signal indicating that the B process is being executed.
-RST A CYC is A This is a CYC reset signal.

-RST B CYC is B This is a CYC reset signal. Forbidden time signal is RQ Another processing request signal for the time period input by A, here RQ This is a signal for prohibiting acceptance of B.

The programmable counter 22 is a programmable counter which generates a prohibiting time between signals. The prohibition time signal is a regular RQ with the highest priority. Based on the time when A is input, RQ that is another processing request before this base point
From the time tB required for processing B, the RQ after this base point It is a time period until the time tA required for processing A.

The D-FF (1) takes in RQ-A in synchronization with the clock and outputs A of "1". CYC is output and the reset signal notified at the end of processing-RST A Reset with CYC and A The CYC is set to "0".

The D-FF (2) takes in RQ-B in synchronization with the clock and outputs B of "1". CYC is output and the reset signal notified at the end of processing-RST B Reset with CYC and B The CYC is set to "0".

Next, the operation of the circuit shown in FIG. 2A will be described with reference to the time chart shown in FIG. Is the highest priority periodic processing request signal RQ A is input (generated).

Is a processing request signal RQ A typed
In response to this, the D-FF (1) in (a) of Fig. 2 is
This is taken in and the "1" processing in progress signal A Output CYC
Then, a processing unit (not shown) starts processing.

Since the processing from a processing unit (not shown) ends at the next clock, a reset signal -RST for resetting A CYC is input to the D-FF (1) of FIG. 2A via the inverter.

Is a reset signal -RST A C
In response to the input of YC, the processing execution signal A at the next clock Set CYC to “0” and RQ A series of processing for A is completed.

Is an asynchronous processing request signal RQ B was input at the same time as, but it was kept waiting because it was the prohibition time, and the processing request signal RQ At the time when the process of A is completed, the D-FF (2) of FIG. Set CYC to "1".

Since the processing from a processing unit (not shown) ends at the next clock, the reset signal -RST for resetting B CYC is input to the D-FF (2) of FIG. 2A through the inverter.

Is a reset signal -RST B C
In response to the input of YC, the processing execution signal B at the next clock Set CYC to “0” and RQ A series of processes for B is completed.

Similarly, hereafter, ",", ",",
The next processing request is accepted and processed in the order of ',', '. Here, the highest priority periodic processing request (here, RQ) is given to the programmable counter 22 of FIG.
Requests other than A) (RQ here) By setting the time tB necessary for B) to perform the processing, it is possible to generate the prohibited time 21 corresponding to an arbitrary processing request, and reliably receive the highest priority periodic processing request and perform the processing. Becomes

[0036]

As described above, according to the present invention,
Since the prohibition time tNB is set before and after the processing request to be processed with the highest priority and other processing requests are not accepted in this time zone, the periodical processing request with the highest priority can be performed without waiting. , Can be surely processed with the highest priority.
As a result, (1) in the conventional method, it is not possible to perform a control such that a processing request is generated periodically and the processing is given the highest priority. However, the present invention enables the control. became.

(2) Further, the programmable counter 2
By using 2, it is possible to easily deal with processing requests that require various processing times.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating the configuration and operation of one embodiment of the present invention.

FIG. 3 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

1: Processing execution signal generation circuit 2: Inhibition time generation circuit 21: Inhibition time 22: Programmable counter tNB: Inhibition time tA: Processing request RQ Time required to execute A tB: Processing request RQ Time required to execute B

Claims (1)

[Claims] 1. In a competitive arbitration method with a prohibition time for processing a processing request with the highest priority, a processing-in-progress signal generating circuit (1) that receives a processing request and outputs a processing-in-progress signal is provided for each processing request that is received. With the provision, the prohibition time (21) is generated based on the highest priority processing request,
And a prohibition time generation circuit (2) for prohibiting another processing-in-progress signal generation circuit (1) from accepting the processing request, and the above-mentioned processing-in-progress signal generation circuit (1) receives the highest priority periodic processing request. Is received and sends a processing-in-progress signal, and the prohibition time generation circuit (2) generates a prohibition time (21) from a predetermined time before to a predetermined time after the time when this periodic processing request is made. A competitive arbitration system with prohibited time, characterized in that another processing-in-progress signal generation circuit (1) is configured to prohibit acceptance of another processing request.