JPS6229819B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interrupt control device that performs interrupt processing for multiple interrupt causes when another interrupt signal is generated during one interrupt processing, and particularly relates to an interrupt control device that performs interrupt processing for multiple interrupt causes. The present invention relates to an interrupt control device that applies a single interrupt request signal to a processing device for an interrupt cause.

As the number of interrupt causes increases, other interrupt causes may occur while one interrupt process is being executed.
In such a case, conventionally, the interrupt signal that occurs later is waited for, and after the previous interrupt processing is completed, processing for the cause of the later interrupt is performed. However, when the number of interrupt causes increases, the interrupt levels are multiplexed so that while interrupt processing for a certain interrupt cause is being executed, an interrupt cause with a higher priority than that interrupt cause occurs. In this case, interrupt the previous interrupt processing, execute the interrupt processing for the later interrupt cause, return to the previous interrupt processing after the interrupt processing is completed, and interrupt the interrupt processing that is currently being executed. When an interrupt cause with a lower priority than the cause occurs, it is preferable to allow interrupt processing for a later interrupt cause to be executed after the current interrupt processing is completed.

However, if a different interrupt request signal is assigned to each of a plurality of interrupt causes and the plurality of interrupt causes are controlled independently, waiting and enabling of the interrupt causes can be controlled relatively easily. However, as the number of interrupt request signals increases, the configuration of the interrupt processing circuit becomes complicated, which is not preferable. On the other hand, if a single interrupt request signal circuit handles a plurality of interrupt causes, the interrupt processing circuit can be simplified. However, if a single interrupt request signal is used to deal with a plurality of interrupt causes, it is difficult to multiplex and prioritize interrupts as described above.

An object of the present invention is to provide a device having one interrupt request signal generation circuit that is commonly used for multiple interrupt causes, even when multiple interrupt causes occur. An object of the present invention is to provide an interrupt control device that enables interrupt processing.

The present invention includes an interrupt input storage circuit that is provided corresponding to each of a plurality of interrupt causes having different priorities, is set by an interrupt signal from the interrupt cause, and is reset after the interrupt processing is completed. , a mask memory circuit provided corresponding to the interrupt input memory circuit, which is set at the start of interrupt processing and reset after the end of interrupt processing, a single interrupt request signal generation circuit, and each interrupt input memory. The interrupt input storage circuit and the corresponding mask storage circuit provided corresponding to the circuit are in the set and reset states, respectively, and all of the interrupt input storage circuits corresponding to the interrupt cause with the higher priority are reset. and a gate circuit that generates an output during a period in which the interrupt request signal generating circuit generates an interrupt request signal for a predetermined period from the time when the output is generated in response to the output from the gate circuit. After an interrupt request signal is generated for an arbitrary interrupt cause, the output of the gate circuit is stopped by setting a mask memory circuit corresponding to the interrupt cause, and thereby the output of the gate circuit is stopped. This system is characterized in that it allows acceptance of successively generated interrupts with a higher priority, and prohibits acceptance of interrupts with a lower priority.

Embodiments of an interrupt control device according to the present invention will be described in detail with reference to the drawings. In Figure 1, MSK
0, MSK1, MSK2, and MSK3 take the instructions SMSK0, SMSK1, SMSK2, and SMSK3, respectively, generated by the data processing central processing unit (hereinafter referred to as CPU) as their set inputs, and the instructions RMSK0, RMSK
1, RMSK2, and RMSK3 are reset type flip-flops (hereinafter referred to as F/Fs) which serve as mask F/Fs for each interrupt, as will be described later. IH0, IH1, IH
2. IH3 has the corresponding interrupt cause INT0,
INT1, INT2, INT3 are the set inputs,
This is an interrupt input F/F that uses instructions RIH0, RIH1, RIH2, and RIH3 as reset inputs. AND gate 1 is a 2-input AND gate whose inputs are the output of interrupt input F/F IH0 and the output of corresponding mask F/F MSK0, and AND gate 2 is the output of upper interrupt input F/F IH0, corresponding Q output of mask F/F MSK1, own interrupt input F/
F 3-input AND gate that takes Q output of IH1 as input, AND gate 3 is upper interrupt input F/F
Each output of IH0, IH1, and the corresponding mask F/F MSK2, and the Q of its own interrupt input F/F IH2
4-input AND gate with output as input, AND gate 4 is upper interrupt input F/F IH0, IH1,
IH2, each output of the corresponding mask F/F MSK3, and its own interrupt input IH3's Q output is input 5
It is an input AND gate, and OR gate 5 is a 4-input OR gate whose inputs are the outputs of AND gates 1, 2, 3, and 4, and a delay type F/F (hereinafter referred to as D-F/F/F).
F) 6 has the output of the OR gate 5 as its input. Inverter 7 inputs the output of DF/F 6 and inputs its inverted output to AND gate 8 . The other input of AND gate 8 is the output of OR gate 5. D-F/F6, inverter 7,
The AND gate 8 is an interrupt request signal generating circuit 9 that constitutes a pulse differentiating circuit that generates a single pulse serving as an interrupt request signal (REQ).

Interrupt request signal REQ from output terminal 10 of circuit 9
When this occurs, the CPU interrupts the program being executed, saves the program and various data at the time of the interrupt, and moves to the interrupt processing program corresponding to the cause of the interrupt. Assuming that no processing is being executed for any interrupt cause, interrupt input F/F IH0, IH1, IH
Both IH2 and IH3 are in the reset state (output is "1"). Depending on the processing status of the program, even if an interrupt cause occurs, the interrupt may not be accepted. Whether or not this acceptance is allowed is determined by the CPU mask F/F MSK0, MSK
This can be done by controlling 1, MSK2, and MSK3. It is now assumed that these mask F/Fs are in an interrupt acceptance state and are all in a reset state (output is "1").

In this state, interrupt cause INT2 with the third priority occurs, and while the interrupt processing program for interrupt cause INT2 is being executed, the second interrupt cause INT1, which has a higher priority than interrupt cause INT2, occurs. The progress of the program in this case is shown in FIG. 2, and the time chart is shown in FIG. 3 for explanation. The CPU is executing program A, and the address
When the interrupt cause INT2 occurs at the time _t1 when An is reached, this signal sets the interrupt input F/F IH2 (Q=“1”,=“0”). Since the upper interrupt input F/Fs IH0 and IH1 and the corresponding mask F/F MSK2 have all been reset, the Q output of the interrupt input F/F IH2 is divided via AND gate 3 and OR gate 5. D-F/F6 is input to the output terminal 10.
An interrupt request signal REQ corresponding to the delay time determined by is generated at time _t2 . With this signal
The CPU interrupts the program A being executed at the end of the address An, detects that the AND gate 3 has a logical value of 1, and moves to the interrupt processing program B for the corresponding interrupt cause INT2. At the beginning of this interrupt processing program, there is an instruction SMSK2 to set mask F/FMSK2.
is in the set state (
Output=“0”). In other words, when the interrupt processing state for interrupt cause INT2 is reached, the interrupt mask F/F MSK2 corresponding to this interrupt cause is set to prevent the interrupt cause INT2 from being accepted, and after this interrupt processing is finished, It is determined again whether or not to accept the interrupt cause INT2. In this state, among the inputs of AND gate 3, mask F/F MSK2
The output becomes logical value “0”, and the interrupt input F/F
The Q output of IH2 is prohibited from being input to the interrupt signal generation circuit 9 by the AND gate 3.

Here, if the mask F/F MSK2 were not present, the interrupt input F/F IH2 would be in the set state during the interrupt processing period, so the output of the AND gate 3 would always remain "1" and the upper interrupt Even if an interrupt signal is generated from an interrupt cause, the pulse differentiating circuit 9 cannot generate an interrupt request signal. On the other hand, with the start of interrupt processing for interrupt cause INT2,
When the interrupt input F/F IH2 is reset, the output of the AND gate 3 is stopped, and it becomes possible to accept higher-order interrupts, but at the same time, it also becomes possible to accept the lower-order interrupt cause INT3, making it impossible to perform priority interrupt processing. Therefore, by providing the mask F/F MSK2 and setting it, the output of the AND gate 3 is stopped, allowing interrupts with a higher priority, and interrupts with a lower priority. It is possible to prohibit the acceptance of interrupts, which enables multiple priority interrupt control. The same applies to other mask F/Fs. Such a mask F/F is particularly effective in the interrupt control device of the present invention which generates a single interrupt request signal for a plurality of interrupt causes.

At a point in time during the interrupt processing period for interrupt cause INT2
When an interrupt occurs due to the upper interrupt cause INT1 at _t3 , the interrupt input F/F IH1 is set. At this time, the interrupt input F/F IH0 is in the reset state and the mask F/F MSK1 is also in the reset state, so the Q output of the interrupt input F/F IH1 generates an interrupt signal via AND gate 2 and OR gate 5. The interrupt request signal REQ is input to the circuit 9 and is generated at time _t4 . As mentioned above, when the interrupt request signal REQ occurs, the running program is interrupted, so the program B for the interrupt cause INT2 is placed at address B.
The process is interrupted at the end of _p , and the CPU detects that the output of the AND gate 2 is a logical value "1" and moves to the interrupt processing program C for the interrupt cause 1. At the beginning of the interrupt processing program for this interrupt cause 1, there is a set instruction for mask F/F MSK1.
SMSK1 is placed, and the mask F/F SMSK1 is set to prohibit reception of lower-order interrupts.

At the end of program C for interrupt cause INT1, a reset instruction RIH1 for interrupt input F/F IH1 is placed, and after the program for interrupt cause INT1 ends, interrupt input F/F IH1 enters the reset state at time _t5 . . In addition, the instruction RMSK1 for the mask F/F MSK1 can also be generated after the interrupt input F/F IH1 is reset, and if the interrupt cause INT1 appears again, the interrupt processing for this interrupt cause INT1 will be accepted. You can set whether or not.
When the interrupt processing program C for the interrupt cause INT1 is finished, the interrupted interrupt processing program B for the interrupt cause INT2 returns to address B _p+1 .
The rest of this program is executed, and at the end, the interrupt input F/F HI2, which holds the interrupt cause in the same way as the interrupt processing program for the interrupt cause INT1,
An instruction for mask F/F MSK2 is provided, and interrupt cause INT2 is issued at the end of program B at _t6 .
Returns to address A _o+1 of program A before occurrence of the error.

On the other hand, Figure 4 shows the progress of the program when the interrupt cause INT3 occurs during the execution of the interrupt processing program for the interrupt cause INT2, and the time chart is shown in Figure 5.
Each is shown in the figure. Interrupt input F/F IH ₃ is set at time _t7 when INT3 occurs, but interrupt input F/F IH, which is one of the inputs of AND gate 4, is set.
Since the output of INT2 is the logical value "0", the Q output of the interrupt input F/F IH3 is not input to the interrupt signal generation circuit 9, and the execution of the interrupt processing program B for the interrupt cause INT2 continues. Ru. As mentioned above, the interrupt input F/F IH2 is reset at the time _t8 when this program B ends, so the interrupt cause INT
1. Interrupt request signal in the same way as for INT2
REQ occurs, the CPU detects that the output of AND gate 4 is a logical value "1", and the interrupt cause INT
The process moves to interrupt processing program D corresponding to No. 3. Also placed at the beginning of this program is an instruction to set the mask F/F MSK3 for the interrupt input F/F INT3, similar to the interrupt causes INT1 and INT2. After the interrupt processing program D for interrupt cause INT3 ends, the same processing as in the interrupt processing program for interrupt causes INT1 and INT2 is executed, and the address A _o+ of program A before interrupt cause INT2 occurs is executed.
Return to ₁ .

Interrupt processing for interrupt causes INT0, INT1, and INT3 is also performed in order of priority. In this example, the priorities are INT0, INT1, INT2,
It can be seen that the order is INT3.

As described above, according to the interrupt control device of the present invention using the single interrupt request method, there is a priority order for interrupt causes, and while the interrupt processing program for one interrupt cause is being executed, another interrupt When an interrupt cause occurs, whether to perform an interrupt or wait is determined according to the priority order. It will be easily understood that the effect of this invention is greater than that of a method in which what occurs later is simply waited for.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the interrupt control device according to the present invention, and Fig. 2 is a program when an interrupt cause with a higher priority occurs after an interrupt cause with a lower priority occurs. Figure 3 is a time chart of the circuit shown in Figure 1 in the state shown in Figure 2. Figure 4 is a time chart of the circuit shown in Figure 1 in the state of Figure 2. Figure 5 is a diagram showing the transition of the program when an interrupt cause occurs.
This is a time chart of the circuit shown in the figure. IH0~IH3: Interrupt cause memory element, MSK0~
MSK3: Interrupt non-acceptance storage element, 1 to 4: AND gate for priority setting, 9: Interrupt signal generation circuit.

Claims (1)

[Claims] 1. An interrupt input storage circuit that is provided corresponding to each of a plurality of interrupt causes with different priorities, that is set by an interrupt signal from the interrupt cause, and that is reset after the completion of interrupt processing; A mask memory circuit is provided corresponding to the interrupt input memory circuit, and is set at the start of interrupt processing and reset after the interrupt processing is completed, a single interrupt request signal generation circuit, and a mask memory circuit corresponding to each interrupt input memory circuit. The interrupt input storage circuit and the corresponding mask storage circuit are in the set and reset states, respectively, and all of the interrupt input storage circuits corresponding to the higher priority interrupt cause are in the reset state. a gate circuit that generates an output for a period, and the interrupt request signal generation circuit generates an interrupt request signal for a predetermined period from the time when the output is generated in response to the output from the gate circuit, and After an interrupt request signal is generated for the interrupt cause, the output of the gate circuit is stopped by setting the mask memory circuit corresponding to the interrupt cause, and thereby the interrupt request signal is generated continuously. 1. An interrupt processing control device that allows acceptance of interrupts with a higher priority and prohibits acceptance of interrupts with a lower priority.