JPH05257875A - Method for evading interruption processing start delay - Google Patents

Method for evading interruption processing start delay

Info

Publication number
JPH05257875A
JPH05257875A JP5778192A JP5778192A JPH05257875A JP H05257875 A JPH05257875 A JP H05257875A JP 5778192 A JP5778192 A JP 5778192A JP 5778192 A JP5778192 A JP 5778192A JP H05257875 A JPH05257875 A JP H05257875A
Authority
JP
Japan
Prior art keywords
interrupt
processing
interruption
interrupt processing
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5778192A
Other languages
Japanese (ja)
Inventor
Noboru Minagawa
昇 皆川
Nobuaki Seta
信明 瀬田
Koji Saito
功治 斎藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Instruments Engineering Co Ltd
Hitachi Ltd
Original Assignee
Hitachi Instruments Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Instruments Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Instruments Engineering Co Ltd
Priority to JP5778192A priority Critical patent/JPH05257875A/en
Publication of JPH05257875A publication Critical patent/JPH05257875A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)

Abstract

PURPOSE:To start interruption processing without any delay by a software system which is placed in an interruption inhibition period. CONSTITUTION:If an interruption processing request is generated at optional timing during the execution of processing 1 including the interruption inhibition period, the start of interruption processing 5 is delayed if the current processing position 2 is in the interruption inhibition period (between 3 and 4). For the purpose, temporary interruption processing is performed before main interruption processing to absorb the delay of the processing start in the interruption inhibition period by the temporary interruption processing and the real interruption processing start is set in the temporary interruption processing to eliminate the delay of the processing start.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は割込み禁止期間を含むソ
フトウェアにおいて、割込み処理の実行・制御に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to execution and control of interrupt processing in software including an interrupt prohibition period.

【0002】[0002]

【従来の技術】割込み処理には 割込みレベル(優先順
位)があり、割込み禁止もその割込みレベルに応じて割
込みの可・否を与える。
2. Description of the Related Art Interrupt processing has an interrupt level (priority), and interrupt prohibition also gives an interrupt enable / disable according to the interrupt level.

【0003】割込み処理実行要求があったとき、割込み
禁止期間中あるいは別の割込み処理中であった場合、割
込みレベルによって当該割込み処理が実行されるか遅延
されるかが決定される。割込み処理が遅延されることな
く瞬時に実行させるには、割込みレベルを高くすれば良
い。この割込みレベルによって遅延することなく割込み
処理が実行される。
When there is an interrupt processing execution request, during the interrupt disabled period or during another interrupt processing, it is determined whether the interrupt processing is executed or delayed depending on the interrupt level. In order to execute the interrupt processing instantly without delay, the interrupt level may be increased. With this interrupt level, interrupt processing is executed without delay.

【0004】[0004]

【発明が解決しようとする課題】常に遅延することなく
該当割込み処理を実行させたい場合、割込みレベルを最
も高くすれば良いが、割込み禁止の割込みレベルが当該
割込み処理の割込みレベルと同等かもしくはそれよりも
高く、その割込みレベルを変更できない場合、当該割込
み処理開始が場合によって遅延することはさけられな
い。
When it is desired to execute the corresponding interrupt processing without delay, the interrupt level may be set to the highest, but the interrupt level of interrupt inhibition is equal to or higher than the interrupt level of the interrupt processing. If the interrupt level is higher than the above, and the interrupt processing start cannot be delayed in some cases.

【0005】本発明の目的は、このようなソフトウェア
システムにおいて該当割込み処理開始遅延を回避するこ
とにある。
An object of the present invention is to avoid the delay in starting the corresponding interrupt processing in such a software system.

【0006】[0006]

【課題を解決するための手段】まず、割込み禁止期間の
長さ(時間間隔)を知る。
First, the length (time interval) of the interrupt prohibition period is known.

【0007】次に、処理開始を遅延させたくない本当の
割込み処理実行要求の発生する時刻から、その時間間隔
以前に、仮の割込み処理実行要求を行う。
Next, a tentative interrupt processing execution request is issued before the time interval from the time when the true interrupt processing execution request that does not want to delay the processing start occurs.

【0008】また、割込みレベルは「本当の割込み処理
>仮の割込み処理>その他」に設定する。
The interrupt level is set to "real interrupt process> temporary interrupt process>other".

【0009】そして、仮の割込み処理中に本当の割込み
処理実行要求があるようにすることで、割込み禁止期間
を回避する。
Then, by making a real interrupt processing execution request during the temporary interrupt processing, the interrupt prohibition period is avoided.

【0010】[0010]

【作用】本当の実行すべき割込み処理に先立って実行さ
れる仮の割込み処理は、本当の割込み処理が実行要求時
に割込み禁止期間に当たらないようにしている。
The provisional interrupt process executed prior to the actual interrupt process to be executed is such that the true interrupt process does not fall within the interrupt disable period at the time of execution request.

【0011】仮の割込み処理開始時に割込み禁止期間に
当たり、仮の割込み処理の開始が遅れても、本当の割込
み処理実行要求の発生する時刻から割込み禁止期間の長
さ(時間間隔)より前に仮の割込み処理実行要求を発生
させたため、本当の割込み処理実行要求発生時は仮の割
込み処理中であり、本当の割込み処理を瞬時に実行可能
にしている。
Even if the start of the temporary interrupt processing is delayed and the start of the temporary interrupt processing is delayed, the temporary interrupt processing is started before the time (interval) of the interrupt disable period from the time when the real interrupt processing execution request is generated. Since the interrupt processing execution request is generated, the temporary interrupt processing is in progress when the true interrupt processing execution request is generated, and the real interrupt processing can be executed instantaneously.

【0012】仮の割込み処理中は、割込みレベルによっ
て割込み禁止期間を含む他の処理の実行を禁止し、本当
の割込み処理実行要求のみを受付可能にしている。
During the temporary interrupt processing, execution of other processing including the interrupt prohibition period is prohibited depending on the interrupt level, and only a true interrupt processing execution request can be accepted.

【0013】[0013]

【実施例】以下、本発明の一実施例を図1〜図2により
説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

【0014】処理の流れ(図1)において、(a)従
来、(b)本発明の比較を示す。
In the process flow (FIG. 1), a comparison between (a) conventional and (b) the present invention is shown.

【0015】また、タイミングチャート(図2)におい
ても、(a)従来、(b)本発明の比較を示す。
The timing chart (FIG. 2) also shows a comparison between (a) conventional and (b) the present invention.

【0016】従来は、処理1中に任意のタイミングで割
込み処理5の実行要求が発生する。現在の処理位置2
が、割込み禁止期間(3−4間)であれば割込み処理開
始は待たされる。そこで、本発明では実行すべき本当の
割込み処理に先立って仮の割込み処理を実行させる。こ
のとき現在の処理位置2が、割込み禁止期間(3−4
間)であれば仮の割込み処理開始は待たされる。割込み
禁止解除になって、仮の割込み処理が開始し、本当の割
込み処理実行要求が発生したときは現在の処理位置2は
仮の割込み処理中であり、割込み禁止期間に当たらない
ため当該割込み処理は遅延することなく実行される。
Conventionally, an execution request for the interrupt processing 5 is generated at an arbitrary timing during the processing 1. Current processing position 2
However, in the interrupt prohibition period (between 3 and 4), the start of interrupt processing is delayed. Therefore, in the present invention, the temporary interrupt process is executed prior to the true interrupt process to be executed. At this time, the current processing position 2 is the interrupt prohibition period (3-4
In case of (interval), the start of provisional interrupt processing is delayed. When the interrupt is released and the temporary interrupt process starts and a true interrupt process execution request occurs, the current processing position 2 is in the temporary interrupt process and the interrupt disable period is not reached. Runs without delay.

【0017】本当の割込み処理が割込み禁止期間に当た
らないようにするためには、仮の割込み処理中でなくて
もよい。例えば、仮の割込み処理から呼ばれたタスクが
実行中に、本当の割込み処理実行要求が受付可能なよう
に割込みレベルが考慮されていて、他の割込み処理は実
行されないようにタイミングが図られていても良い。ま
た、仮の割込み処理中に他の割込み処理が実行されて
も、本当の割込み処理実行開始が遅延されないよう、割
込みレベルが考慮されていてれば良い。
In order to prevent the true interrupt processing from falling within the interrupt prohibition period, the temporary interrupt processing need not be in progress. For example, while a task called from a temporary interrupt process is being executed, the interrupt level is taken into consideration so that a true interrupt process execution request can be accepted, and timing is designed so that other interrupt processes are not executed. May be. Further, the interrupt level may be taken into consideration so that even if another interrupt process is executed during the temporary interrupt process, the real interrupt process execution start is not delayed.

【0018】[0018]

【発明の効果】OS(オペレーティング・システム)は
一般にOSの管理する資源保護のため、OS内で割込み
禁止している部分があるが、その期間は数十(μs)と
短時間であるため問題とはならない。しかし、例えば電
磁流量計のように励磁&流量信号のサンプリングを周期
的に正確に実行しなければ、サンプリングによって得ら
れたA/D変換器からのカウンター値に誤差が生じ、カ
ウンター値から求めた流量値も不正確になる。この電磁
流量計のソフトウェアにOSを採用する場合、本発明に
よって正確に励磁&流量信号のサンプリング周期を保つ
ことができる。
The OS (operating system) generally has a part in which interrupts are prohibited within the OS in order to protect the resources managed by the OS, but the problem is that the period is as short as several tens (μs). Does not mean However, unless the excitation & sampling of the flow rate signal is performed periodically accurately as in the case of an electromagnetic flow meter, an error occurs in the counter value from the A / D converter obtained by sampling, and the counter value is obtained. The flow rate value will also be inaccurate. When the OS is adopted as the software of this electromagnetic flow meter, the sampling cycle of the excitation & flow rate signal can be accurately maintained by the present invention.

【0019】また、本発明によってOSの改造といった
ことなく既成のOSを使用できるため、経済的であり、
かつソフトウェアの信頼性が向上する。
Further, according to the present invention, since an existing OS can be used without modifying the OS, it is economical,
And the reliability of the software is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】プログラムにおける処理の流れの概略図であ
る。
FIG. 1 is a schematic diagram of a process flow in a program.

【図2】プログラムにおける処理のタイミングチャート
である。
FIG. 2 is a timing chart of processing in a program.

【符号の説明】[Explanation of symbols]

1…処理、2…現在の処理位置、3…割込み禁止、4…
割込み禁止解除、5…割込み処理。
1 ... Processing, 2 ... Current processing position, 3 ... Interrupt disabled, 4 ...
Interrupt disable release, 5 ... Interrupt processing.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 斎藤 功治 茨城県勝田市市毛882番地 株式会社日立 製作所計測器事業部内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koji Saito 882, Ige, Katsuta-shi, Ibaraki Hitachi Ltd. Measuring Instruments Division

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】ある事象が発生したときに瞬時に処理を開
始しなければならない割込み処理と、割込みを禁止して
いる処理部分とで構成されるプログラムにおいて、割込
み禁止期間中に事象が発生し割込み処理実行要求があっ
たとき、割込み処理開始が遅延しないようにするため、
当該割込み処理の前に仮の割込み処理実行を設けたこと
を特徴とする、割込み処理開始遅延の回避方法。
1. A program comprising an interrupt process that must start processing instantly when an event occurs and a processing part that disables the interrupt, and the event occurs during the interrupt disable period. When there is an interrupt processing execution request, in order not to delay the interrupt processing start,
A method for avoiding an interrupt processing start delay, characterized in that provisional interrupt processing execution is provided before the interrupt processing.
JP5778192A 1992-03-16 1992-03-16 Method for evading interruption processing start delay Pending JPH05257875A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5778192A JPH05257875A (en) 1992-03-16 1992-03-16 Method for evading interruption processing start delay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5778192A JPH05257875A (en) 1992-03-16 1992-03-16 Method for evading interruption processing start delay

Publications (1)

Publication Number Publication Date
JPH05257875A true JPH05257875A (en) 1993-10-08

Family

ID=13065423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5778192A Pending JPH05257875A (en) 1992-03-16 1992-03-16 Method for evading interruption processing start delay

Country Status (1)

Country Link
JP (1) JPH05257875A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6003127A (en) * 1995-10-04 1999-12-14 Nippondenso Co., Ltd. Pipeline processing apparatus for reducing delays in the performance of processing operations

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6003127A (en) * 1995-10-04 1999-12-14 Nippondenso Co., Ltd. Pipeline processing apparatus for reducing delays in the performance of processing operations
US6308263B1 (en) 1995-10-04 2001-10-23 Nippondenso Co., Ltd. Pipeline processing apparatus for reducing delays in the performance of processing operations

Similar Documents

Publication Publication Date Title
JPH05257875A (en) Method for evading interruption processing start delay
US6397283B1 (en) Method of automatically adjusting interrupt frequency
JPH0546540A (en) Conflict arbitration system with inhibition time
JP2944543B2 (en) Interrupt control device
JP2008077184A (en) Interrupt control circuit
JPH0683652A (en) Microcomputer system
JPH0415912B2 (en)
JPH09114541A (en) Interruption generation time confirming circuit and processor
JPH05324497A (en) Real-time data processor
JPH06149592A (en) Interruption processing system for microcomputer
JPS642981B2 (en)
JPH05215758A (en) Speed detector
JPS59114644A (en) Program start controlling system
JPH0226245B2 (en)
JPH07219784A (en) Interruption control system
JP2619418B2 (en) Wait instruction control method
JPS60237168A (en) Ignition timing controller for internal-combustion engine
JPH0540621A (en) Microprocessor
JPH0693240B2 (en) Program synchronization circuit
JPH0675780A (en) Interruption controller
JPS6126478A (en) Gate controller of inverter
JPH0863364A (en) Wait time acquiring method
JPH10161887A (en) Method and device for interruption signal synchronization
JPS6354891B2 (en)
JPH11110231A (en) Interruption control system