JPH07219784A - Interruption control system - Google Patents

Abstract

PURPOSE:To prevent the loss of interval timer interruption. CONSTITUTION:In this interruption control system, an interruption control part 303 receives an interruption signal generated at specified periods from a timer circuit 301 and a general interruption signal, a processor 307 interrupt-processes from an interruption request from the interruption control part and vector data, and at the time of generating another interruption while this processing, the interruption control part holds the interruption state for one time for each interruption signal. In the interruption control system, an interruption state holding circuit 304 stores and holds the generation of an interval timer interruption signal and an NMI information circuit 305 NMI-informs the processor with a second interval timer interruption signal so as to execute an interval timer interruption processing. A vector decoder circuit 306 releases the states of the interruption state holding circuit and the NMI information circuit when the interval timer interruption processing is finished.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control system for a microprocessor system, and more particularly to an interrupt recognition system using an interval timer.

[0002]

2. Description of the Related Art In interrupt control, a processor receiving a request from an interrupt control unit returns an approval (permission) signal, receives vector data, and determines and processes the contents of the interrupt.

When another interrupt signal is generated during the processing, the interrupt control unit holds the signal only once for each line, and sends the held signal to the processor as soon as the current interrupt processing is completed, Perform processing.

FIG. 7 shows a circuit for interrupt control which is generally used. Reference numeral 101 is an interrupter control unit (interruption control unit) that controls interrupt control, and 102 is a processor.

101a0 is a standard interval timer interrupt signal, 101a1 to 101a7 are various interrupt signals, 102a is a signal for requesting an interrupt to a processor (INT signal), 101b is an interrupt acknowledge signal,
102b0 to 102b7 are signals for sending 1-byte interrupt vector timing to the processor through the data bus.

An example of this operation will be described in detail below with reference to FIG.

Interval timer interrupt signal 101a0 generated from the interval timer circuit 100
Generates an edge in a constant cycle, as indicated by edge timings 1, 2, and 3 in the time chart.

At this time, the interrupt control unit 101
Sends an interrupt request signal 102a to the processor 102 (timing 8). Then, the processor 102 returns the interrupt acknowledge signal 101b as low level pulses (timings 11 and 12) several times (generally two or three times, and the example shown is two times).

Accordingly, the interrupt control unit 10
1 is an interrupt vector by an 8-bit data bus
The data 102b0 to 102b7 are transferred to the processor 102 (timing 17). The processor 102 determines the type of interrupt based on the transferred vector data,
To process.

The same operation is performed when an interrupt other than the interval timer circuit 100 occurs. As an example, assume that the interrupt signal 101a1 is generated. In response to the rise of the edge timing 4, the interrupt control unit 101 causes the interrupt request signal 102a
To the processor 102 (timing 9).

Then, the processor 102 returns the interrupt acknowledge signal 101b with two low level pulses (timings 13 and 14). Along with this, the interrupt control unit 101 transfers the interrupt vector data 102b0 to 102b7 to the processor 102 through the 8-bit data bus (timing 18). Processor 1
02 determines and processes the type of interrupt based on the transferred vector data.

Next, assume that an interrupt signal 101a1 (edge timing 6-7) is generated. then,
The interrupt control unit 101 uses the interrupt request signal 1
02a (timing 10) is sent to the processor 102.

Then, the processor 102 returns the interrupt acknowledge signal 101b with two low level pulses (timings 15 and 16). Along with this, the interrupt control unit 101 transfers the interrupt vector data 101b0 to 101b7 (timing 19) to the processor 102 through the 8-bit data bus.

The processor 102 determines the type of interrupt based on the transferred vector data and processes it.

When the interval timer interrupt signal 101a0 (edge timing 3) occurs during such a series of operation processing, the interrupt control unit 101 receives and holds the interrupt signal, and the interrupt request signal 102a ( Continue to assert timing 20).

The processor 102 uses the previous interrupt signal 1
As soon as the processing of 01a1 (edge timing 6-7) is completed, the interrupt request signal 102a (timing 20) is accepted, and the interrupt acknowledge signal 101b is returned by two low level pulses (timing 21, 22). Then, the interrupt control unit 101 uses the 8-bit data bus to generate the interrupt vector data 101b0-
101b7 (timing 23) is transferred to the processor 102.

The processor 102 determines the type of interrupt based on the transferred vector data and processes it.

As described above, if the interval timer interrupt interrupted at a constant cycle is not recognized by the processor 102, a problem will occur when performing timer processing that requires accuracy.

[0019]

In the conventional interrupt processing, when the interrupt signals 101a0 to 101a7 are generated and the processing takes time, that is, when other interrupt processing is prohibited for a long time, the processor 10
There is a problem that the period in which 2 is temporarily in the interrupt disabled state is prolonged and an interrupt from the interval timer circuit 100 interrupting at a fixed time cannot be accepted.

During general interrupt processing, the interval
When a timer interrupt occurs, the interrupt control unit 101 holds the signal once, and upon completion of the interrupt currently being processed, the signal held by the processor 102 is received and interrupt processing is performed.

However, for the same interrupt line, the interrupt controller holds the signal for one time, but cannot hold the signal for the second time and thereafter, so that the interval timer interrupt is further interrupted before the completion of the first timer interrupt process. If it occurs, the result is that the second interval timer interrupt is ignored.

A time lag occurs when the interval timer interrupt is used for accurate time counting or the like. An example of this operation will be described in detail below with reference to FIG.

It is assumed that the general interrupt signal 101a1 (edge timing 3-4 in the time chart) is generated. At that time, the interrupt control unit 101
Sends an interrupt request signal 102a (timing 5) to the processor 102. Then, the processor 102
Sets the interrupt acknowledge signal 101b to low level twice.
Return with pulse (timing 7, 8).

Accordingly, the interrupt controller 10
1 transfers the interrupt vector data 101b0-101b7 (timing 11) to the processor 102 through the 8-bit data bus.

When the interval timer interrupt signal 101a0 (edge timing 1) is generated during such a series of operation processing, the interrupt control unit 1 is in the interrupt disabled period because of the processing of the general interrupt.
01 receives and holds an interrupt signal, and the processor 10
The interrupt request signal 102a for 2 (timing 6) is continuously asserted. At this time, when the interval timer interrupt signal 102a (edge timing 2) is further generated, the interrupt control unit 101 has already asserted the interrupt request signal 102a, so this interrupt processing is ignored.

The processor 102 uses the previous interrupt signal 1
As soon as the processing of 01a1 (timing 3-4) is completed, the interrupt request signal 102a (timing 6) is accepted,
The interrupt acknowledge signal 101b is returned by two low level pulses (timing 9, 10).

The interrupt control unit 101
Is an interrupt vector
The data 101b0 to 101b7 (timing 12) are transferred to the processor 102.

The processor 102 determines the type of interrupt based on the transferred vector data and processes it.

As described above, since the signal of the interval timer interrupt more than twice cannot be held during the interrupt processing, the interrupt is ignored. Unless the interval timer interrupt interrupted at a constant cycle is recognized by the processor 102, a problem may occur when performing timer processing that requires accuracy.

An object of the present invention is to provide an interrupt control system which prevents loss of interval timer interrupts.

[0031]

According to the present invention, in order to solve the above problems, an interrupt control unit receives an interval timer interrupt signal and a general interrupt signal which are generated at a constant period, and the interrupt control unit is directed to a processor. The processor makes an interrupt request, returns an interrupt enable signal for the interrupt request to the interrupt control unit, performs processing according to the vector data received from the interrupt control unit, and when another interrupt occurs during this processing, In the interrupt control method, in which the interrupt control unit holds the interrupt state only once for each interrupt signal and issues an interrupt request to the processor when the current interrupt processing is completed, when the interval timer interrupt signal is generated. To keep that state A state holding circuit, and an NMI notifying circuit for notifying the processor of the occurrence of a non-maskable interrupt when the next interval timer interrupt signal is generated while the interrupt state holding circuit is holding the interval timer interrupt signal. When the vector data is an interval timer interrupt vector, an interrupt processing end signal is received from the processor, and the interrupt state holding circuit and the NMI notification circuit are released when the processor generates an interrupt enable signal. And an interval timer vector decoder circuit for performing.

Further, according to the present invention, an interval timer interrupt signal and a general interrupt signal generated at a constant period are accepted by an interrupt control unit, the interrupt control unit issues an interrupt request to a processor, and the processor interrupts the interrupt request. In an interrupt control system for performing processing, a counter circuit for counting the occurrence of the interval timer interrupt signal,
An interrupt request circuit for storing the generation of the interval timer interrupt signal and continuing to generate the interval timer interrupt signal in the interrupt control unit, wherein the processor is the counter when executing the processing of the interval timer interrupt. It is characterized in that the count value of the circuit is read from the data bus, the interval timer interrupt processing is executed by the difference between this count value and the previous count value, and the request of the interrupt request circuit is released.

[0033]

When the interval timer interrupt is generated twice during the interrupt disable period during which the processor is executing general interrupt processing, the interrupt control unit holds the interrupt signal as a regular interrupt signal at the first time and the NMI notification at the second time. Notifying the processor prevents loss of interval timer interrupts.

When the interval timer interrupt processing is performed, the interval timer vector decoder circuit clears the interrupt state holding circuit and the NMI notification circuit and waits for the next interval timer interrupt.

Further, the number of interval timer interrupts generated during execution of general interrupt processing by the processor is stored in the counter circuit and an interrupt request is issued by the interrupt request circuit, and the processor completes general interrupt processing. When executing the interval timer interrupt processing, the interval timer interrupt processing can be eliminated by executing the interval timer interrupt by the difference in the number of interval timer interrupts that occurred between the previous and current interval timer interrupt processing. To prevent.

[0036]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, 301 is an interval timer circuit, 30
3 is an interrupt controller, 304 is an interval timer interrupt state holding circuit having a flip-flop configuration,
305 is a flip-flop configuration, and the processor 1
NMI notification circuit for notifying 02 that an NMI (non-maskable interrupt provided in a general processor and provided in addition to a normal interrupt input) has occurred,
Reference numeral 306 is a decoder circuit for an interval timer interrupt vector, and 307 is a processor and its peripheral circuits.

301a is an interval timer circuit 30
1 is an interrupt request signal, 303a is a general interrupt request signal, 303b is an interrupt request signal for the processor, 303c is a vector data bus, 304a is a signal for holding an interrupt state, 305a is an NMI request signal for the processor, and 306a is An interval timer interrupt enable signal (clear), 307a is an interrupt enable signal from the processor, and 307b is a signal indicating an interrupt process of the processor.

The interrupt state holding circuit 304 holds the state when an interval timer interrupt signal is generated by a flip-flop having a data input as a pull-up and an interval timer interrupt signal as a clock input.

The NMI notification circuit 305 uses the interval
When the second interval timer interrupt signal is generated by the flip-flop which receives the signal 304a of the holding state of the timer interrupt signal as the data input and the interval timer interrupt signal as the clock input, the non-maskable interrupt is generated in the processor. Notice.

In the interval timer vector decoder circuit 306, the vector data 303c is an interval timer interrupt vector, and the processor 30
7 to receive the interrupt processing end signal 307b, and when the processor generates the interrupt enable signal 307a, the interrupt state holding circuit 304 and the NMI notification circuit 30
Clear (clear) the state of 5.

FIG. 2 shows an expanded example of the interval timer interrupt vector decoder circuit 306.

First, the processor 307 initializes the interrupt controller 303 and the interval timer circuit 301, enables the interrupt of the processor itself, and the interval timer circuit 301 sends an interrupt request signal 301a to the interrupt controller 303. When asserted, the interrupt controller 303 asserts the interrupt request signal 303b.

At the same time, the interrupt state holding circuit 30
4 is set, and the interrupt state holding signal 304a is asserted.

The processor 307 accepts this interrupt, disables the interrupt of the processor itself, asserts the interrupt processing end signal 307b, and asserts the interrupt permission signal 307a twice.

The processor 307 causes the vector code data bus 303c of the interrupt controller 303 by the second rise of the interrupt enable signal 307a.
Receives the vector code from

In the vector decoder circuit 306 of the interval timer, this vector code is the vector of the interval timer interrupt, and the interrupt processing signal 307
When b is asserted, the signal 306a for clearing the interrupt state holding circuit 304 and the NMI notification circuit 305 is asserted at the second pulse timing of the interrupt permission signal 307a of the processor 307.

Processor 3 that received the vector code
07 starts the interval timer interrupt process,
When the processing is completed, the interrupt processing signal 307b is negated and the interrupt of the processor itself is enabled.

Next, when the general interrupt signal 303a is asserted, the interrupt controller 303 asserts the interrupt signal 303b for the processor. However, the interrupt state holding circuit 304 is not set because it is not an interval timer interrupt.

The processor 307 accepts this interrupt, disables its own interrupt,
The interrupt processing signal 307b is asserted, and the interrupt permission signal 307a is asserted twice. The processor 307 receives the vector code from the vector code data bus 303c of the interrupt controller 303 at the second rise of the interrupt enable signal 307a.

Processor 3 that received the vector code
07 starts a predetermined interrupt process.

When the interval timer interrupt signal 301a is asserted during this process, the interrupt controller 303 asserts the interrupt request signal 303b to the processor 307. However, since the processor 307 is in the process of interrupting, it does not assert the interrupt permission signal 307a. Therefore, the interval timer interrupt processing waits for the processing. At this time, the interrupt state holding circuit 304 receives the interrupt and is set.

Further, when the interval timer interrupt signal 301a is asserted, the interrupt controller 303 is in a state of accepting the previous interval timer interrupt, and therefore does not accept the interrupt of this time.

Therefore, no vector code is output from the interrupt controller 303, and the processor 307
Since the interrupt permission signal 307a of 1 is not output, the signal 306a for clearing 304 and 305 is not asserted even though the interrupt processing signal 307b is asserted.

Therefore, the interrupt state holding circuit 3 has already been
Since 04 is set, the NMI notification circuit 305 is set to notify the processor 307 of the NMI and notify that the interval timer interrupt request has been generated twice during the current interrupt processing.

This operation is the basic operation of the present invention. With this circuit configuration, "while the processor is executing another interrupt process, for example, even if an interval timer interrupt occurs twice, the first interrupt The signal is held by the interrupt controller, and the processor performs the process as soon as the interrupt process that is currently being performed is completed. In addition, the NMI can notify this by the second time. "

For this reason, in the interrupt recognition type processor system adopting this circuit configuration, although the interval timer interrupt request is input twice while the processor is executing an interrupt having a long processing time, Since the interrupt controller can accept only one interrupt, the NMI notifies the second interrupt request so that the second interrupt request is not discarded.

FIG. 3 shows the state of the interrupt system in the case of the present circuit configuration, as compared with the state in which the interrupt is discarded in the conventional interrupt system shown in FIG.

The operation will be described in detail below in the order of the timings additionally shown in the time chart of FIG.

(Timing 1) Interval timer circuit 301 requests an interrupt and interrupt request signal 301
Assert a.

(Timing 2) Interrupt controller 3
03 requests an interrupt and asserts an interrupt request signal 303b.

(Timing 3) Interrupt state holding circuit 3
04 is set, and the interrupt state holding signal 304a is asserted.

(Timing 4) The processor 307 starts interrupt processing and asserts a signal 307b indicating that interrupt processing is being executed.

(Timing 5) The processor 307 starts interrupt processing and asserts the interrupt permission signal 307a twice.

(Timing 6) Interrupt controller 3
03 activates the vector code data bus 303c.

(Timing 7) Interrupt controller 3
03, after knowing that the processor 307 has accepted the interrupt, negates the interrupt request signal 303b.

(Timing 8) A signal 30 for clearing the interrupt state holding circuit 304 and the NMI notification circuit 305 due to the output of the interval timer interrupt.
Assert 6a.

(Timing 9) Interrupt state holding circuit 3
04 is cleared and the interrupt state holding signal 304a is negated.

(Timing 10) The processor 307
The signal 307b indicating that the interrupt processing is being executed is negated.

The above is the normal operation of the interval timer interrupt.

(Timing 11) A general interrupt circuit requests an interrupt and asserts the interrupt request signal 303a.

(Timing 12) The interrupt controller 303 requests an interrupt, and the interrupt request signal 303b
Assert.

(Timing 13) The processor 307 starts interrupt processing and asserts a signal 307b indicating that interrupt processing is being executed.

(Timing 14) The processor 307 starts interrupt processing and asserts the interrupt permission signal 307a twice.

(Timing 15) The interrupt controller 303 activates the vector code data bus 303c.

(Timing 16) After knowing that the processor 307 has accepted the interrupt, the interrupt controller 303 negates the interrupt request signal 303b.

(Timing 17) The interval timer circuit 301 requests an interrupt, and the interrupt request signal 30
Assert 1a.

(Timing 18) The interrupt controller 303 requests an interrupt, and the interrupt request signal 303b
Assert.

(Timing 19) The interrupt state holding circuit 304 is set at the rising edge of the interrupt request signal 303b.

(Timing 20) The interval timer 301 requests an interrupt, and the interrupt request signal 301a
Assert.

(Timing 21) NMI notification circuit 305
At (timing 17), the interrupt by the interval timer interrupt is prohibited and cannot be accepted, so the interrupt vector is not output from the interrupt controller 303.

Therefore, the interval timer interrupt vector decoder circuit does not output, and the interrupt state holding signal 304a remains asserted,
Assert the NMI request signal 305a. This allows
The processor 307 is subjected to NMI.

Here, in the NMI processing, if the interval timer interrupt processing is performed, the interval
The timer interrupt will not be lost.

As described above, in this embodiment, the interrupt state holding circuit 304 of the interval timer circuit, the NMI notification circuit 305, and the timer vector decoder circuit 306 for clearing these circuits at the time of normal operation are provided. , 1 even if the interval timer interrupt signal is generated twice during the interrupt disable period by general processing
Regular interrupt processing is performed the second time, and the second time can be notified to the processor 307 by NMI notification, and loss of the interrupt signal due to the interval timer can be prevented.

FIG. 4 is a circuit diagram showing another embodiment of the present invention. In the figure, 401 is an interval timer circuit,
Reference numeral 402 is a timer interrupt request circuit, 403 is an interrupt controller, and 404 is a processor and its peripheral circuits.

401a is an interval timer circuit 40
1 is an interrupt request signal, 402a is an interrupt request signal from the timer interrupt request circuit 402, 403a is a general interrupt request signal, 403b is an interrupt request signal for a processor, 403c is a vector data bus,
Reference numeral 404a is an interrupt enable signal for the processor.

An example in which the timer interrupt request circuit 402 is expanded is shown in FIG. 502 is a pulse counter for counting the number of occurrences of the interval timer interrupt request signal 401a, and 503 is a circuit for storing the occurrence of the interval timer interrupt and requesting the processor 404 for the interrupt.

In this configuration, when the interval timer 401 asserts the interrupt request signal, the interrupt request circuit 503 in the timer interrupt request circuit 402 continues to assert the interrupt request signal 402a.

As a result, the interrupt controller 40
3 is an interrupt request signal 403 to the processor 404
Assert b.

The processor 404 accepting this interrupt request asserts the interrupt enable signal 404a twice. The processor 404 uses the second interrupt enable signal 40
Vector data is received from the data bus 403c at the rising edge of 4a.

Processor 4 receiving vector data
04 starts the interval timer interrupt processing. First, the processor 404 uses the pulse counter 502.
Value is read from the data bus 403c, the interrupt request circuit 503 is reset, the interval timer interrupt process is performed for the difference in the number of interrupts from the previous interval timer interrupt to the current interval timer interrupt, and the process ends.

Next, when the general interrupt signal 403a is asserted, the interrupt controller 403 asserts the interrupt signal 403b to the processor 404.

The processor 404 accepts this interrupt and asserts the interrupt permission signal 404a twice. The processor 404 uses the second interrupt enable signal 4
Interrupt controller 40 by the rising edge of 04a
3 receives vector data from the data bus 403c.

Processor 4 receiving vector data
04 starts a predetermined interrupt process.

When the interval timer interrupt signal 401a is asserted during this processing, the timer interrupt request circuit 402 asserts the interrupt request signal 402a, and the interrupt controller 403 sends the interrupt request signal to the processor 404. Assert 403b.

However, since the processor 404 is in the process of interrupting, it does not assert the interrupt enable signal 404a. Therefore, the interval timer interrupt request has to wait for its processing.

In this state, the pulse counter 502 in the timer interrupt request circuit 402 counts the number of times the interval timer interrupt signal 401a is asserted.

When the processor 404 receives the interrupt signal 403b after finishing the processing currently being executed, the interrupt enable signal 404a is asserted twice. Processor 40
4 receives the vector data from the data bus 403c at the second rise of the interrupt enable signal 404a.

Processor 4 receiving vector data
04 starts the interval timer interrupt processing. First, the processor 404 uses the pulse counter 502.
Value is read from the data bus 403c, the interrupt request circuit 503 is reset, interval timer interrupt processing is performed for the number of interrupts, and the processing ends.

Such an operation is the basic processing of the present embodiment, and by this, "even if an interval timer interrupt occurs twice or more while the processor is executing general interrupt processing, this interrupt Count the number of times, and as soon as the interrupt processing currently being performed is completed,
The processor executes the interval timer processing for the number of interrupts ".

Therefore, in the present embodiment, even if the interval timer interrupt request is generated a plurality of times while the processor is executing an interrupt having a long processing time, the interrupt request is counted so as not to be discarded. As a result, the processor can process as many times as the number of input interrupts.

FIG. 6 shows a time chart of the interrupt processing of this embodiment. The operation will be described in detail below in the order of the timings shown in FIG.

(Timing 1) A general interrupt circuit requests an interrupt and asserts an interrupt request signal 403a.

(Timing 2) Interrupt controller 4
03 asserts the interrupt request signal 403b.

(Timing 3) The processor 404 starts interrupt processing and asserts the interrupt enable signal 404a twice.

(Timing 4) Interrupt controller 4
03 activates the data bus 403c.

(Timing 5) Interval timer 4
01 requests an interrupt and asserts an interrupt signal 401a.

(Timing 6) The pulse counter 502 in the timer interrupt request circuit 402 causes the interrupt signal 401
Count a and count up.

(Timing 7) The interrupt request circuit 503 in the timer interrupt request circuit 402 requests an interrupt and asserts the interrupt request signal 402a.

(Timing 8) Interrupt controller 4
03 requests an interrupt and asserts an interrupt request signal 403b.

(Timing 9) Interval timer 4
01 requests an interrupt and asserts an interrupt request signal 401a.

(Timing 10) The pulse counter 502 in the timer interrupt request circuit 402 causes the interrupt signal 40
Count 1a and count up.

(Timing 11) By the processor 404 controlling the interrupt source in the interrupt processing,
The interrupt request signal 403a is cleared, and the interrupt process ends.

(Timing 12) The processor 404 starts the interrupt processing and asserts the interrupt permission signal 404a twice.

(Timing 13) The interrupt controller 403 activates the data bus 403c.

(Timing 14) The pulse counter 502 in the timer interrupt request circuit 402 is connected to the data bus 40.
Activate 3c.

The processor 404 now reads the value of the pulse counter 502 and compares it with the previous value,
Determine how many interval timer interrupts have occurred from the previous interrupt to this interrupt, and process the interrupted number of times. At the same time, the read pulse count value is stored in a storage means such as a memory.

(Timing 15) The processor 404
Interrupt request circuit 5 in timer interrupt request circuit 402
03 is reset.

As described above, in the present embodiment, the number of interval timer interrupt requests is counted, and this is read at each interval timer interrupt and compared with the previous value to determine the number of interrupts. Since the interval timer interrupt processing is executed for the number of interrupts, it is possible to prevent loss of the interval timer interrupt.

[0119]

As described above, according to the present invention, when the interval timer interrupt is generated twice during the interrupt disable period during which the processor is executing the general interrupt process, the interrupt control unit first causes the interrupt to occur normally. Since it is held as an interrupt signal and notified to the processor by NMI notification for the second time, it is possible to prevent the loss of the interval timer interrupt.

Further, according to the present invention, the interval timer interrupt count generated during execution of general interrupt processing by the processor is stored and an interrupt request is made, and the processor completes the general interrupt processing and the interval timer When interrupt processing is executed, interval timer interrupts are executed by the difference in the number of interval timer interrupts that occurred between the previous and current interval timer interrupt processing, preventing loss of interval timer interrupt processing. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an example of development of an interval timer vector decoder circuit.

FIG. 3 is an example of interrupt processing according to the embodiment.

FIG. 4 is a block diagram of another embodiment.

FIG. 5 shows an example of a timer interrupt request circuit according to another embodiment.

FIG. 6 shows an example of interrupt processing according to another embodiment.

FIG. 7 shows an example of conventional interrupt control.

FIG. 8 shows an example of a period during which another interrupt is prohibited by the interrupt processing of the processor.

FIG. 9 is an example of a period in which another interrupt is prohibited by the interrupt processing of the processor.

[Explanation of symbols]

 301, 401 ... Interval timer circuit 303, 403 ... Interrupt control section 304 ... Interrupt state holding circuit 305 ... NMI notification circuit 306 ... Interval timer vector decoder circuit 307, 404 ... Processor 402 ... Timer interrupt request circuit

Claims (2)

[Claims] 1. An interrupt control unit receives an interval timer interrupt signal and a general interrupt signal that are generated at regular intervals, the interrupt control unit issues an interrupt request to a processor, and the processor interrupts an interrupt enable signal for the interrupt request. Performs processing according to the vector data returned to the control section and received from the interrupt control section, and when another interrupt occurs during this processing, the interrupt control section holds the interrupt state only once for each interrupt signal. In the interrupt control method for issuing an interrupt request to the processor when the current interrupt processing is completed, an interrupt state holding circuit that holds the state when the interval timer interrupt signal is generated, and the interrupt state holding circuit Is in An NMI notification circuit for notifying the processor of the occurrence of a non-maskable interrupt when the next interval timer interrupt signal is generated while holding the global timer interrupt signal, and the vector data is a vector of the interval timer interrupt. Yes, and when the interrupt processing end signal is received from the processor and the processor generates an interrupt enable signal, the interrupt state holding circuit and the NMI
An interrupt control method comprising: an interval timer vector decoder circuit for releasing the state of the notification circuit. 2. An interrupt which accepts an interval timer interrupt signal and a general interrupt signal which are generated at a constant cycle in an interrupt control unit, the interrupt control unit issues an interrupt request to a processor, and the processor performs interrupt processing in response to the interrupt request. In the control method, a counter circuit that counts the occurrence of the interval timer interrupt signal, and an interrupt request circuit that stores the occurrence of the interval timer interrupt signal and continues to generate the interval timer interrupt signal in the interrupt control unit The processor reads the count value of the counter circuit from the data bus when executing the processing of the interval timer interrupt, and the interface reads only the difference between the count value and the previous count value. 1. An interrupt control method, wherein a timer interrupt process is executed and a request from the interrupt request circuit is canceled.