JPH0541441A - Testing method for integrated circuit - Google Patents

Abstract

PURPOSE:To reduce test time necessary to a defective article, by performing a test by using a test flow wherein the number of defective in each test item of a test flow of an initially set specific order is counted, and the sequence of test items is rearranged after a specified period, in the order of the number of counts. CONSTITUTION:Firstly, the same flow as an initially set program is executed, and tests 1, 2, 3,..., N are progressed in order. As to an IC which becomes defective in the cource of test, the test is finished by said test item. Counting is performed by counters 1a-Na of the item, and the test is transferred to the next IC to be tested. After a specified interval is passed, the number of counts of the counters 1a-Na are mutually compared. The test items are automatically rearranged in the order of the number of counts. The above interval is set by the number of ICs to be tested, or by the number of tested wafers in the case of IC chips in the wafer state. Thereby defective ICs can be comparatively rapidly decided to be defective.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a method for testing integrated circuits.

[0002]

2. Description of the Related Art A program used in a conventional integrated circuit (IC) testing method is divided into a plurality of test items, which are arranged in a certain order to form one program. In this arrangement, the simplest and most important ones in terms of the characteristics of the IC are placed first, and the functional test is gradually made difficult. By this method of assembly, general mistakes such as electrical contact mistakes that are completely different from the function of the IC can be found early.

FIG. 1A is a flow chart for explaining an example of a conventional integrated circuit testing method. Testing of one IC under test starts from test 1 and ends at test N. If the test item on the way becomes defective, the test ends there, and the next IC under test is tested.

For example, a non-test IC that becomes defective in test 3
Always executes tests 1 and 2 and then receives test 3 and is determined to be defective, and the test ends.

[0005]

A program used in a conventional integrated circuit testing method is formed by a constant permuted flow. The characteristics and functions of ICs largely depend on their diffusion state, and the defective contents of defective products are biased depending on the lot.

Therefore, in the conventional program flow, even if the defective test item is known in advance, there is a problem that it cannot be determined as a defective product unless all the items from the beginning to the item are tested according to the flow.

Further, therefore, the measuring time required for the test of the unnecessary portion is lost time, which hinders the improvement of productivity.

[0008]

An integrated circuit test method according to the present invention is an integrated circuit test method for testing a plurality of electrical test items of a semiconductor device in a predetermined order. The number of failures in each test item of the test flow in the order of is counted, and then, after a predetermined time,
The permutation of test items is tested by a test flow in which the predetermined permutations are rearranged in the descending order of the count.

[0009]

The present invention will be described below with reference to the drawings. FIG. 1 is a flow chart of a program for explaining an embodiment of the present invention. (A) is a flow chart when an IC test is started, and (b) is a flow chart after a predetermined interval.

As shown in the flow of FIG. 1 (a), the flow is initially the same as when the program was created.
The test is performed in order of 2, 3, ..., N. For the IC under test that becomes defective during the test, the test is completed with the test item,
It is counted by the count 1a to Na of that item, and the test of the next IC to be tested is started.

After the lapse of a predetermined interval, as shown in FIG. 1B, the count numbers of the counters 1a to Na are compared with each other, and the test items are automatically rearranged in descending order of count. FIG. 1B is a flow chart after rearrangement when the count numbers of the counters 1a to Na become counter 3a> counter 2a> counter 1a. This interval is set by the number of tested ICs to be tested, or that of IC chips in a wafer state is set by the number of tested wafers.

In addition, the interval can be checked not only from the beginning to the interval but also repeatedly at the same intervals thereafter.
The test items are automatically rearranged after the interval, but the items which are not desired to be rearranged can be set in advance.

[0013]

As described above, according to the present invention, the flow of the IC test program can be automatically rearranged, so that defective test items can be arranged in descending order, and defective products can be determined to be defective early.

Therefore, the test time required for defective products can be shortened and the overall IC productivity (the number of outputs) can be improved.

[Brief description of drawings]

FIG. 1A and FIG. 1B are test flow charts for explaining an embodiment of the present invention.

[Explanation of symbols]

 1-N test item 1a-Na defective counter

Claims (1)

[Claims] 1. A method of testing an integrated circuit for testing a plurality of electrical test items of a semiconductor device in a predetermined order,
The number of failures in each test item in the initially set test flow in the predetermined order is counted, and after a predetermined time, the permutations of the test items are rearranged in the order of the count. A test method for an integrated circuit, characterized by performing a test flow.