JPH03203365A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable the automatic test of semiconductor integrated circuits wherein circuit operations on the same wafer are different, by arranging pads connected by using resistor elements determined by the kind of integrated circuits, on the identical positions of all chips. CONSTITUTION:Semiconductor integrated circuits 11, 12 whose circuit operations are different and whose number of pads, pad positions, chip sizes, etc., are equal are formed on the same wafer 13. When the integrated circuits are electrically tested, a tester arbitrarily selects either one of the circuits 11 and 12. When the circuit 11 is selected, it is recognized by measuring a resistor element 18 between pads 14, 15, and electric test of the circuit 11 is automatically started. When the circuit 12 is selected, it is recognized by measuring a resistor element 19 between pads 16, 17, and electric test of the circuit 12 is automatically started.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and in particular to semiconductor integrated circuits that have different circuit operations with the same number of pads, input/output pad positions, power supply pad positions, and chip sizes. This invention relates to semiconductor integrated circuits in which circuits are formed on the same wafer.

[Conventional technology]

Conventionally, as shown in FIG. 3, this type of semiconductor integrated circuit has been manufactured on the same wafer 33 in order to identify semiconductor integrated circuits 31 and 32 with different circuit operations. An identification symbol 34 consisting of a type number or alphanumeric characters of the semiconductor integrated circuit 31, 32 was provided in each chip.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuits described above, semiconductor integrated circuits with different circuit operations are identified by the type number of the semiconductor circuit provided in each chip or an identification symbol consisting of alphanumeric characters, etc. When using a tester to electrically test multiple semiconductor integrated circuits with different circuit operations created on the same wafer, prepare test programs for each semiconductor integrated circuit with different circuit operations, and The LS is designed to measure only one type of semiconductor integrated circuit to be tested in advance using the identification symbol.
The disadvantage is that the I tester must be configured.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit in which a plurality of semiconductor integrated circuits with different circuit operations are fabricated on the same wafer with the same number of pads, input/output pad positions, power supply pad positions, and chip size. In each chip of different semiconductor integrated circuits, a resistor element having an arbitrary resistance value determined for each semiconductor integrated circuit with a different circuit operation is installed, and in each chip of a semiconductor integrated circuit with a different circuit operation, the resistor element is connected to each other by the above-mentioned resistor element. The pads connected by resistive elements are provided at the same location in all chips constituting a semiconductor integrated circuit fabricated on the same wafer.

In this way, pads connected to each other by resistive elements having arbitrary resistance values determined for individual semiconductor integrated circuits with different circuit operations are provided at equal positions in all chips on the same chip, and the resistance value between the pads is adjusted. By measuring this, it is possible to identify semiconductor integrated circuits with different circuit operations.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. 11.12 is the number of pads for semiconductor integrated circuits with different circuit operations.

Semiconductor integrated circuits constructed on the same wafer 13 with chips having the same input/output pad positions, power supply pad positions, and chip sizes, 14.15 inside the semiconductor integrated circuits 11 connected to each other by resistive elements 18 having arbitrary resistance values R; Pads 16 and 17 provided in the semiconductor integrated circuit 12 are provided in the semiconductor integrated circuit 12 which are connected to each other by a resistance element 19 having a resistance value of 2R in which two resistance elements 18 are connected in series.
．． This is a pad provided at the same position as No. 15.

Next, a case will be described in which the semiconductor integrated circuits 11 and 12 are electrically tested using an LSI tester at the wafer stage.

The test program used in this test measures the resistance value between pads 14.15 or pads 16.17 before testing the semiconductor integrated circuit 11.12, and determines the electrical resistance of the semiconductor integrated circuit 11 or 12 based on the measured resistance value. This is a test program that performs tests.

The LSI tester is set so that semiconductor integrated circuits 11 and 12 are arbitrarily selected and measured.

When an electrical test is performed using the test settings described above, the tester arbitrarily selects either one of the semiconductor integrated circuits 11 and 12.

When the semiconductor integrated circuit 11 is selected, the resistance element 18 between the pads 14 and 15 is measured.
1, and automatically starts an electrical test of the semiconductor integrated circuit 11.

Further, when the semiconductor integrated circuit 12 is selected, the pad 16.
By measuring the resistance element 19 between 17 and 17, it is identified that it is a semiconductor integrated circuit I2, and the semiconductor integrated circuit 1 is automatically detected.
Start electrical test No. 2.

FIG. 2 shows another embodiment of the invention.

21.22 is a PAD semiconductor integrated circuit with different circuit operations.
A semiconductor integrated circuit constructed on the same wafer 23 with chips having the same number, input/output pad positions, power supply pad positions, and chip size, 24.25 is an Nch MO8) transistor 28 having an arbitrary ON resistance value R, a pad provided within the connected semiconductor integrated circuit 27;
26.27 is provided in the semiconductor integrated circuit 22 in which two NchMO8) transistors 28 are connected in series with an NchMO8I transistor 29 having an ON resistance value of 2R, and is provided at the same position as the PADs 24 and 25. It is a pad.

Next, a case will be described in which the semiconductor integrated circuits 21 and 22 on the same wafer 23 are electrically tested using an LSI tester at the wafer stage. The test program used for this test is
4.25 or the resistance value between the pads 26 and 27, and the semiconductor integrated circuit 21. or 22
This is a test program that performs electrical tests.

The LSI tester is set to measure semiconductor integrated circuits 21 and 22.

When performing the electrical test under the test settings described above, L
The SI tester arbitrarily selects the semiconductor integrated circuit 21 or 22. Pad 2 when semiconductor integrated circuit 21 is selected
The ON resistance value of the resistance element 28 between 4.25 and 25 is measured, the semiconductor integrated circuit 21 is identified, and an electrical test of the semiconductor integrated circuit 21 is automatically started. Also, when the semiconductor integrated circuit 22 is selected, the resistor element 29 between the pads 26 and 27
The ON resistance value of the semiconductor integrated circuit 22 is measured, the semiconductor integrated circuit 22 is identified, and an electrical test of the semiconductor integrated circuit 22 is automatically started.

〔Effect of the invention〕

As explained above, the present invention provides a semiconductor integrated circuit in which a plurality of semiconductor integrated circuits having different circuit operations are fabricated on the same wafer with the same number of pads, input/output pad positions, power supply pad positions, and chip sizes. Each chip of a semiconductor integrated circuit with a different circuit operation has pads connected to each other by a resistor element having an arbitrary resistance value determined by the type of semiconductor integrated circuit with a different circuit operation; By providing pads at the same positions on all chips on the same wafer, it is possible to automatically test semiconductor integrated circuits with different circuit operations on the same wafer during electrical testing of semiconductor integrated circuits using an LSI tester at the crossbar stage. This has the effect of shortening test time.

[Brief explanation of drawings]

FIG. 1 shows a first embodiment of the present invention, and FIG. 2 shows a second embodiment of the present invention.
The embodiment shown in FIG. 3 is a conventional example. 11.12, 21.22, 31.32... Semiconductor integrated circuits with different circuit operations, 13, 23.33...
...Wafer 14.15,16,17,2425.
26, 27.35...Pad, 18.19...
...Resistance element, 28.29...N c b
MoS) transistor, 34... identification symbol,
IA...Enlarged view of semiconductor integrated circuit 11, IB.
...Enlarged view of semiconductor integrated circuit 12, 2A...
... Enlarged view of semiconductor integrated circuit 21, 2B... Enlarged view of semiconductor integrated circuit 22.

Claims (1)

[Claims] In a semiconductor integrated circuit where multiple semiconductor integrated circuits with different circuit operations are created on the same wafer with the same number of pads, input/output pad positions, power supply pad positions, and chip size, each chip of the semiconductor integrated circuit with different circuit operations A semiconductor integrated circuit with different circuit operations, which includes pads connected to each other by resistive elements having arbitrary resistance values determined for each individual semiconductor integrated circuit, and in which the pads connected to each other by the resistive elements are fabricated on the same wafer. A semiconductor integrated circuit characterized in that it is provided at the same position within all chips constituting the integrated circuit.