JPH08274176A - Semiconductor device - Google Patents

Abstract

PURPOSE: To easily sort a plurality of IC chips having different functions from each other even when the IC chips are arranged on the same substrate by measuring the drain-source voltages of specific transistors and recognizing the positions of the semiconductor chips on the semiconductor substrate from the voltage values, etc. CONSTITUTION: On a semiconductor substrate, electrodes 11 are provided at prefixed positions or the same position and a plurality of semiconductor chips having different functions which are actuated when a prescribed voltage is applied to the electrodes 11 and a prescribed input signal is supplied to the electrodes 11 are arranged in a plane. In such a semiconductor device, transistors having different characteristics or connections against each function are provided between the electrodes 11. The drain-source voltages V0 of the transistors are measured and the positions of the semiconductor chips arranged in the same plane are recognized from the voltage values or resistance values of resistance elements.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device advantageous for discriminating different functions.

[0002]

2. Description of the Related Art In recent years, with the development of LSI-related technology, a circuit desired by a user can be realized relatively freely as an LSI. In addition, it becomes possible to integrate a large-scale circuit on one chip, and development and production of a large number of small-quantity products are required.

In general, LSI has been attempted to reduce the manufacturing cost for mass production by arranging a plurality of chips on the same substrate and manufacturing them at the same time. As a means for responding to the demand for a small amount and a large variety of products without impairing such characteristics, there is a method of arranging and manufacturing LSIs having different functions on the same substrate. In particular, in the case of the master slice method, it is possible to form various types of LSIs having different functions by changing the wiring connections in the post process of the process on the semiconductor substrate called the base in which the basic cells are prefabricated in the pre process of the manufacturing process. it can.

Next, it is necessary to judge whether the LSI on the substrate is tested on a chip-by-chip basis. As a chip arranging method corresponding to automation, as shown in FIG. LSIs having the same function are arranged. However, as a method of arranging LSIs having a plurality of types of functions in order to utilize the above-mentioned features and coping with automation, chips having different functions are arranged for each column or each row (FIGS. 3B and 3). (See (c)).

In the case of the arrangement on the substrate shown in FIG. 3B, the chip A1 is first probed and tested, and then the lateral movement amount is moved as the sum of the lateral dimensions of the chip A1 and the chip B1. , Chip A2 is probed and tested. Similarly, when the test of the chip A3 is completed, the chip A3 is moved in the vertical direction by the vertical dimension of the chip A3 to test the chip A4. When the test of the chip A4 is completed, the chip B1 is probed and the tests are sequentially performed in the same manner as the tests of the chips A1 to A4.

In the case of the arrangement on the substrate shown in FIG. 3 (c),
The test is sequentially performed by setting the vertical movement amount as the sum of the vertical dimensions of the chips A1 and B1 and the horizontal movement amount as the horizontal dimension of the chip A1. The arrangement on the substrate shown in FIG. 3 (d) is an n ₂ arrangement, and the arrangement shown in FIG.
Alternatively, as in the case of the chip arrangement shown in FIG.
The horizontal movement amount is the sum of the horizontal dimensions of the chips A1 and B1, and the vertical movement amount is the chips A1 and C1.
Of the chips (A _i , B _i , C _i ,
The test is performed in the order of D _i , i is an integer. In these cases, the starting point of the test had to be probed on the chip to be tested, and it was done visually, so that it was very difficult for a high-density and similar LSI such as a master slice.

In order to solve this drawback, JP-A-58-58
Japanese Patent No. 176966 discloses a semiconductor device that uses a resistor having a value that differs for each function between electrodes located at predetermined positions.

[0008]

However, in the above-mentioned known example, it is necessary to dispose the resistor at a predetermined position. In order to distinguish the difference of LSI by resistance,
It will be determined by the current and the voltage. In this case, if the range in which the voltage can be determined is about 0.1 V, the current is several meters.
Even if it is about A, a resistance of about several KΩ is required, so that there is a problem that a large area is required. Further, in the case of the master slice which requires a specific terminal and has the largest usage range, there is a problem that a new area is required because it is almost covered with transistors.

[0009]

According to the present invention, there is provided a semiconductor device comprising:
A plurality of semiconductor chips each having an electrode at a predetermined position or at the same position on a semiconductor substrate, and having a predetermined voltage source and an input signal applied to the electrode and having different functions of a semiconductor chip performing a predetermined function are provided. In a semiconductor device arranged on a plane, a transistor having different characteristics for each function or a resistive element having different connection is provided between the electrodes, and a voltage between a drain and a source of the transistor is measured to measure the voltage. According to the value or the resistance value of the resistance element, the position on the semiconductor substrate of the semiconductor chip arranged on the plane is recognized.

[0010]

In the semiconductor device of the present invention, instead of using resistors arranged at predetermined positions, the characteristics of the extra input / output terminals are used to select LSIs having different functions. The output terminal is composed of a combination of a large number of transistors in order to secure driving capability.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1A shows a structure of a transistor of an output circuit of a semiconductor device according to an embodiment of the present invention. The output circuit has a plurality of transistors (P1
.About.Pn, N1 to Nn). Output terminal 11 by this combination of transistors
The voltage drop V0 when the current (I) is injected is different. For example, in the case of a MOS transistor, the voltage drop V0 per one transistor Nn of the inverter 21 composed of the transistor Pn and the transistor Nn is about 0.7.
V, and the output circuit shown in FIG.
Since the voltage drop in the case of being composed of individual pieces is about 1.4 V, the difference between the chips can be discriminated.

In the semiconductor device of the present invention, the chip A is shown in FIG.
The chip B has the output circuit shown in FIG. 1B, and the chip B has the output circuit type shown in FIG.

When selecting non-defective chips from the semiconductor substrate that has undergone the diffusion process and the wiring process, the electrical characteristics of each of the chips A and B are tested. At this time, the chip A must be tested under the test conditions compatible with the chip A, and the chip B must be tested under the test conditions compatible with the chip B. Therefore, whether the chip to be tested is A or B is determined in advance, and the test is performed under each test condition based on the determined result.

FIG. 2 shows the flow of this test. First, the voltage drop of the transistor according to the present invention connected to a specific terminal is measured to determine whether it is chip A or chip B. Next, a test is performed under measurement conditions suitable for each, and the quality is judged. By setting the test program having such a flow in the automatic tester, it is possible to judge the quality in one process. In addition, since the chips are automatically identified, it is not necessary to visually set the starting point, and even two types of chips randomly arranged on the same substrate can be tested without specifying the starting point. it can.

In this embodiment, the transistor configuration of the output of a specific terminal is different, or the transistor of an empty terminal is used.

The LSI of the master slice can configure circuits of an unspecified number of users, and it is very unlikely that the configurations of outputs having different driving capabilities match at the output terminals. Some terminals have different driving capabilities. Therefore, the chip is identified using the output terminal used as the signal line.

Although the embodiment is shown here for two types of chips A and B, various types of chips can be dealt with by combining transistors and combining output terminals. It is also possible to deal with irregular arrangements.

[0019]

As is apparent from the above description, by using the present invention, a plurality of ICs having different functions on the same substrate.
Even if chips are arranged, they can be easily selected, and the effects of reducing manufacturing costs and automating inspection are great.

For example, when 100 chips can be obtained from one wafer and 30, 30, 40 and non-defective products of chips A, B, and C are required, respectively, in the conventional method, 3 chips can be obtained. Although one wafer was required, the method according to the invention will only require one wafer. Further, in the case of the method of adding the resistance, at least two terminals cannot be used for the resistance terminals, but the present invention enables the effective use of the terminals by using the empty terminals.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of an output terminal of an embodiment of the present invention in a CMOS type LSI.

FIG. 2 is a flow chart when a probing test is performed on an embodiment of the present invention.

FIG. 3 is an example of a chip arrangement having a plurality of types of functions.

[Explanation of symbols]

11 output terminals 21-23 output circuit P1, P2 P-type MOS transistor N1, N2 N-type MOS transistor A1-An, B1-Bn, C1-Cn, D1, D2
LSI

Claims (1)

[Claims] 1. A semiconductor chip having electrodes at predetermined positions or at the same position on a semiconductor substrate, and a predetermined voltage source and an input signal are applied to the electrodes to perform predetermined functions and different functions of a semiconductor chip. A plurality of semiconductor devices arranged on a plane, each of which has a transistor having different characteristics for each function or a resistive element having a different connection between the electrodes, and a voltage between a drain and a source of the transistor. Is measured and the position on the semiconductor substrate of the semiconductor chip arranged on the plane is recognized based on the voltage value or the resistance value of the resistance element.