JP2006118910A - Evaluation device for transistor, and evaluation method for transistor using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a characteristics evaluation circuit and an evaluation method for a transistor, capable of analyzing dispersions in the characteristics of the plurality of transistors. <P>SOLUTION: This characteristics evaluation device for the transistor has a plurality of unit circuits 10, including the transistor 1 of a measuring object with a gate connected to an output terminal of a two-input NAND circuit 2 via an inverter 3, with a drain connected to a column electric power source 11, and with a source connected to a row electric power source 12. The characteristics evaluation device has further an inverter as a voltage detector, wherein a column driver circuit 22 is connected to the row electric power source 12, wherein a row driver circuit 21 is connected to the column electric power source 11, and connected to the column electric power source 11, and an output terminal 24 for receiving an output signal OUTC from the each inverter 23. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a transistor evaluation apparatus used for evaluating characteristics of a transistor after completion of a semiconductor device manufacturing process and a transistor evaluation method using the same.

  A transistor used in a semiconductor device is one of important components, and is an important evaluation item not only during development of a semiconductor process but also during mass production of a semiconductor device. The characteristics of the manufactured transistor are as follows: TEG (Test Element Group), that is, a plurality of transistors to be measured arranged in a matrix form using a decoder for identifying the address of each transistor. One is selected and the current of the selected specific transistor is individually measured.

  Hereinafter, a conventional transistor characteristic evaluation apparatus will be described with reference to the drawings (for example, see Patent Document 1).

  FIG. 12 shows a circuit configuration of a conventional transistor characteristic evaluation apparatus. As shown in FIG. 12, a plurality of transistors to be measured 59 (NMOS transistors) to be measured are arranged in a matrix on a semiconductor wafer. The gate and drain of each transistor 59 to be measured are connected to DC power supply units 53 and 54 for transistor measurement via selection transistors 55 and 56, respectively. The source of each transistor under measurement 59 is connected to the GND terminal 60.

  On the semiconductor wafer, an X decoder 51 and a Y decoder 52, which are decoder circuits, are arranged in the periphery of the transistor 59 to be measured. The X decoder 51 and the Y decoder 52 are supplied with a pulse source (non-delayed). Are connected.

The operation of the transistor characteristic evaluation apparatus configured as described above will be described below. When the transistor to be measured is selected by the X decoder 51 and the Y decoder 52, the selection transistors 55 and 56 on the line connected to the selected transistor are selected one by one. As a result, the voltage from the DC power supply units 53 and 54 is applied only to the selected transistor under measurement 59, and the current of the selected transistor under measurement 59 is measured.
Japanese Patent No. 348869

  However, in the conventional transistor evaluation apparatus, first, when a predetermined potential is applied to the gates of the transistors 59 included in a specific column by the X decoder 51, the gates of all the transistors in the specific column. Since a predetermined potential is applied to the transistor, a failure factor other than the transistor to be measured may affect the measurement result. This problem cannot be ignored as the number of transistors under measurement increases.

  Second, with the increase in the number of elements in the semiconductor integrated circuit device, the size of the transistors is miniaturized and the number of transistors is also increasing. The number of transistors reaches 1 billion per chip. ing. In order to examine variation in transistor characteristics and distribution of characteristics among chips, wafers, and lots, it is necessary to measure as many as 1 million transistors to be measured per wafer. In this case, in the method of individually measuring the current value of a specific transistor with respect to the non-measured transistors arranged in a matrix as in the conventional example, the number of measured transistors per wafer is 1 million. Furthermore, since measurement of one transistor (application of voltage and measurement of current) requires 30 ms, the measurement time for one wafer is 8 hours or more.

  As described above, although the transistor characteristic evaluation apparatus according to the conventional example is suitable for evaluating a relatively small transistor to be measured, evaluation of a transistor to be measured integrated on a large scale is realistic. is not.

  The present invention solves the first problem and the second problem, makes it possible to reliably perform characteristic evaluation of a transistor under measurement integrated on a large scale, and to measure a circuit integrated on a large scale. An object is to enable evaluation of characteristics of a transistor in a short time.

  In order to achieve the above object, a first transistor characteristic evaluation apparatus according to the present invention has a gate connected to a signal line, one of a source and a drain connected to a first wiring, and the other connected to a second line. A transistor to be measured connected to the first wiring, a first circuit for connecting the first wiring to the power supply terminal or the ground terminal, and a second circuit for connecting the second wiring to the power supply terminal or the ground terminal. The first wiring is connected to the output terminal via a voltage detector.

  According to the characteristic evaluation apparatus for the first transistor, the first wiring is connected to the power supply terminal by the first circuit to charge the first wiring, and the gate of the transistor to be measured is set to a predetermined voltage. After the change, in a state where the second wiring is connected to the ground terminal by the second circuit, the charge accumulated in the first wiring is discharged via the transistor to be measured and the second wiring, The current characteristic of the transistor to be measured is determined based on the time until the output of the voltage detector is reversed due to the change in the potential of the first wiring due to the discharge of the charge accumulated in the first wiring. To evaluate. Accordingly, even if the transistors are miniaturized and integrated on a large scale, the characteristics of the transistor to be measured can be evaluated in a short time.

  In the first transistor characteristic evaluation apparatus, the first circuit is connected in series between a power supply terminal and a ground terminal, and has a connection node connected to the first wiring and a pair of different conductivity types. The second circuit is preferably composed of a pair of transistors that are connected in series between the power supply terminal and the ground terminal, and whose connection node is connected to the second wiring and have different conductivity types. . If it does in this way, the 1st circuit and the 2nd circuit can be constituted easily and certainly.

  The first transistor characteristic evaluation apparatus preferably further includes voltage applying means for applying a predetermined voltage to the gate of the transistor to be measured.

  Further, the first transistor characteristic evaluation apparatus is connected in series between a voltage application terminal for applying a predetermined voltage and a ground terminal, and its connection node is connected to the gate of the transistor to be measured. It is preferable to further include a circuit composed of a pair of transistors of different types.

  In this way, the first circuit connects the first wiring to the power supply terminal by the first circuit and charges the first wiring with the charge, and the gate of the transistor to be measured is changed to a predetermined voltage. Then, the second circuit discharges the charge accumulated in the first wiring via the transistor to be measured and the second wiring in a state where the second wiring is connected to the ground terminal by the second circuit. A third step for obtaining a time until the output of the voltage detector is inverted by a change in the potential of the first wiring due to the discharge of the charge accumulated in the first wiring, and While inputting a plurality of voltages different from each other within a predetermined voltage range to the gate of a certain transistor, the first to third steps are repeated, and the time until the output of the voltage detector is inverted is determined each time. Output of voltage detector Threshold voltage of the transistor to be measured from the time relationship until the reversal can be determined. As a result, even if the transistors are miniaturized and integrated on a large scale, the threshold voltage characteristics of the measurement target transistor can be evaluated in a short time.

  Each of the second transistor characteristic evaluation devices according to the present invention is arranged in a matrix, the gate is connected to the output terminal of the NAND circuit, and one of the source and the drain is connected to the first wiring. And a second wiring connected to a transistor included in a unit circuit belonging to the same row among the plurality of unit circuits, the second circuit including a plurality of unit circuits including a transistor to be measured connected to the second wiring. Is one row direction wiring, and one input terminal of the NAND circuit included in the unit circuit belonging to the same row is connected to the row address control unit, and the unit circuit belonging to the same column among the plurality of unit circuits The first wiring connected to the included transistor is a column-directional wiring, and the other input of the NAND circuit included in the unit circuit belonging to the same column Child is characterized in that it is connected to a column address control unit.

  According to the second transistor characteristic evaluation apparatus, it is possible to apply a potential only to the gate of the transistor included in the unit circuit having the NAND circuit selected by the row address control unit and the column address control unit. Since no potential is applied to the gate of the transistor included in the unit circuit, it is possible to prevent a failure factor other than the transistor to be measured from affecting the measurement result.

  The third transistor characteristic evaluation device according to the present invention is a transistor characteristic evaluation device, each of which is arranged in a matrix, the gate is connected to the output terminal of the NAND circuit, and one of the source and drain is A plurality of unit circuits including a plurality of transistors to be measured connected to a first wiring and the other connected to a second wiring, and the plurality of unit circuits included in a unit circuit belonging to the same row among the plurality of unit circuits; The second wiring connected to the transistor is a row-directional wiring, and a negative input terminal of the NAND circuit included in the unit circuit belonging to the same row is connected to a row address control unit, The first wirings connected to the plurality of transistors included in unit circuits belonging to the same column among the plurality of unit circuits are arranged in a column direction. , And the other input terminal of the NAND circuit included in the unit circuits belonging to the same column is characterized in that it is connected to a column address control unit.

  According to the third transistor characteristic evaluation apparatus, it is possible to apply a potential only to the gate of the transistor included in the unit circuit having the NAND circuit selected by the row address control unit and the column address control unit, When included in the circuit, no potential is applied to the gate of the transistor, so that a failure factor other than the transistor to be measured can be prevented from affecting the measurement result. In addition, the characteristics of a plurality of transistors included in each unit circuit can be performed simultaneously, and the measurement time can be further shortened.

  The second or third transistor characteristic evaluation apparatus is configured to connect a plurality of first circuits for connecting the first wiring to the power supply terminal or the ground terminal, and to connect the second wiring to the power supply terminal or the ground terminal. A plurality of second circuits, a column driver controller that outputs a control signal to each gate of a pair of transistors in the first circuit, and a control signal that is output to each gate of a pair of transistors in the second circuit It is preferable that each of the column direction wirings is connected to an output terminal via a voltage detector.

  In this case, a plurality of unit circuits including the transistors to be measured arranged in a matrix are individually selected, and the first circuit is connected to the power supply terminal by the first circuit to be connected to the first wiring. After charging the charge and changing the gate of the transistor to be measured to a predetermined voltage, the charge accumulated in the first wiring is connected to the ground terminal by the second circuit. The output of the voltage detector is inverted by a change in the potential of the first wiring caused by discharging through the transistor to be measured and the second wiring and discharging the charge accumulated in the first wiring. By performing the process of obtaining the time until each transistor included in each of the plurality of unit circuits, variation in current characteristics of the plurality of transistors can be determined. Even the static as integrated into miniaturized and large, the variation in characteristics of the measurement target transistor can be evaluated in a short time.

  In the device for evaluating characteristics of the second or third transistor, the first circuit is connected in series between the power supply terminal and the ground terminal, and its connection node is connected to each column direction wiring so that the conductivity types are different from each other. It consists of a pair of transistors, and the second circuit consists of a pair of transistors that are connected in series between a power supply terminal and a ground terminal, and whose connection node is connected to each row-direction wiring and that have different conductivity types. Is preferred. If it does in this way, the 1st circuit and the 2nd circuit can be constituted easily and certainly.

  In the device for evaluating characteristics of the second or third transistor, the second circuit is preferably connected to one terminal and another terminal of each row direction wiring.

  The second or third transistor characteristic evaluation apparatus preferably further includes a voltage applying unit that applies a predetermined voltage to the gate of the transistor to be measured.

  The second or third transistor characteristic evaluation apparatus is connected in series between a voltage application terminal for applying a predetermined voltage and a ground terminal, and its connection node is connected to the gate of the transistor to be measured. It is preferable to further include a circuit including a pair of transistors having different conductivity types.

  In this case, a plurality of unit circuits including the transistors to be measured arranged in a matrix are individually selected, and the first circuit is connected to the power supply terminal by the first circuit to be connected to the first wiring. In the first step of charging the charge, and after changing the gate of the transistor to be measured to a predetermined voltage, the second wiring is connected to the ground terminal by the second circuit. A second step of discharging the accumulated charge via the transistor to be measured and the second wiring; and a potential of the first wiring by discharging the charge accumulated in the first wiring. A third step of obtaining a time until the output of the voltage detector is inverted by a change, and a first to a third while inputting a plurality of voltages different from each other within a predetermined voltage range to a gate of a transistor to be measured Repeat the process Return, the time until the output of the voltage detector is inverted is obtained every time, and the process of obtaining the threshold voltage value of the transistor from the relationship between the time until the gate voltage and the output of the voltage detector are inverted is a plurality of unit circuits By performing for each of the transistors included in each of the transistors, variation in threshold voltage values of a plurality of transistors can be determined. As a result, even if the transistors are miniaturized and integrated on a large scale, variations in threshold voltage characteristics of the transistors to be measured can be evaluated in a short time.

  Preferably, the second or third transistor characteristic evaluation apparatus further includes an automatic oscillation circuit that outputs control signals to the row address control unit, the column address control unit, the row driver control unit, and the column driver control unit, respectively. . In this way, for example, in a burn-in test in a wafer state, it is possible to apply a stress current for accelerating and generating deterioration of transistor characteristics without inputting a control signal from the outside.

  Preferably, the second or third transistor characteristic evaluation device further includes at least one fuse element that allows a specific unit circuit to be selected and driven from among the plurality of unit circuits. In this way, the position of the defective transistor can be reliably identified from among the highly integrated transistors.

  In the first, second, or third transistor characteristic evaluation apparatus, the voltage detector is preferably an inverter or a differential amplifier. In this way, it is possible to reliably invert the output of the voltage detector with respect to a change in the potential of the first wiring due to the discharge of the charge accumulated in the first wiring.

  In order to achieve the above object, a first transistor characteristic evaluation method according to the present invention is directed to a transistor evaluation method using the first transistor characteristic evaluation apparatus of the present invention. The first wiring is connected to the power supply terminal by charging the first wiring, and the second wiring is connected to the second circuit after the gate of the transistor to be measured is changed to a predetermined voltage. And the step of discharging the charge accumulated in the first wiring through the transistor to be measured and the second wiring while being connected to the grounding terminal, and the charge accumulated in the first wiring is discharged. And a step of evaluating the current characteristics of the transistor to be measured based on the time until the output of the voltage detector is inverted due to the change in the potential of the first wiring. To.

  According to the characteristic evaluation method of the first transistor, the measurement time per transistor is the time for accumulating charges in the first wiring and the time for discharging through the transistor to be measured and the second wiring. Therefore, even if the transistors are miniaturized and integrated on a large scale, the characteristics of the transistor to be measured can be evaluated in a short time.

  The second transistor characteristic evaluation method according to the present invention is directed to a transistor evaluation method using the first transistor characteristic evaluation apparatus, and by connecting the first wiring to the power supply terminal by the first circuit. In the first step of charging the first wiring with the charge, and after changing the gate of the transistor to be measured to a predetermined voltage, the second wiring is connected to the ground terminal by the second circuit. A second step of discharging the charge accumulated in the first wiring via the transistor to be measured and the second wiring; and a first step by discharging the charge accumulated in the first wiring. A third step of obtaining a time until the output of the voltage detector is inverted due to a change in potential of the wiring of the wiring, and a plurality of voltages different from each other within a predetermined voltage range are not input to the gate of the transistor to be measured. From the first step to the third step, the time until the output of the voltage detector is inverted is obtained each time, and the gate voltage and the time until the output of the voltage detector are inverted. And a step of obtaining a threshold voltage value of a transistor to be measured from the relationship.

  According to the characteristic evaluation method of the second transistor, the measurement time of the threshold voltage value per transistor is the time during which charges are accumulated in the first wiring, the transistor to be measured, and the second wiring. Therefore, even if the transistors are miniaturized and integrated on a large scale, the threshold voltage characteristics of the transistors to be measured can be reduced in a short time. Can be evaluated.

  In order to achieve the above object, a third transistor characteristic evaluation method according to the present invention is directed to a transistor evaluation method using a second or third transistor characteristic evaluation apparatus, and is arranged in a matrix. A step of charging the first wiring by selecting a plurality of unit circuits including the transistor to be measured individually and connecting the first wiring to the power supply terminal by the first circuit; After the gate of a certain transistor is changed to a predetermined voltage, the charge accumulated in the first wiring is measured with the second wiring connected to the ground terminal by the second circuit and the second Until the output of the voltage detector is reversed due to the step of discharging via the first wiring and the change in the potential of the first wiring due to the discharge of the charge accumulated in the first wiring. By performing the transistors respectively included the step of determining a time to a plurality of unit circuits, and evaluating the variation in current characteristics of a plurality of transistors.

  According to the characteristic evaluation method of the third transistor, the measurement time of the transistor included in each unit circuit is the time during which charges are accumulated in the first wiring, the transistor to be measured, and the second wiring. Since it depends on the discharge time, the measurement time can be greatly shortened. Therefore, even if the transistors are miniaturized and integrated on a large scale, the characteristics of the transistor to be measured can be evaluated in a short time. Can do.

  To achieve the above object, a fourth transistor characteristic evaluation method according to the present invention is directed to a transistor evaluation method using a second or third transistor characteristic evaluation device, and is arranged in a matrix. A first step of individually charging a plurality of unit circuits including a transistor to be measured and connecting the first wiring to the power supply terminal by the first circuit to charge the first wiring; After changing the gate of the transistor to be measured to a predetermined voltage, the charge accumulated in the first wiring is measured while the second wiring is connected to the ground terminal by the second circuit. And the second step of discharging via the second wiring and the change in the potential of the first wiring due to the discharge of the charge accumulated in the first wiring, the output of the voltage detector The third step for obtaining the time until switching and the first step to the third step were sequentially repeated while inputting a plurality of voltages different from each other within a predetermined voltage range to the gate of the transistor to be measured. Thereafter, a process for obtaining the threshold voltage value of the transistor to be measured from the relationship between the gate voltage and the time until the output of the voltage detector is inverted is obtained every time the output until the output of the voltage detector is inverted is repeated. The variation of the threshold voltage values of the plurality of transistors is evaluated by performing for each of the transistors included in the plurality of unit circuits.

  According to the characteristic evaluation method of the fourth transistor, the measurement time of the threshold voltage value of the transistor included in each unit circuit is the time during which charges are accumulated in the first wiring, the transistor to be measured, and the second wiring. Therefore, even if the transistor is miniaturized and integrated on a large scale, the threshold voltage characteristics of the transistor to be measured can be reduced. It can be evaluated in a short time.

  According to the transistor characteristic evaluation apparatus and the transistor characteristic evaluation method of the present invention, even if the transistors are miniaturized and integrated on a large scale, the characteristics of the transistor under measurement can be reliably evaluated. In addition, the characteristics of the transistor under measurement integrated on a large scale can be evaluated in a short time.

(First embodiment)
A transistor characteristic evaluation apparatus according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a circuit configuration of a transistor characteristic evaluation apparatus according to a first embodiment of the present invention. As shown in FIG. 1, the transistor characteristic evaluation apparatus according to the first embodiment is a so-called TEG formed on a part of a semiconductor wafer made of, for example, silicon (Si), and the source is a column power line 11. A plurality of unit circuits 10 including the transistor 1 to be measured, which is an N-type MOSFET whose drain is connected to the row power supply line 12, are arranged in a matrix.

  In each unit circuit 10, the gate of the transistor 1 to be measured is connected to the output terminal of the 2-input NAND circuit 2 via the inverter 3. One input terminal of the 2-input NAND circuit 2 is connected to the column address signal line 13, and the other input terminal is connected to the row address signal line 14.

  Each column power line 11 is connected to each column pad 151, 152,..., 15n (where n is an integer of 1 or more), and each row pad 161, 162,... 16m (where m is 1 or more). Are connected to each other.

  Each column address signal line 13 is connected to a column address controller 17 that is a column address controller, and each row address signal line 14 is connected to a row address controller 18 that is a row address controller.

  Hereinafter, a transistor evaluation method incorporated in the transistor characteristic evaluation apparatus configured as described above will be described with reference to the drawings.

  2A shows an enlarged region 20 in FIG. 1, and FIG. 2B shows an operation timing of the evaluation apparatus. Here, as shown in FIG. 2A, a transistor characteristic evaluation method will be described for one of the plurality of unit circuits 10, for example, the unit circuit 10 located in the first row and the first column.

  First, as shown in FIG. 2B, the column pad 151 is applied with the control signal SWT having a high potential (“H” in the figure) applied to the gate of the transistor 1 to be measured and the row pad 161 grounded. A voltage of 0 V to 1.2 V is applied to. As a result, a current I flows from the drain to the source of the transistor 1. Here, the control signal SWT is generated by address signals from the column address controller 17 and the row address controller 18.

  Furthermore, in the first embodiment, by providing the column address controller 17 and the row address controller 18, any one of the plurality of unit circuits 10 arranged in a matrix can be selected. One of the transistors deviating from the distribution of variation can be identified.

  That is, it becomes possible to selectively apply a potential only to the gate of the transistor 1 included in the unit circuit 10 having the two-input NAND circuit 2 selected by the row address controller 18 and the column address controller 17, and other unit circuits. Since no potential is applied to the gate of the transistor 1 included in the transistor 10, it is possible to prevent a failure factor other than the transistor 1 to be measured from affecting the measurement result.

  As described above, according to the first embodiment, non-Ids characteristics and saturation current values are selectively selected for a plurality of unit circuits 10 like a memory arranged in a matrix for a group of transistors 1 to be measured. And can be evaluated. This makes it possible to evaluate transistors that have been miniaturized and integrated on a large scale in a realistic processing time. Therefore, it is necessary to reliably evaluate variations in transistor characteristics and distribution of characteristics within a chip, within a wafer, or between lots. Is possible.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 3 shows a circuit configuration of a unit circuit of the transistor characteristic evaluation apparatus according to the second embodiment of the present invention. In FIG. 3, the same components as those shown in FIG.

  The transistor characteristic evaluation apparatus according to the second embodiment adds a configuration that enables the characteristics of the transistor to be evaluated in a short time to the configuration of the first embodiment.

  As shown in FIG. 3, in the transistor characteristic evaluation apparatus according to the second embodiment, the output terminals are replaced with column power supplies instead of the column pads 15n (n = 1 to n) and the row pads 16m (m = 1 to m). A column driver circuit 21 as a first circuit connected to the line 11, a row driver circuit 22 as a second circuit whose output terminal is connected to the row power supply line 12, and a voltage connected to the column power supply line 11 It has an inverter 23 as a detector and an output terminal 24 that receives an output signal OUTC of the inverter 23. Here, the control signal SWT is an output signal from the inverter 3 included in the unit circuit 10.

  The column driver circuit 21 is connected in series between a power supply terminal and a ground terminal, and has a first PMOSFET 21a whose gate receives a first column drive signal CDP, and a first whose gate receives a second column drive signal CDN. NMOSFET 21b.

  The column driver circuit 22 is connected in series between a power supply terminal and a ground terminal, and has a second PMOSFET 22a whose gate receives the first row drive signal RDP, and a second whose gate receives the second row drive signal RDN. NMOSFET 22b.

  The first circuit and the second circuit are not limited to the circuit shown in the present embodiment as long as the column power line 11 and the row power line 12 can be switched to the power terminal or the ground terminal and connected. .

  Hereinafter, a transistor evaluation method incorporated in the transistor characteristic evaluation apparatus configured as described above will be described with reference to the drawings.

  First, as shown in FIG. 4A, a method for measuring a source-drain current will be described.

  The signal of the second column drive signal CDN is set to the low level (“L” in the drawing), and the signal potentials of the first row drive signal RDP and the second row drive signal RDN are both set to the high level (“H” in the drawing). ), And the signal potential of the control signal SWT is set to the high level. In this state, when the voltage of the first column drive signal CDP transitions from 0V to 1.2V, the current Is flows between the source and drain of the transistor 1 as shown in FIG. 1 PMOSFET 22 a, the transistor 1 to be measured, and the second NMOSFET 22 b of the row drive circuit 22.

  From the above, also in the second embodiment, it is possible to evaluate the current characteristics and saturation current value of the transistor 1 to be measured.

  Next, a method for evaluating current characteristics for a transistor in a very short time will be described.

  As shown in FIG. 4B, when the control signal SWT is at the low level (“L” in the figure), the potentials of the first column drive signal CDP and the second column drive signal CDN are both set to the low level. When the potentials of the first row drive signal RDP and the second row drive signal RDN are both at a high level ("H" in the figure), the column driver circuit 21 passes through the first PMOSFET 21a from the power supply terminal of the column driver circuit 21. Charges are charged in the column power supply line 11 connected to the node NC1 which is the output terminal 21. As a result, the potential of the node NC1 becomes high level.

  Subsequently, after the potential of the node NC1 becomes high level, the potential of the first column drive signal CDP is changed to high level, so that the node NC1 becomes a high impedance state. In this high impedance state, the potential of the output signal OUTC at the output terminal 24 is at a low level.

Next, by changing the potential of the control signal SWT to a high level, the charge stored in the column power supply line 11 flows to the ground terminal through the transistor 1 and the second NMOSFET 22b of the row driver circuit 22. At this time, the rate of potential drop at the node NC1 varies depending on the degree of charge outflow, that is, the current driving capability of the transistor 1. More specifically, when the threshold voltage value (Vt) of the transistor 1 is relatively high, that is, when the saturation current value is relatively low, the potential drop rate is small, and conversely, the threshold voltage value of the transistor 1 Is relatively low, that is, when the saturation current value is relatively high, the potential drop rate is large. For example, as shown in FIG. 3, when Tr.0 having a low threshold voltage value and Tr.1 having a high threshold voltage value are evaluated by this method as shown in FIG. 3, as shown in FIG. Tr.1 having a higher value has a lower potential drop rate at the node NC1 than Tr.0 having a lower threshold voltage value. After that, when the potential of the node NC1 drops to half of the high level potential (the level of the one-dot chain line in the drawing), the potential of the output signal OUTC becomes high level by the inversion operation of the inverter 23. Subsequently, delay times t ₀ and t ₁ from the time when the potential of the control signal SWT changes to the high level to the time when the potential of the output signal OUTC changes to the high level are converted into saturation current values. In the figure, Tr. The delay time for ₀ corresponds to t ₀ and the delay time for Tr.1 corresponds to t ₁ . The inventor of the present application has found that the relationship between the saturation current value of the transistor 1 and the delay time is obtained by setting the power supply voltage to 1.2 V and corresponds to the following relational expression (1).

Saturation current value (mA) × {100 × delay time (ns) −about 2000} ≈1 (1)
Therefore, when the saturation current value of the transistor 1 is 1 mA, the measurement time corresponds to about 20 ns. Therefore, when measurement is performed using the timing chart as shown in FIG. 4B, the measurement time of one transistor 1 can be at most 1 μs or less. Here, the inverter 23 that is a voltage detector may be replaced with a differential amplifier that uses a half potential of the high-level potential as a reference potential.

  FIG. 5 shows an example in which the configuration of the transistor characteristic evaluation apparatus according to the second embodiment of the present invention is arranged in a matrix and integrated on a large scale. In FIG. 5, the same components as those shown in FIG.

  As shown in FIG. 5, the input terminal of each column driver circuit 21 is connected to a column driver controller 25. That is, the gate of the first PMOSFET 21 a receives the first column drive signal CDP from the column driver controller 25, and the gate of the first NMOSFET 21 b receives the second column drive signal CDN from the column driver controller 25.

  The input terminal of each row driver circuit 22 is connected to the row driver controller 26. That is, the gate of the second PMOSFET 22 a receives the first row drive signal RDP from the row driver controller 26, and the gate of the second NMOSFET 22 b receives the second row drive signal RDN from the row driver controller 26.

  The gate of each transistor 1 is connected to the output terminal of the 2-input NAND circuit 2 via the inverter 3. One input terminal of the 2-input NAND circuit 2 is connected to the column address signal line 13, and the other input terminal is connected to the row address signal line 14. Each column address signal line 13 is connected to a column address controller 17, and each row address signal line 14 is connected to a row address controller 18. Here, the gate potential of each transistor 1 is controlled by the column address controller 17 and the row address controller 18 corresponding to the control signal SWT in FIG.

  The operation and evaluation method of each unit circuit 10 is as described above, and each column power supply line 11 and each row circuit are controlled by control signals from the column address controller 17, column driver controller 25, row address controller 18 and row driver controller 26. The power supply line 12 is selectively controlled. Thereby, since the current Is can be arbitrarily applied to the plurality of unit circuits 10, the characteristics of the transistors in each unit circuit 10 can be measured as the delay time.

  With the above-described configuration, conventionally, the measurement time for one transistor takes about 30 ms to measure the current value using an ammeter, so 8 hours are required to measure the characteristics of one million transistors. I need it. According to the present invention, since one transistor can be measured in 1 μs, the characteristics of one million transistors can be measured in 1 s.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.
FIG. 6 shows a circuit configuration of a unit circuit of the transistor characteristic evaluation apparatus according to the third embodiment of the present invention. In FIG. 6, the same components as those shown in FIG.

  The transistor characteristic evaluation apparatus according to the third embodiment adds a configuration that enables evaluation of variations in threshold voltage values in a short time to the configuration of the second embodiment.

  As shown in FIG. 6A, instead of the control signal SWT, a control signal pad 191 capable of applying an arbitrary voltage to the gate of the transistor 1 included in the unit circuit 10 is provided. FIG. 6B shows another example of the configuration of the transistor characteristic evaluation apparatus according to the third embodiment. For example, in FIG. 6B, the gate voltage control circuit 27 whose output terminal is connected to the gate of the transistor 1 corresponds to the control signal pad 191 in FIG. The gate voltage control circuit 27 is connected in series between a power supply terminal to which an arbitrary voltage can be applied and a ground terminal, and has a PMOSFET 27a and an NMOSFET 27b whose gates receive the output signal of the two-input NAND circuit 2 included in the unit circuit 10. It consists of and. Therefore, the gate voltage control circuit 27 can change the potential of the output terminal by changing the potential of the power supply terminal.

  Hereinafter, a transistor evaluation method incorporated in the transistor characteristic evaluation apparatus configured as described above will be described with reference to the drawings.

  As shown in FIG. 7, the potentials of the first column drive signal CDP and the second column drive signal CDN are set while the potential of the output terminal of the gate voltage control circuit 27 is at a low level (“L” in the figure). When both are set to the low level and the potentials of the first row drive signal RDP and the second row drive signal RDN are both set to the high level (“H” in the drawing), the power supply terminal of the column driver circuit 21 passes through the first PMOSFET 21a. As a result, the column power supply line 11 connected to the node NC1 which is the output terminal of the column driver circuit 21 is charged, and as a result, the potential of the node NC1 becomes high level as in the second embodiment. Subsequently, as in the second embodiment, after the potential of the node NC1 becomes high level, the potential of the first column drive signal CDP is changed to high level, so that the node NC1 becomes in a high impedance state. .

Next, by changing the potential level of the output terminal of the gate voltage control circuit 2 to the potential level V1 of an arbitrary output terminal, the charge stored in the column power supply line 11 is changed to the first level of the transistor 1 and the row driver circuit 22. Flows to the ground terminal through the second NMOSFET 22b. At this time, the rate of potential drop at the node NC1 varies depending on the output potential level of the gate voltage control circuit 27. More specifically, when the potential at the output terminal of the gate voltage control circuit 27 is relatively high, the potential drop rate is large, and conversely, the potential at the output terminal of the gate voltage control circuit 27 is relatively high. When it is low, the rate of potential drop is small. After that, when the potential of the node NC1 drops to half of the high level potential (the level of the one-dot chain line in the figure), the potential of the output signal OUTC becomes high level by the inversion operation of the inverter 23. Furthermore, when the potential of the output terminal of the gate voltage control circuit 27 becomes equal to or lower than the threshold potential of the transistor 1 to be measured, the rate of drop is significantly reduced. For example, as shown in FIG. 6B, the threshold voltage value of the transistor 1 is V _x−1 , and the potential of the power supply terminal of the gate voltage control circuit 27 is V ₁ to V _x (where V ₁ > V ₂ >...> V _x-1 > V _x ) If the threshold voltage value of the transistor 1 is a voltage between V _x-1 and V _x , as shown in FIG. In addition, the drop rate of the potential at the node NC1 is significantly reduced when it changes from V _{x -1} to V _x .

Therefore, from the time when the potential of the control signal SWT is changed to the high level with respect to each potential (V ₁ , V ₂ ,..., V _x−1 , V _x ) of the power supply terminal of the gate voltage control circuit 27. The threshold voltage value of the transistor 1 is determined by measuring each delay time (t ₁ , t ₂ ,..., T _x−1 , t _x ) until the potential of the output signal OUTC changes to the high level. It is possible to estimate.

  As described above, when the transistor characteristic evaluation apparatus according to the third embodiment is arranged in a matrix and integrated on a large scale as shown in FIG. For example, a gate voltage control circuit 27 may be provided as a voltage applying means for applying a predetermined voltage to the gate.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

  FIG. 8 shows a circuit configuration of a transistor characteristic evaluation apparatus according to the fourth embodiment of the present invention. In FIG. 8, the same components as those shown in FIG.

  The transistor characteristic evaluation apparatus according to the fourth embodiment is similar to the transistor characteristic evaluation apparatus according to the second embodiment in that the characteristic evaluation of the transistor 1 that is a measurement target included in each unit circuit 10 is the same row power line. The structure which can be performed with the resistance value in 12 is added.

  Specifically, as illustrated in FIG. 8, the transistor characteristic evaluation apparatus according to the fourth embodiment includes a plurality of row driver circuits 22 connected to both ends of each row power supply line 12. An input terminal of each row driver circuit 22 is connected to a row driver controller 26.

  With such a configuration, even when any unit circuit 10 arranged in a matrix is selected, the row power lines 12 have the same wiring length, and therefore the resistance values of the row power lines 12 are also the same. Therefore, the resistance value of the current path from the transistor 1 to be measured can be made the same value, and the cause of characteristic variation due to circuits other than the transistor 1 to be measured can be eliminated.

(Fifth embodiment)
Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings.

  FIG. 9 shows a circuit configuration of a transistor characteristic evaluation apparatus according to the fifth embodiment of the present invention. In FIG. 9, the same components as those shown in FIG.

  The transistor characteristic evaluation apparatus according to the fifth embodiment adds a configuration capable of applying a stress current to the configuration of the second embodiment by an internal signal generated inside the apparatus.

  Specifically, as shown in FIG. 9, the transistor characteristic evaluation apparatus according to the fifth embodiment is connected to the column address controller 17, the row address controller 18, the column driver controller 25, and the row driver controller 26, respectively. An excitation oscillation circuit 28 is provided.

  With such a configuration, for example, in a burn-in test performed in a wafer state, it is possible to apply a stress current for accelerating and generating deterioration of transistor characteristics without inputting a control signal from the outside.

(Sixth embodiment)
Hereinafter, a sixth embodiment of the present invention will be described with reference to the drawings.

  FIG. 10 shows a circuit configuration of a transistor characteristic evaluation apparatus according to the sixth embodiment of the present invention. In FIG. 10, the same components as those shown in FIG.

  The transistor characteristic evaluation apparatus according to the sixth embodiment adds a configuration that facilitates physical analysis by providing a fuse element to the configuration of the second embodiment.

Specifically, as illustrated in FIG. 10, the transistor characteristic evaluation apparatus according to the sixth embodiment includes a column address controller 17, a row address controller 18, a column driver controller 25, a row driver controller 26, and each unit circuit 10. A plurality of fuse elements 29a that uniquely determine connection to the. Here, the number of fuse elements 29a is, for example, m + n when the unit circuit 10 has 2 ^m rows and 2 ⁿ columns. However, m and n are integers of m = n.

  A fixed control signal pattern is input to each of the controllers 17, 18, 25, and 26 depending on the combination of the cut portions of the plurality of fuse elements 29 a. Thereby, only by applying a potential to the two terminals of the voltage terminal and the ground terminal, an evaluation current flows only in the specific unit circuit 10. As a result, since evaluation of a specific transistor can be performed with a small number of terminals, evaluation using a semiconductor parameter analyzer or the like is possible.

  As described above, according to the sixth embodiment, it is possible to reliably identify the position of the defective transistor from among the transistors in which hundreds of millions are provided per wafer.

(Seventh embodiment)
The seventh embodiment of the present invention will be described below with reference to the drawings.

  FIG. 11 shows a circuit configuration of a transistor characteristic evaluation apparatus according to the seventh embodiment of the present invention. In FIG. 11, the same components as those shown in FIG.

  The transistor characteristic evaluation apparatus according to the seventh embodiment has a configuration in which multiple transistors to be measured can be selected.

  As shown in FIG. 11, for example, the unit circuit 10A in the first row and the first column (the lower left end in the figure) includes two column power supply lines 11 (1) and 11 (2) and one row power supply line. 12 (1). Similarly, the unit circuit 10A of the i-th row and j-th column (i is an integer from 1 to m, j is an integer from 1 to n) has two column power supply lines 11 (2i-1). , 11 (2i) and one row power supply line 12 (j).

  For example, for the unit circuit 10A in the first row and the first column (the lower left end in the figure), the sources of the two transistors 1a and 1c are connected in parallel to the column power line 11 (1), and each drain is The row power supply line 12 (1) is connected in parallel. Further, the source of the two transistors 1b and 1d is connected in parallel to the column power supply line 11 (2), and each drain is connected in parallel to the row power supply line 12 (1). The gates of the transistors 1a and 1b adjacent along the row power supply line 12 (1) are connected to the 2-input NAND circuit 2a through the inverter 3a. The gates of the transistors 1c and 1d adjacent along the row power supply line 12 (1) are connected to the 2-input NAND circuit 2b via the inverter 3b. One input terminal of the 2-input NAND circuit 2a is connected to the column address signal line 13 (1), and the other input terminal is connected to the row address signal line 14 (1). One input terminal of the 2-input NAND circuit 2b is connected to the column address signal line 13 (1), and the other input terminal is connected to the row address signal line 14 (2).

  Accordingly, one unit circuit 10A includes four transistors 1a, 1b, 1c, and 1d, two two-input NAND circuits 2a and 2b, and inverters 3a and 3b. Unit circuit 10A is arranged in m rows and n columns.

  Hereinafter, a transistor evaluation method incorporated in the transistor characteristic evaluation apparatus configured as described above will be described with reference to the drawings.

  Here, a method of measuring current characteristics for the unit circuit 10A in the first row and the first column will be described.

  First, in the state where the gate potential of the transistors 1a, 1b, 1c, and 1d included in the unit circuit 10A in the first row and the first column is set to the low level, the row driver controller 26 and the unit circuit 10A arranged in the first row In the connected column driver circuit 22, the potential of the first row drive signal RDP and the potential of the second row drive signal RDN are both set to the high level, the second PMOSFET 22a is turned off, and the second NMOSFET 22b is turned on. And

  Next, the column driver controller 25 determines the potentials of the first column driver signals CDP (A) and CDP (B) in the two column driver circuits 21A and 21B connected to the unit circuit 10A arranged in the first column. The second row drive signals CDN (A) and CDN (B) are set to a low level, both the first PMOSFET 21a (A) and PMOSFET 21a (B) are turned on, and the first NMOSFET 21b (A) and NMOSFET 21b (B) Are turned off. As a result, the column power supply lines 11 (1) and 11 (2) are charged to a high level potential.

  Next, the column power supply lines 11 (1) and 11 (2) are set to the high level potential by returning both the first PMOSFET 21a (A) and the PMOSFET 21a (B) which are turned on to the off state. When in a charged state, it is in an electrically floating state.

  Next, only the two transistors 1a and 1b to be measured connected to the column power supply lines 11 (1) and 11 (2) and the row power supply line 12 (1) are selectively turned on. This is realized by setting the row address signal line 14 (1) to the high level by the row address controller 18 and setting the column address signal line 13 (1) to the high level by the column address controller 17. As a result, the charges charged in the column power supply lines 11 (1) and 11 (2) flow to the ground terminal through the transistors 1a and 1b, the row power supply line 12 (1), and the second NMOSFET 22b, respectively. After that, when each potential of the column power supply lines 11 (1) and 11 (2) is lowered to half of the power supply potential, inverters connected to the column power supply lines 11 (1) and 11 (2), respectively. The potential of each output signal OUTC is inverted from the low level to the high level by 23A and 23B, and is output from the output terminals 24A and 24B, respectively.

  Therefore, the current characteristics of the two transistors 1a and 1b as the measurement objects are simultaneously measured by monitoring the time from when the transistors 1a and 1b as the measurement objects are turned on until the inverters 23A and 23B are inverted. be able to.

  Similarly, for the transistors 1c and 1d included in the unit circuit 10A in the first row and the first column, the row address signal line 14 (2) is set to high level by the row address controller 18, and the column address signal line 13 is set by the column address controller 17. Evaluation can be performed by setting (1) to a high level and selectively turning on only the transistors 1c and 1d.

  As described above, according to the sixth embodiment, by accessing one unit circuit 10B, the current characteristics of two transistors 1a and 1b or transistors 1c and 1d can be measured simultaneously. Therefore, the evaluation time can be reduced by half.

  Here, the two transistors 1a and 1b or the transistors 1c and 1d are connected to the control signal line for controlling the gate of the transistor. However, the number may be three or more, and the number is not limited.

  The present invention has an effect that characteristics of a transistor to be measured in an integrated circuit in which transistors are miniaturized and integrated on a large scale can be evaluated reliably and in a short time. It is effective as a transistor evaluation apparatus and evaluation method used for transistor characteristic evaluation in

1 is a circuit diagram showing a transistor characteristic evaluation apparatus according to a first embodiment of the present invention. FIG. 2A is a circuit diagram schematically showing a unit circuit constituting a transistor characteristic evaluation apparatus according to a first embodiment of the present invention and a current flowing through the unit circuit. (B) is a timing chart for evaluating the characteristics of the transistors included in the unit circuit of (a). 5 is a circuit diagram schematically showing a unit circuit constituting a transistor characteristic evaluation apparatus according to a second embodiment of the present invention and a current flowing through the unit circuit. FIG. (A) It is a timing diagram which evaluates the characteristic of the transistor contained in the unit circuit which comprises the characteristic evaluation apparatus of the transistor which concerns on the 2nd Embodiment of this invention. (B) is a timing chart in which the characteristics of the transistors included in the unit circuit of (a) are individually selected and evaluated from the voltage-current characteristics. It is a circuit diagram which shows the characteristic evaluation apparatus of the transistor arrange | positioned at the matrix form which concerns on the 2nd Embodiment of this invention. (A) And (b) is a typical circuit which shows the unit circuit of the transistor characteristic evaluation apparatus which concerns on the 3rd Embodiment of this invention. It is a timing diagram which evaluates the threshold voltage characteristic of the transistor contained in the unit circuit which comprises the transistor characteristic evaluation apparatus which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows the characteristic evaluation apparatus of the transistor which concerns on the 4th Embodiment of this invention. It is a circuit diagram which shows the characteristic evaluation apparatus of the transistor which concerns on the 5th Embodiment of this invention. It is a circuit diagram which shows the characteristic evaluation apparatus of the transistor which concerns on the 6th Embodiment of this invention. It is a circuit diagram which shows the characteristic evaluation apparatus of the transistor which concerns on the 7th Embodiment of this invention. It is a typical circuit diagram which shows the transistor characteristic evaluation apparatus which concerns on a prior art example.

Explanation of symbols

1, 1a, 1b, 1c, 1d Measurement target transistor 2, 2a, 2b 2-input NAND circuit 3, 3a, 3b Inverter 10 Unit circuit 10A Unit circuit 11 Column power supply line (column direction wiring)
11 (1) to 11 (2n) Column power supply line 12 Row power supply line (row direction wiring)
12 (1) to 12 (m) Row power supply line 13 Column address signal line 13 (1) to 13 (n) Column address signal line 14 Row address signal line 14 (1) to 14 (2 m) Row address signal line 15 Column Pad 151 Column pad 15m Column pad 16 Row pad 161 Row pad 16m Row pad 17 Column address controller (column address control unit)
18 Row address controller (row address controller)
191 Gate input terminal pads 21, 21A, 21B Column driver circuit (first circuit)
21a, 21a (A), 21a (B) First PMOSFET
21b, 21b (A), 21b (B) First NMOSFET
22 Row driver circuit (second circuit)
22a Second PMOSFET
22b Second NMOSFET
23, 23A, 23B (first) inverter (first voltage detector)
24, 24A, 24B (first) output terminal 25 column driver controller (column driver controller)
26 Row Driver Controller (Row Driver Control Unit)
27 Gate Voltage Control Circuit 27a PMOSFET
27b NMOSFET
28 Self-excited oscillation circuit 29 Fuse circuit 29a Fuse element

Claims (19)

A device characteristic evaluation apparatus,
A transistor that is a measurement target, in which a gate is connected to a signal line, and one of a source and a drain is connected to a first wiring and the other is connected to a second wiring;
A first circuit for connecting the first wiring to a power supply terminal or a ground terminal;
A second circuit for connecting the second wiring to a power supply terminal or a ground terminal,
The device for evaluating characteristics of a transistor, wherein the first wiring is connected to an output terminal via a voltage detector. The first circuit includes a pair of transistors connected in series between a power supply terminal and a ground terminal and having a connection node connected to the first wiring and having different conductivity types,
The second circuit includes a pair of transistors connected in series between a power supply terminal and a ground terminal and having a connection node connected to the second wiring and having different conductivity types. The transistor characteristic evaluation apparatus according to claim 1.   3. The transistor characteristic evaluation apparatus according to claim 1, further comprising voltage applying means for applying a predetermined voltage to a gate of the transistor to be measured.   A circuit composed of a pair of transistors that are connected in series between a voltage application terminal for applying a predetermined voltage and a ground terminal, and whose connection node is connected to the gate of the transistor to be measured, and having different conductivity types The transistor characteristic evaluation apparatus according to claim 1, further comprising: A device characteristic evaluation apparatus,
Each is arranged in a matrix, the gate is connected to the output terminal of the NAND circuit, and one of the source and drain is connected to the first wiring and the other is connected to the second wiring. A plurality of unit circuits including a transistor are provided.
The second wiring connected to the transistor included in a unit circuit belonging to the same row among the plurality of unit circuits is one row-directional wiring,
One input terminal of the NAND circuit included in the unit circuit belonging to the same row is connected to a row address control unit,
The first wiring connected to the transistors included in the unit circuits belonging to the same column among the plurality of unit circuits is a column-direction wiring;
The other input terminal of the NAND circuit included in the unit circuit belonging to the same column is connected to a column address control unit. A device for evaluating transistor characteristics, each arranged in a matrix, having a gate connected to an output terminal of a NAND circuit, one of a source and a drain connected to a first wiring, and the other connected to a second wiring A plurality of unit circuits including a plurality of transistors to be measured connected,
The second wiring connected to the plurality of transistors under measurement included in a unit circuit belonging to the same row among the plurality of unit circuits is one row-direction wiring,
The negative input terminal of the NAND circuit included in the unit circuit belonging to the same row is connected to a row address control unit,
Each of the first wirings connected to the plurality of transistors included in a unit circuit belonging to the same column among the plurality of unit circuits is a column direction wiring;
The other input terminal of the NAND circuit included in the unit circuit belonging to the same column is connected to a column address control unit. A plurality of first circuits for connecting the first wiring to a power supply terminal or a ground terminal;
A plurality of second circuits for connecting the second wiring to a power supply terminal or a ground terminal;
A column driver controller that outputs a control signal to each gate of a pair of transistors included in the first circuit;
A row driver controller that outputs a control signal to each gate of a pair of transistors included in the second circuit;
7. The transistor characteristic evaluation apparatus according to claim 5, wherein each of the column-direction wirings is connected to an output terminal via a voltage detector. The first circuit includes a pair of transistors that are connected in series between a power supply terminal and a ground terminal and whose connection nodes are connected to the column-direction wirings and have different conductivity types.
The second circuit includes a pair of transistors that are connected in series between a power supply terminal and a ground terminal, and whose connection nodes are connected to the row-direction wirings and have different conductivity types. Item 8. The transistor characteristic evaluation apparatus according to Item 7.   9. The transistor characteristic evaluation apparatus according to claim 7, wherein the second circuit is connected to one terminal and another terminal of each row direction wiring.   The transistor characteristic evaluation apparatus according to claim 7, further comprising a voltage applying unit that applies a predetermined voltage to a gate of the transistor to be measured.   A circuit composed of a pair of transistors that are connected in series between a voltage application terminal for applying a predetermined voltage and a ground terminal, and whose connection node is connected to the gate of the transistor to be measured, and having different conductivity types. The transistor characteristic evaluation apparatus according to claim 7, further comprising:   The automatic oscillation circuit that outputs control signals to the row address control unit, the column address control unit, the row driver control unit, and the column driver control unit, respectively, is further provided. The transistor characteristic evaluation apparatus described in 1.   12. The transistor according to claim 5, further comprising at least one fuse element capable of selecting and driving a specific unit circuit among the plurality of unit circuits. Characteristic evaluation device.   3. The transistor characteristic evaluation apparatus according to claim 1, wherein the voltage detector is an inverter or a differential amplifier.   8. The transistor characteristic evaluation apparatus according to claim 7, wherein the voltage detector is an inverter or a differential amplifier. A transistor evaluation method using the transistor characteristic evaluation device according to claim 1 or 2,
Charging the first wiring by connecting the first wiring to a power supply terminal by the first circuit;
After changing the gate of the transistor to be measured to a predetermined voltage, the charge accumulated in the first wiring is measured in a state where the second wiring is connected to the ground terminal by the second circuit. Discharging through the target transistor and the second wiring;
Based on the time until the output of the voltage detector is inverted due to a change in the potential of the first wiring due to the discharge of the charge accumulated in the first wiring, the current of the transistor to be measured And a step of evaluating characteristics. A transistor evaluation method comprising: A transistor evaluation method using the transistor characteristic evaluation apparatus according to claim 3 or 4,
A first step of charging the first wiring by connecting the first wiring to a power supply terminal by the first circuit;
After changing the gate of the transistor to be measured to a predetermined voltage, the charge accumulated in the first wiring is measured in a state where the second wiring is connected to the ground terminal by the second circuit. A second step of discharging through the target transistor and the second wiring;
A third step of obtaining a time until the output of the voltage detector is inverted by a change in the potential of the first wiring due to the discharge of the charge accumulated in the first wiring;
The output of the voltage detector is inverted after sequentially repeating the first step to the third step while inputting a plurality of voltages different from each other within a predetermined voltage range to the gate of the transistor to be measured. And calculating the threshold voltage value of the transistor to be measured from the relationship between the gate voltage and the time until the output of the voltage detector is inverted. A characteristic transistor evaluation method. A transistor evaluation method using the transistor characteristic evaluation device according to claim 5, wherein a plurality of unit circuits including the transistors to be measured arranged in a matrix are individually provided. Selected,
Charging the first wiring by connecting the first wiring to a power supply terminal by the first circuit;
After changing the gate of the transistor to be measured to a predetermined voltage, the charge accumulated in the first wiring is measured in a state where the second wiring is connected to the ground terminal by the second circuit. Discharging through the target transistor and the second wiring;
Each of the plurality of unit circuits includes a step of obtaining a time until the output of the voltage detector is inverted due to a change in the potential of the first wiring due to the discharge of the charge accumulated in the first wiring. The transistor evaluation method is characterized in that a variation in current characteristics of the plurality of transistors is evaluated by performing on the transistor. A transistor evaluation method using the transistor characteristic evaluation apparatus according to claim 10 or 11, wherein a plurality of unit circuits including the transistors to be measured arranged in a matrix are individually selected,
A first step of charging the first wiring by connecting the first wiring to a power supply terminal by the first circuit;
After changing the gate of the transistor to be measured to a predetermined voltage, the charge accumulated in the first wiring is measured in a state where the second wiring is connected to the ground terminal by the second circuit. A second step of discharging through the target transistor and the second wiring;
A third step of obtaining a time until the output of the voltage detector is inverted by a change in the potential of the first wiring due to the discharge of the charge accumulated in the first wiring;
The output of the voltage detector is inverted after sequentially repeating the first step to the third step while inputting a plurality of voltages different from each other within a predetermined voltage range to the gate of the transistor to be measured. Obtaining the threshold voltage value of the transistor to be measured from the relationship between the gate voltage and the time until the output of the voltage detector is inverted, for each of the unit circuits. A method for evaluating a transistor, characterized by evaluating variations in threshold voltage values of the plurality of transistors by performing each of the transistors included therein.

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