CN114264930A - Chip screening test method - Google Patents
Chip screening test method Download PDFInfo
- Publication number
- CN114264930A CN114264930A CN202111523044.9A CN202111523044A CN114264930A CN 114264930 A CN114264930 A CN 114264930A CN 202111523044 A CN202111523044 A CN 202111523044A CN 114264930 A CN114264930 A CN 114264930A
- Authority
- CN
- China
- Prior art keywords
- tested
- parameter
- test
- chip
- parameters
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012216 screening Methods 0.000 title claims abstract description 38
- 238000010998 test method Methods 0.000 title description 8
- 238000012360 testing method Methods 0.000 claims abstract description 196
- 238000000034 method Methods 0.000 claims abstract description 51
- 238000012545 processing Methods 0.000 claims abstract description 10
- 230000002950 deficient Effects 0.000 description 8
- 101100283411 Arabidopsis thaliana GMII gene Proteins 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 239000013256 coordination polymer Substances 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 101000730643 Homo sapiens Zinc finger protein PLAGL1 Proteins 0.000 description 3
- 102100032570 Zinc finger protein PLAGL1 Human genes 0.000 description 3
- 101150049912 bin3 gene Proteins 0.000 description 3
- 208000032005 Spinocerebellar ataxia with axonal neuropathy type 2 Diseases 0.000 description 2
- 208000033361 autosomal recessive with axonal neuropathy 2 spinocerebellar ataxia Diseases 0.000 description 2
- 238000007619 statistical method Methods 0.000 description 2
- 101000999373 Homo sapiens Interferon-related developmental regulator 2 Proteins 0.000 description 1
- 102100036480 Interferon-related developmental regulator 2 Human genes 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000011990 functional testing Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000012950 reanalysis Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012956 testing procedure Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Abstract
The invention provides a method for chip screening test, which comprises the following steps: establishing an intelligent learning model for chip testing; classifying the parameters to be tested of each chip, and arranging the parameters to be tested in sequence according to classification numbers; and sequentially testing the parameters to be tested according to the arranged sequence, processing the test result by using an intelligent learning model, predicting the failure probability of each parameter to be tested, and lifting the classification number of the parameter to be tested with the highest probability to the front of the arranged sequence so as to test the parameter to be tested with the highest probability preferentially. According to the invention, the failure rate of the parameters to be tested is output by processing the test result of the currently tested parameters to be tested through the intelligent learning model, the test parameters with high failure rate are referred to the front, and the test is carried out preferentially in the later test process, so that the test time of the chip can be reduced, and the test efficiency of the chip can be improved.
Description
Technical Field
The invention relates to the field of chip testing, in particular to a chip screening test method.
Background
In order to comprehensively detect whether various performances of the chip meet expected indexes, the screening process of the chip, whether CP test or FT test, is composed of a plurality of flows, each flow needs to carry out a plurality of project tests, some specific chip tests possibly need to be inserted in the carrying process of each flow, the problem possibly occurring in the actual use of the chip is covered as much as possible, and defective products are screened and removed in the testing process.
The existing chip test mainly comprises a screening process, wherein the CP test is to test each chip of the entire Wafer, test items include but are not limited to various basic electrical parameters and chip application functions, multi-temperature state screening can be carried out under general conditions, and the CP test can be carried out only when a normal pass is used for packaging. And performing FT test after packaging, wherein FT test screening processes are generally multiple, a chip needs to be subjected to some tests in the process, such as aging tests, whether the electrical characteristics of the packaged chip reach the standard or not is tested by observing the packaged chip placed in various environments, and whether the performances of related test items are stable and qualified or not is repeatedly verified. When the chip is tested, the flow and the scheme of the test screening are determined and are embodied on the program, namely the test parameters and the test items in the test program are fixed, each parameter index is tested in sequence according to the setting in the solidification program until a certain test item fails, the failure data is stored, and the current failure item Bin number is recorded. Generally, in the chip screening test process, it is not required to complete all test items for reanalysis, when one of the test items fails, it can be marked as a defective product, so that if one test item fails, the test of the current chip is suspended and marked as fail, and when screening, unless there is a special requirement, the side point of general screening is to eliminate the defective product, if data is concerned, for the failed chip, the specific data of the failed test item is concerned, and the data of the passed test item in the incomplete test flow result retained by the failed chip is not used for detailed analysis.
However, in the testing process of the prior art, a great number of testing parameters may be tested, and if a certain testing parameter has a high failure rate in a batch of products, the testing parameter is tested later, which results in a great amount of time waste and reduces the testing efficiency.
Disclosure of Invention
The invention aims to provide a chip screening test method which can test parameters with larger failure rate preferentially, thereby reducing the test time and improving the test efficiency.
In order to achieve the above object, the present invention provides a method for chip screening test, comprising:
establishing an intelligent learning model for chip testing;
classifying the parameters to be tested of each chip, and arranging the parameters to be tested in sequence according to classification numbers;
and sequentially testing the parameters to be tested according to the arranged sequence, processing the test result by using an intelligent learning model, predicting the failure probability of each parameter to be tested, and lifting the classification number of the parameter to be tested with the highest probability to the front of the arranged sequence so as to test the parameter to be tested with the highest probability preferentially.
Optionally, in the method for chip screening test, the test result includes: and testing whether the product, the testing process, the testing batch, the chip number, the coordinate, the ChipID and the testing parameter are invalid or not.
Optionally, in the method for screening and testing chips, the parameters to be tested of the chips are tested at intervals of a set time according to a sequence in which the classification number of the parameter to be tested with the highest probability is referred to the front of the arrangement sequence.
Optionally, in the method for screening and testing a chip, a part of the parameters to be tested or all of the parameters to be tested includes at least two test items, and at least two of the test items have a certain relationship.
Optionally, in the method for chip screening test, if any one of the test items fails, the test parameter fails.
Optionally, in the method for chip screening test, an intelligent learning model for chip test is established by using historical test data of the same chip.
Optionally, in the method for chip screening test, the method for processing the test result by using the intelligent learning model includes: and inputting the test result into the intelligent learning model, and outputting the predicted failure probability of the parameter to be tested by the intelligent learning model.
Optionally, in the method for screening and testing a chip, the parameters to be tested include a first parameter to be tested, a second parameter to be tested, a third parameter to be tested, and a fourth parameter to be tested, and the first parameter to be tested, the second parameter to be tested, the third parameter to be tested, and the fourth parameter to be tested are sequentially arranged according to the classification number.
Optionally, in the method for screening and testing a chip, if the failure rate of the second parameter to be tested predicted by the intelligent learning model is the maximum, the arrangement sequence is changed into the second parameter to be tested, the first parameter to be tested, the third parameter to be tested and the fourth parameter to be tested.
Optionally, in the method for screening and testing a chip, if the failure rate of the fourth parameter to be tested predicted by the intelligent learning model is the maximum, the arrangement sequence is changed into the fourth parameter to be tested, the first parameter to be tested, the second parameter to be tested and the third parameter to be tested.
In the chip screening test method provided by the invention, the failure rate of the parameters to be tested is output by processing the test result of the currently tested parameters to be tested through the intelligent learning model, the test parameters with high failure rate are referred to the front row, and the test is carried out preferentially in the subsequent test process, so that the test time of the chip can be reduced, and the test efficiency of the chip can be improved.
Drawings
FIG. 1 is a flow chart of a method of chip screening test according to an embodiment of the present invention.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Referring to fig. 1, the present invention provides a method for chip screening test, including:
s11: establishing an intelligent learning model for chip testing;
s12: classifying the parameters to be tested of each chip, and arranging the parameters to be tested in sequence according to classification numbers;
s13: and sequentially testing the parameters to be tested according to the arranged sequence, processing the test result by using an intelligent learning model, predicting the failure probability of each parameter to be tested, and lifting the classification number of the parameter to be tested with the highest probability to the front of the arranged sequence so as to test the parameter to be tested with the highest probability preferentially.
In the embodiment of the present invention, the test result includes: and testing whether the product, the testing process, the testing batch, the chip number, the coordinate, the ChipID and the testing parameter are invalid or not. The result of the test parameter of each chip can be associated with the relevant information, whether the test parameter of the chip fails or not can be known from the test result, and the product name, the test flow, the test batch, the chip number, the coordinate and the ChipID of the chip can be known, so that the chip can be conveniently tracked.
Preferably, the parameters to be tested of the chip are tested according to the sequence that the classification number of the parameter to be tested with the highest probability is referred to the front row of the arrangement sequence at set intervals. That is, the test result of each piece is required to be input into the intelligent learning model, but if the sequence is adjusted according to the test result after each piece of test, the time for changing is too much, and if a batch of tests are finished and then the tests are performed according to the adjusted sequence, a large amount of time is wasted, so that the tests can be performed according to the adjusted sequence after a period of time or after the number of the tests is set, and the set time or the set number can be calculated by personnel or obtained according to experience.
Preferably, part of the parameters to be tested or all of the parameters to be tested comprise at least two test items, and at least two test items have a certain correlation. And if any test item fails, the test parameters fail. That is, some parameters may contain several associated test items, so that such parameters are tested together with the several test items contained therein, and if there is no associated test item, a test parameter is formed independently. When the sequence is adjusted, several test items are adjusted together.
Preferably, historical test data of the same chip is used for establishing an intelligent learning model of the chip test.
Preferably, the method for processing the test result by using the intelligent learning model comprises the following steps: and inputting the test result into an intelligent learning model, and outputting the predicted failure probability of the parameter to be tested by the intelligent learning model.
Preferably, the parameters to be tested comprise a first parameter to be tested, a second parameter to be tested, a third parameter to be tested and a fourth parameter to be tested, and the first parameter to be tested, the second parameter to be tested, the third parameter to be tested and the fourth parameter to be tested are sequentially arranged according to the classification number. And if the failure rate of the second parameter to be tested predicted by the intelligent learning model is the maximum, changing the arrangement sequence into the second parameter to be tested, the first parameter to be tested, the third parameter to be tested and the fourth parameter to be tested. And if the failure rate of the fourth parameter to be tested predicted by the intelligent learning model is the maximum, changing the arrangement sequence into the fourth parameter to be tested, the first parameter to be tested, the second parameter to be tested and the third parameter to be tested. The first parameter to be tested, the second parameter to be tested, the third parameter to be tested and the fourth parameter to be tested in the embodiment of the present invention are only an example, and may be other numbers of parameters to be tested in practice and may also be other names. For example:
example one
SM15 XX-single channel transceiver normal temperature test:
the CP screening process of the product is normal temperature-high temperature-low temperature, the testing procedures are the same, the normal temperature failure is the most under the general condition, the high temperature failure and the low temperature failure are less, and the normal temperature testing process is taken as an example, known testing items are independent from each other, so classification is not needed, and therefore, the testing can be divided into eight types:
| test parameters | Classification | BinNum | Time of measurement | LOT1 statistics | LOT2 statistics |
| PASS | 55.01％ | 64.23％ | |||
| Connect | / | bin2 | 0.02 | 0％ | 0％ |
| Vih_Vil | A | bin3 | 3.42 | 28.75％ | 6.58％ |
| Voh_Vol | II | bin4 | 0.23 | 0.04％ | 0％ |
| Function | III | bin5 | 0.25 | 14.37％ | 29.08％ |
| Icc | Fourthly | bin6 | 0.84 | 0.04％ | 0.08％ |
| VDYN | Five of them | bin7 | 0.56 | 0％ | 0％ |
| Iihl | Six ingredients | bin8 | 0.21 | 0％ | 0％ |
| Vout | Seven-piece | bin9 | 0.12 | 0％ | 0％ |
| Vth | Eight-part | bin10 | 0.25 | 1.78％ | 0.04％ |
TABLE 1
In table 1, the column of test parameters contains eight parameters to be tested, and the eight parameters are tested sequentially, and the eight parameters are respectively: the statistical results of Vih _ Vil, Voh _ Vol, Function, Icc, VDYN, Iihl, Vout, and Vth, LOT1, and LOT2 are determined as defective using the prior art test method, i.e., yield distribution after the cure test procedure test, most fail die in LOT1 failed bin3 and stopped the test. Due to process variation, most fail die in LOT2 will fail only in bin5 and stop testing, and is judged to be defective.
After the intelligent learning model of the chip test is established, test results are continuously acquired in the test process, including information such as test flow, test batch number, sheet number, coordinates and test project failure conditions, to form a sample set, the samples are updated, the states of test parameters are predicted by using the intelligent learning model, the failure rate of each parameter is predicted in advance, and the failure parameter bin5 with the maximum failure rate is found, so that the test sequence can be adjusted in advance in the LOT2 test process, and the priority of the functional test parameter bin5(Function) is adjusted to be the highest (the top). In the formal test process, most parameters fail when a test parameter bin5(Function) is tested, the test is stopped, the defective products are screened out, and the defective products can be screened out without waiting for the bin3 and bin4 test to be completed like the test method in the prior art.
Example two (FT test):
JEM88 EXXXX-gigabit Ethernet PHY circuit normal temperature test:
the classification and grading conditions of the test parameters are shown in table 1, and the test items of the product part have progressive relations:
TABLE 2
As can be seen from table 2, the test parameters are divided into twelve classes, where 3 test parameters of the eleven and twelve classes need to be fixed in sequence, two of x.1 need to be tested first, and the test parameters of x.2 can be calculated only by obtaining two variable data, when the statistical analysis fails, the eleven and twelve classes of test parameters need to be analyzed and adjusted as a whole, and the sequence of two test items with the same priority in the same class can be changed or adjusted if necessary.
The product has more defective products in the normal temperature test process after packaging, and the yield of the normal temperature test process after packaging in multiple batches tested in 2 months is taken as an example:
TABLE 3
As can be seen from table 3, the main failure items of the circuits in different batches are different, the intelligent learning model for chip testing is used to predict the state of the test parameters in the current batch, and the statistical analysis is performed to obtain the potential failure parameters, so that the test parameters with the highest possible failure can be quickly determined, and the priority of the test parameters can be adjusted. Especially for the relevant parameters of the GMII mode function, taking batch 4 as an example, the predicted main failure parameters are basically concentrated on the eleventh test, i.e. the failure rate of the GMII 1000M mode output clock scan 1 is: 3.0 percent; the failure rate of GMII 1000M mode output clock scan 2 is: 6.27 percent; the failure rate of the rise time of the output clock of the GMII 1000M mode is as follows: 2.23.0 percent. Then it can be calculated that the total failure rate of the eleventh type of test parameter is: (11.47)% (3.0+6.27+ 2.2). Therefore, the order of the GMII 1000M mode output clock scan 2 with a failure rate of 6.27% can be adjusted forward in the eleven types of test parameters in preference to the GMII 1000M mode output clock scan 1 and the GMII 1000M mode output clock rise time test by adjusting the three test items in the eleven types of test parameters together (priority test). By using the testing method provided by the embodiment of the invention, the testing time can be saved to the maximum extent, and the bad circuit packaged by the current product can be screened out quickly.
In summary, in the method for screening and testing a chip provided in the embodiment of the present invention, the failure rate of the parameter to be tested is output by processing the test result of the parameter to be tested that has been tested by the intelligent learning model, the test parameter with a large failure rate is referred to the front, and the test is performed preferentially in the subsequent test process, so that the test time of the chip can be reduced, and the test efficiency of the chip can be improved.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of chip screening tests, comprising:
establishing an intelligent learning model for chip testing;
classifying the parameters to be tested of each chip, and arranging the parameters to be tested in sequence according to classification numbers;
and sequentially testing the parameters to be tested according to the arranged sequence, processing the test result by using an intelligent learning model, predicting the failure probability of each parameter to be tested, and lifting the classification number of the parameter to be tested with the highest probability to the front of the arranged sequence so as to test the parameter to be tested with the highest probability preferentially.
2. The method for chip screening test of claim 1, wherein the test results comprise: and testing whether the product, the testing process, the testing batch, the chip number, the coordinate, the ChipID and the testing parameter are invalid or not.
3. The method for chip screening test as set forth in claim 1, wherein the parameters to be tested of said chip are tested at set intervals in an order in which the classification number of the parameter to be tested having the highest probability is mentioned to the front of the arrangement order.
4. The method for chip screening test of claim 1, wherein some or all of the parameters to be tested comprise at least two test items, and at least two of the test items have a certain relationship therebetween.
5. The method for chip screening test of claim 4, wherein if any of said test items fails, said test parameter fails.
6. The method of chip screening test of claim 1, wherein the same kind of historical test data of the chip is used to build an intelligent learning model of chip testing.
7. The method for chip screening test of claim 1, wherein the method for processing the test result using the smart learning model comprises: and inputting the test result into the intelligent learning model, and outputting the predicted failure probability of the parameter to be tested by the intelligent learning model.
8. The method for chip screening test of claim 1, wherein the parameters to be tested include a first parameter to be tested, a second parameter to be tested, a third parameter to be tested and a fourth parameter to be tested, and the first parameter to be tested, the second parameter to be tested, the third parameter to be tested and the fourth parameter to be tested are arranged in sequence according to the classification number.
9. The method for chip screening test of claim 8, wherein if the failure rate of the second parameter to be tested predicted by the smart learning model is the largest, the ranking order is changed to the second parameter to be tested, the first parameter to be tested, the third parameter to be tested and the fourth parameter to be tested.
10. The method for chip screening test according to claim 8, wherein if the failure rate of the fourth parameter to be tested predicted by the smart learning model is the maximum, the sequence is changed to the fourth parameter to be tested, the first parameter to be tested, the second parameter to be tested and the third parameter to be tested.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111523044.9A CN114264930A (en) | 2021-12-13 | 2021-12-13 | Chip screening test method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111523044.9A CN114264930A (en) | 2021-12-13 | 2021-12-13 | Chip screening test method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114264930A true CN114264930A (en) | 2022-04-01 |
Family
ID=80826952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111523044.9A Pending CN114264930A (en) | 2021-12-13 | 2021-12-13 | Chip screening test method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114264930A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115308518A (en) * | 2022-10-10 | 2022-11-08 | 杭州三海电子有限公司 | Method and system for determining parameter measurement sequence of burn-in circuit |
| CN116148641A (en) * | 2023-04-20 | 2023-05-23 | 长鑫存储技术有限公司 | Method, apparatus, computer device and readable storage medium for chip classification |
| CN116774017A (en) * | 2023-08-22 | 2023-09-19 | 南京宏泰半导体科技股份有限公司 | Chip test efficiency improving system and method based on machine learning |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0541441A (en) * | 1991-07-02 | 1993-02-19 | Nec Kyushu Ltd | Testing method for integrated circuit |
| JPH1194909A (en) * | 1997-09-17 | 1999-04-09 | Mitsubishi Electric Corp | Method and apparatus for testing semiconductor device |
| JPH11243125A (en) * | 1998-02-25 | 1999-09-07 | Yokogawa Electric Corp | Ic test system |
| JP2007298465A (en) * | 2006-05-02 | 2007-11-15 | Fujitsu Ltd | Test sequence determination method, device, and program |
| US20110288808A1 (en) * | 2010-05-20 | 2011-11-24 | International Business Machines Corporation | Optimal test flow scheduling within automated test equipment for minimized mean time to detect failure |
| CN102707225A (en) * | 2012-06-21 | 2012-10-03 | 上海华岭集成电路技术股份有限公司 | Integrated circuit testing optimizing method and testing device thereof |
| US20190304849A1 (en) * | 2018-03-27 | 2019-10-03 | Streammosaic, Inc. | Selective inclusion/exclusion of semiconductor chips in accelerated failure tests |
| TW202006546A (en) * | 2018-07-06 | 2020-02-01 | 華邦電子股份有限公司 | Testing system and adaptive method of generating testing program |
| US20200250078A1 (en) * | 2019-02-01 | 2020-08-06 | Micro Focus Llc | Time-limited dynamic testing pipelines |
| CN112990479A (en) * | 2021-02-26 | 2021-06-18 | 普赛微科技(杭州)有限公司 | Method for improving semiconductor chip yield by using machine learning classifier |
-
2021
- 2021-12-13 CN CN202111523044.9A patent/CN114264930A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0541441A (en) * | 1991-07-02 | 1993-02-19 | Nec Kyushu Ltd | Testing method for integrated circuit |
| JPH1194909A (en) * | 1997-09-17 | 1999-04-09 | Mitsubishi Electric Corp | Method and apparatus for testing semiconductor device |
| JPH11243125A (en) * | 1998-02-25 | 1999-09-07 | Yokogawa Electric Corp | Ic test system |
| JP2007298465A (en) * | 2006-05-02 | 2007-11-15 | Fujitsu Ltd | Test sequence determination method, device, and program |
| US20110288808A1 (en) * | 2010-05-20 | 2011-11-24 | International Business Machines Corporation | Optimal test flow scheduling within automated test equipment for minimized mean time to detect failure |
| CN102707225A (en) * | 2012-06-21 | 2012-10-03 | 上海华岭集成电路技术股份有限公司 | Integrated circuit testing optimizing method and testing device thereof |
| US20190304849A1 (en) * | 2018-03-27 | 2019-10-03 | Streammosaic, Inc. | Selective inclusion/exclusion of semiconductor chips in accelerated failure tests |
| TW202006546A (en) * | 2018-07-06 | 2020-02-01 | 華邦電子股份有限公司 | Testing system and adaptive method of generating testing program |
| US20200250078A1 (en) * | 2019-02-01 | 2020-08-06 | Micro Focus Llc | Time-limited dynamic testing pipelines |
| CN112990479A (en) * | 2021-02-26 | 2021-06-18 | 普赛微科技(杭州)有限公司 | Method for improving semiconductor chip yield by using machine learning classifier |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115308518A (en) * | 2022-10-10 | 2022-11-08 | 杭州三海电子有限公司 | Method and system for determining parameter measurement sequence of burn-in circuit |
| CN115308518B (en) * | 2022-10-10 | 2022-12-23 | 杭州三海电子有限公司 | Parameter measurement sequence determination method and system for burn-in circuit |
| CN116148641A (en) * | 2023-04-20 | 2023-05-23 | 长鑫存储技术有限公司 | Method, apparatus, computer device and readable storage medium for chip classification |
| CN116148641B (en) * | 2023-04-20 | 2023-09-19 | 长鑫存储技术有限公司 | Method, apparatus, computer device and readable storage medium for chip classification |
| CN116774017A (en) * | 2023-08-22 | 2023-09-19 | 南京宏泰半导体科技股份有限公司 | Chip test efficiency improving system and method based on machine learning |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114264930A (en) | Chip screening test method | |
| US6055463A (en) | Control system and method for semiconductor integrated circuit test process | |
| CN100587507C (en) | Method and system for measuring manufactured integrate circuit component | |
| US5570376A (en) | Method and apparatus for identifying faults within a system | |
| CN103413771B (en) | The work dispatching method of wafer acceptance test board | |
| US6857090B2 (en) | System and method for automatically analyzing and managing loss factors in test process of semiconductor integrated circuit devices | |
| CA2515784A1 (en) | Methods and apparatus for data analysis | |
| KR20060006723A (en) | Methods and apparatus for test process enhancement | |
| US7715937B2 (en) | Allocating manufactured devices according to customer specifications | |
| CN109411380B (en) | Method for testing electrical parameters of storage medium and wafer-level integrated circuit | |
| CN108037433B (en) | Screening method and device for integrated circuit test data | |
| CN101398451A (en) | Rapid detection method for testing backing board | |
| CN112014719B (en) | Screening method and device for mass production chips | |
| CN113408915B (en) | Production line bottleneck identification method and system | |
| CN114839518A (en) | Effective key area parameter vector set reordering method and system | |
| US6766265B2 (en) | Processing tester information by trellising in integrated circuit technology development | |
| CN109444712B (en) | Integrated circuit data screening method based on normalization method combined with Euclidean distance function | |
| US6385762B1 (en) | Data reduction using rank-of-ranks methodology | |
| CN101470422B (en) | Debugging method of debugging system for production process machine bench | |
| Lee et al. | Test item priority estimation for high parallel test efficiency under ATE debug time constraints | |
| Streitwieser | Real-time test data acquisition and data processing enabling closed loop control systems for adaptive test | |
| US11152236B2 (en) | System for and method of manufacture using multimodal analysis | |
| US6815233B1 (en) | Method of simultaneous display of die and wafer characterization in integrated circuit technology development | |
| CN110646426B (en) | Method for evaluating white pixel difference of different machine tables of CIS product | |
| US20230290692A1 (en) | Chip grading method and packaging method, and chip grading system and packaging system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |