CN114839518A - Effective key area parameter vector set reordering method and system - Google Patents
Effective key area parameter vector set reordering method and system Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318364—Generation of test inputs, e.g. test vectors, patterns or sequences as a result of hardware simulation, e.g. in an HDL environment
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Abstract
The invention provides a reordering method and a system of an effective key area parameter vector set, which comprises the following steps: obtaining a circuit description language of an integrated circuit to be tested, and generating a test vector set aiming at the integrated circuit to be tested by using a test vector generation tool ATPG; fault injection is carried out on an analog circuit of the integrated circuit to be tested, and whether the integrated circuit to be tested has faults or not is obtained and judged according to a test response value in the current analog circuit; and processing the area coverage of the total key area of transistors contained in different unit circuits relative to the unit circuit by referring to the structural diagram of the integrated circuit to be tested, counting the number of times of hitting faults of each test vector in the test vector set so as to obtain a test characteristic value, processing the test vectors according to the test characteristic value in a sequencing manner, and reordering the test vector set so as to test the integrated circuit to be tested. The invention solves the technical problems of high test cost, low test efficiency and low test accuracy of the integrated circuit.
Description
Technical Field
The invention relates to an integrated circuit testing technology, in particular to a method and a system for reordering an effective critical area parameter vector set.
Background
With the rapid development of the process of the modern semiconductor industry, even chips consisting of hundreds of millions of MOS transistors have come out. In 2019, in the IEEE international electronic device conference (IEMD), the chip grand intel predicts that the chip manufacturing process node technology will keep a 2-year leap pace. Large circuit designs and shrinking feature sizes lead to increased variety of manufacturing defects and reduced yield, and control of these properties becomes particularly difficult. By the end of 2020, the total chip performance change rate has increased to 69%, which directly leads to a rapid increase in the number of test vectors in testing, a significant increase in the test time of Automatic Test Equipment (ATE), and an increasing test cost.
At present, automatic test equipment ATE is expensive in manufacturing cost, high in technological content and huge in updating cost. However, with the rapid development of the CMOS process level, the larger the chip manufacturing scale is, the more dense the circuit components and the circuit complexity are, and the result is that the automatic test equipment ATE is far from meeting the actual requirements of chip testing in terms of performance and technology. Therefore, only by widening the thought, integrating innovation, optimizing the testing method and fully utilizing the existing equipment, the testing efficiency of the fault chip can be improved, and the testing cost is effectively reduced.
Inventive patent application No. CN03802114.5, methods and apparatus for transferring scan patterns in scan-based integrated circuits, transmitter, system and method for reducing test data volume and test implementation time of ATE (automatic test equipment) in scan-based integrated circuits. The scan-based integrated circuit contains multiple scan chains, each scan chain including multiple scan cells connected in series. A transmitter is a combinational logic network connected to any virtual scan controller and any scan connector. The virtual scan controller controls the operation of the transmitter. The system transmits the virtual scan pattern stored in the ATE and generates a transmission scan pattern for testing manufacturing errors based on testing in the integrated circuit by the transmitter. The number of scan chains provided by the ATE can be effectively increased. The method further provides for reordering the scan cells in the selected scan chain to generate a broadcast scan pattern and a dummy scan pattern, and synthesizing the broadcaster and the compactor in the scan-based integrated circuit. Where the broadcaster is implemented using a combinational logic network, the input constraints imposed by the broadcaster allow only a subset of the scan cells to accept a predetermined logic value at any one time that is equal to or complementary to the ATE output. Unlike the transmitter scan arrangement of the previous document which only allows patterns of all zeros and all ones to be applied to the transmitter channels, this prior patent allows different combinations of logic values to appear on these channels at different times. Generating these test patterns requires only enlarging the commonly used ATPG tool to achieve these additional input constraints. Thus, the process of generating the transmission scan pattern will generate the pattern using a set of initial input constraints and analyze the coverage obtained. If the obtained error coverage is not satisfactory, a different set of input limits is applied and a new set of vectors is generated. This process is repeated until the predetermined limiting criteria are met. The foregoing prior patent employs an ATPG tool to expand test patterns, thereby implementing these additional input restrictions, and the present application reorders test vectors without changing the accuracy of fault coverage, and the reordering of test vectors of the patent is different from the specific implementation method employed in the reordering of the present application, and in addition, the patent is applied to a scenario of reducing false coverage of a base scan design, and there is also a difference from the application scenario of the technical scheme of the present application.
In summary, the prior art has the technical problems of high test cost, low test efficiency and low test accuracy.
Disclosure of Invention
The invention aims to solve the technical problems of high test cost, low test efficiency and low test accuracy of the integrated circuit.
The invention adopts the following technical scheme to solve the technical problems: a reordering method of an effective key area parameter vector set comprises the following steps:
s1, obtaining a circuit description language of the integrated circuit to be tested, describing the integrated circuit to be tested by using the hardware description language, and generating a test vector set aiming at the integrated circuit to be tested by using a test vector generation tool ATPG;
s2, fault injection is carried out on the analog circuit of the integrated circuit to be tested, a test response value in the integrated circuit to be tested is obtained, the test response value is compared with a normal circuit test response value, and whether the integrated circuit to be tested has faults or not is judged according to the test response value;
and S3, referring to the structure diagram of the integrated circuit to be tested, processing the area coverage of the total key area of the transistors contained in different unit circuits relative to the unit circuit, counting the times of the hit faults of each test vector in the test vector set, processing to obtain test characteristic values, and processing the test vectors according to the test characteristic values in order to reorder the test vector set for testing the integrated circuit to be tested.
The invention relates to a test method for covering the total critical area of transistors contained in various fault unit circuits in relation to the total area of the unit circuits according to the hit of test vectors by sequencing a test vector set. The invention uses the test vector generation tool ATPG to generate the test vector set aiming at the tested integrated circuit, reduces the test time of a fault chip, improves the test efficiency and reduces the test cost on the premise of not changing the fault coverage rate precision, and the method can present better effect in a super-large-scale complex circuit.
In a more specific technical solution, the step S1 includes:
s11, analyzing and modeling the internal structure of the integrated circuit to be tested, describing the internal structure by the circuit description language, and generating a corresponding analog circuit;
and S12, acquiring the test parameters of the analog circuit, and generating the test vector set by using the test vector generation tool ATPG.
In a more specific technical solution, the step S11 includes:
s111, collecting internal structure data of the integrated circuit to be tested;
and S112, analyzing the internal structure data to model the integrated circuit to be tested so as to construct the analog circuit.
In a more specific technical solution, the step S12 includes:
s121, acquiring data and parameters of the test type of the analog circuit;
s122, acquiring data parameters and requirements in each test type of the analog circuit;
s123, inputting the data and parameters of the test types, the data parameters in each test type and the requirements into the test vector generation tool ATPG so as to generate the test vector set.
The invention balances the unequal proportional relation between the circuit area of the unit circuit and the total key area of the contained transistor in some circuit in the production process design, is beneficial to correct classification research, and can more objectively realize the test aim that the test vector can find the fault earlier in the test process. The method is completely based on software, does not need additional hardware equipment requirements, reduces the testing cost and is feasible.
In a more specific technical solution, the step S2 includes:
s21, acquiring difference preset fault injection parameters;
s22, inputting the difference fault injection parameters into the analog circuit to obtain different test response values;
and S23, judging whether the integrated circuit to be tested has faults or not according to the test response value.
In a more specific technical solution, the step S3 includes:
s31, acquiring the characteristic sizes of various transistors in the analog circuit;
s32, acquiring the ratio data of each circuit unit of the analog circuit;
s33, processing the structure diagram in the analog circuit to obtain the total critical area data of the transistors of each unit circuit and the area data of the unit circuit;
s34, processing the transistor total critical area data and the unit circuit area data to obtain relative area coverage data of different unit circuits in the integrated circuit to be tested;
s35, counting the hit times of each test vector in the simulation fault test process of the simulation circuit;
s36, estimating the test eigenvalue of each test vector according to the hit times, and sequencing the test vectors according to the test eigenvalue to obtain the reordered test vector set.
The invention not only considers the influence of the peripheral neighborhood fault environment of the circuit on the unit circuit, but also pays attention to the possibility of all faults in the unit circuit, also considers the possibility of various physical faults in the transistor and comprehensively considers the problem of circuit complexity.
The invention comprehensively considers the problem of circuit complexity on the premise of not changing the fault coverage rate precision, and reorders the test vectors according to the test characteristic value of each test vector, thereby achieving the purposes of reducing the test time, improving the test efficiency and reducing the test cost.
In a more specific technical solution, in the step S34, the sorting manner of the test vectors includes: and (5) arranging in descending order.
The invention sorts the test vectors according to the test quality from high to low, preferentially loads the test vectors with better test quality in the test set, and leads the test vectors to hit the fault earlier in the test process, thereby achieving the purposes of reducing the test time of the fault integrated circuit, improving the test efficiency and reducing the test cost.
In a more specific technical solution, a method for reordering an effective critical area parameter vector set further includes:
s1', inputting the test vector into Automatic Test Equipment (ATE);
s2', sequentially testing the reordered set of test vectors with the automatic test equipment ATE to complete the testing of the integrated circuit under test.
According to the characteristics and the working process of the automatic test equipment ATE, after each test vector is input into the automatic test equipment ATE, faults which can be detected by the test vector are fixed and invariable in an integrated circuit, and the faults cannot be changed due to the change of the sequence of the test vector. However, different test vectors may hit the same fault, and the number of hit faults of different test vectors is also different, so that more test vectors with better test quality can be loaded preferentially by using a method of changing the loading sequence of the test vectors, the fault coverage rate of the original test set can be maintained, the fault detection time can be obviously shortened, and the test efficiency can be improved.
In a more specific embodiment, in step S2', when the test vector hits a fault of the ic under test, it is determined to screen out a chip corresponding to the ic under test.
In a more specific embodiment, a system for reordering a vector set of effective critical area parameters includes:
the vector set generating module is used for acquiring a circuit description language of the integrated circuit to be tested and generating a test vector set aiming at the integrated circuit to be tested by utilizing a test vector generating tool ATPG;
the fault injection module is used for performing fault injection on the analog circuit of the integrated circuit to be tested, acquiring and judging whether the integrated circuit to be tested has faults or not according to the current test response value in the analog circuit, and the fault injection module is connected with the vector set generation module;
and the reordering module is used for processing the total critical area of the transistors contained in different unit circuits relative to the area coverage of the unit circuit by referring to the structure diagram of the integrated circuit to be tested, counting the times of hitting faults of each test vector in the test vector set so as to obtain a test characteristic value, processing the test vectors according to the test characteristic value in an ordering mode so as to reorder the test vector set and test the integrated circuit to be tested, and the reordering module is connected with the fault injection module.
Compared with the prior art, the invention has the following advantages: the invention relates to a test method for covering the total critical area of transistors contained in various fault unit circuits in relation to the total area of the unit circuits according to the hit of test vectors by sequencing a test vector set. On the premise of not changing the fault coverage rate precision, the method reduces the test time of the fault chip, improves the test efficiency, reduces the test cost, and can show better effect in the super-large-scale complex circuit.
The invention balances the unequal proportional relation between the circuit area of the unit circuit and the total key area of the contained transistor in some circuit in the production process design, is beneficial to correct classification research, and can more objectively realize the test aim that the test vector can find the fault earlier in the test process. The method is completely based on software, does not need additional hardware equipment requirements, reduces the testing cost and is feasible.
The invention not only considers the influence of the peripheral neighborhood fault environment of the circuit on the unit circuit, but also pays attention to the possibility of all faults in the unit circuit, also considers the possibility of various physical faults in the transistor and comprehensively considers the problem of circuit complexity.
The invention sorts the test vectors according to the test quality from high to low, preferentially loads the test vectors with better test quality in the test set, and leads the test vectors to hit the fault earlier in the test process, thereby achieving the purposes of reducing the test time of the fault integrated circuit, improving the test efficiency and reducing the test cost.
The different test vectors of the invention are possible to hit the same fault, and the number of the hit faults of the different test vectors is different, so that the method of changing the loading sequence of the test vectors can be used for leading more test vectors with better test quality to be loaded preferentially, and the fault coverage rate of the original test set is kept. The invention solves the technical problems of high test cost, low test efficiency and low test accuracy in the prior art.
Drawings
FIG. 1 is a schematic diagram of a basic flow of a reordering method for a vector set of effective critical area parameters;
fig. 2 is a detailed flow diagram of a reordering method of an effective critical area parameter vector set.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
For integrated circuit testing, the main flow is as follows:
s1, analyzing and modeling according to the internal structure of the circuit to be tested, and generating a Test vector aiming at the circuit by using an Automatic Test Pattern Generation (ATPG). In the process, the circuit is ensured to reach high fault coverage rate as much as possible.
And S2, after obtaining the test vectors, referring to the structure diagram of the integrated circuit to be tested, calculating the area coverage of the total key area containing the transistors in different unit circuits relative to the unit circuit, in the test process, combining the statistics of the number of times of hitting the corresponding unit circuit fault by each test vector, estimating the test characteristic value of each test vector, reordering the original test set, inputting the ordered test vector set into Automatic Test Equipment (ATE), and testing each circuit to be tested. If any fault is hit by the test vector, the chip is proved to have a problem and cannot be used. If the chip passes all the test vectors, the chip passes the test, and no fault occurs, the chip does not have any fault and can be put into use.
The method of the patent is not directed to the generation process of the test vectors, but is mainly directed to the processing of the test vector set generated in the above-mentioned flow, and the test vectors are reordered. The main focus of this patent lies in: on the premise of not changing the fault coverage rate precision, the circuit complexity problem is comprehensively considered, and the test vectors are reordered according to the test characteristic value of each test vector, so that the aims of reducing the test time, improving the test efficiency and reducing the test cost are fulfilled.
According to the characteristics and the working process of the automatic test equipment ATE, it is known that after each test vector is input into the automatic test equipment ATE, faults which can be detected by the test vector are all fixed and unchanged in an integrated circuit, and cannot be changed due to the change of the sequence of the test vectors. However, different test vectors may hit the same fault, and the number of hit faults of different test vectors is also different, so that more test vectors with better test quality can be loaded preferentially by using a method of changing the loading sequence of the test vectors, so that the fault coverage rate of the original test set can be maintained, the fault detection time can be obviously shortened, and the test efficiency can be improved.
The present invention provides a test vector adjusting method for measuring the test quality of a test vector by using the ratio of the total critical area of a transistor to the circuit unit. And estimating the test characteristic value of each test vector from the test global synthesis. This patent is mainly keeping under the prerequisite that former test set fault coverage rate keeps unchangeable, only to the order transform of test vector, provides better high-quality test set for automatic test equipment ATE to reach and reduce test time, reduce test cost's purpose.
The main content of the invention is as follows: according to the circuit description language, the data is used to perform an efficient metric on the test vector by calculating the total critical area of the transistors in the corresponding cell circuit for the fault hit by the test vector relative to the area coverage of that cell circuit. If the quality of the test vector with a larger test characteristic value is more excellent in the chip under a certain process, the test vector with the larger test characteristic value is arranged in front, and the test vector reordering is performed in the same way. Therefore, when the test is carried out again, the test vector with the maximum test characteristic value is arranged at the first position, the circuit complexity of the unit circuit passed by the first test vector is maximum, the probability of the detected fault is maximum, and the second and third test vectors are sequentially decreased progressively. In actual test, ATE follows a 'failure-to-stop' test mode, that is, as long as any fault is detected in a circuit, the chip is damaged and cannot be used, and the test is stopped, so that the fault can be found earlier through the sequencing, the test time can be effectively reduced, and the test cost is reduced.
Example 2
S1', generating a Test vector set for the circuit by using an Automatic Test Pattern Generation (ATPG) tool according to the circuit description language.
S2', fault injection is performed on the circuit. Whether the circuit has a fault is judged according to a test response value of the test vector input into the analog circuit.
S3', referring to the structure diagram of the tested integrated circuit, calculating the area coverage of the total key area of the transistors contained in different unit circuits relative to the unit circuit, counting the times of hitting faults of each test vector in the fault simulation test, comprehensively estimating the test characteristic value of each test vector, arranging the test vector with the maximum test characteristic value at the first position, and then repeating the steps to complete the sequencing, and then obtaining a new sequenced test vector set.
S4', after the test vector set is sequenced, the test vectors are input into Automatic Test Equipment (ATE), the first test vector can measure the maximum failure probability, and the second and third test vectors are decreased in sequence. Therefore, for a random fault, the sorted test vector set can detect the fault more quickly, so that the test time is reduced, and the test cost is reduced.
In summary, the present invention is a testing method for testing the total critical area of transistors included in each faulty unit circuit according to the total critical area of the transistors hit by the test vectors with respect to the total area coverage of the unit circuit by sorting the test vector set. On the premise of not changing the fault coverage rate precision, the method reduces the test time of the fault chip, improves the test efficiency, reduces the test cost, and can show better effect in the super-large-scale complex circuit.
The invention balances the unequal proportional relation between the circuit area of the unit circuit and the total key area of the contained transistor in some circuit in the production process design, is beneficial to correct classification research, and can more objectively realize the test aim that the test vector can find the fault earlier in the test process. The method is completely based on software, does not need additional hardware equipment requirements, reduces the testing cost and is feasible.
The invention not only considers the influence of the peripheral neighborhood fault environment of the circuit on the unit circuit, but also pays attention to the possibility of all faults in the unit circuit, also considers the possibility of various physical faults in the transistor and comprehensively considers the problem of circuit complexity.
The invention sorts the test vectors according to the test quality from high to low, preferentially loads the test vectors with better test quality in the test set, and leads the test vectors to hit the fault earlier in the test process, thereby achieving the purposes of reducing the test time of the fault integrated circuit, improving the test efficiency and reducing the test cost.
The different test vectors of the invention are possible to hit the same fault, and the number of the hit faults of the different test vectors is different, so that the method of changing the loading sequence of the test vectors can be used for leading more test vectors with better test quality to be loaded preferentially, and the fault coverage rate of the original test set is kept. The invention solves the technical problems of high test cost, low test efficiency and low test accuracy in the prior art.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A reordering method for effective key area parameter vector set (AMP), the method comprising:
s1, obtaining a circuit description language of the integrated circuit to be tested, describing the integrated circuit to be tested by using the hardware description language, and generating a test vector set aiming at the integrated circuit to be tested by using a test vector generation tool ATPG;
s2, fault injection is carried out on the analog circuit of the integrated circuit to be tested, a test response value in the integrated circuit to be tested is obtained, the test response value is compared with a normal circuit test response value, and whether the integrated circuit to be tested has faults or not is judged according to the test response value;
and S3, referring to the structure diagram of the integrated circuit to be tested, processing the area coverage of the total key area of the transistors contained in different unit circuits relative to the unit circuit, counting the number of times of hitting faults of each test vector in the test vector set, processing to obtain test characteristic values, and processing the test vectors according to the test characteristic values in a sequencing manner to reorder the test vector set for testing the integrated circuit to be tested.
2. The method for reordering the effective critical area parameter vector set according to claim 1, wherein said step S1 comprises:
s11, analyzing and modeling the internal structure of the integrated circuit to be tested, describing the internal structure by the circuit description language, and generating a corresponding analog circuit;
and S12, acquiring the test parameters of the analog circuit, and generating the test vector set by using the test vector generation tool ATPG.
3. The method for reordering the effective critical area parameter vector set according to claim 2, wherein said step S11 comprises:
s111, collecting internal structure data of the integrated circuit to be tested;
and S112, analyzing the internal structure data to model the integrated circuit to be tested so as to construct the analog circuit.
4. The method for reordering the effective critical area parameter vector set according to claim 2, wherein said step S12 comprises:
s121, acquiring data and parameters of the test type of the analog circuit;
s122, taking data parameters and requirements in each test type of the analog circuit;
s123, inputting the data and parameters of the test types, the data parameters in each test type and the requirements into the test vector generation tool ATPG so as to generate the test vector set.
5. The method for reordering the effective critical area parameter vector set according to claim 1, wherein said step S2 comprises:
s21, acquiring difference preset fault injection parameters;
s22, inputting the difference fault injection parameters into the analog circuit to obtain different test response values;
and S23, judging whether the integrated circuit to be tested has faults or not according to the test response value.
6. The method for reordering the effective critical area parameter vector set according to claim 1, wherein said step S3 comprises:
s31, acquiring the characteristic sizes of various transistors in the analog circuit;
s32, acquiring the ratio data of each circuit unit of the analog circuit;
s33, processing the structure diagram in the analog circuit to obtain the total critical area data of the transistors of each unit circuit and the area data of the unit circuit;
s34, processing the transistor total critical area data and the unit circuit area data to obtain relative area coverage data of different unit circuits in the integrated circuit to be tested;
s35, counting the hit times of each test vector in the simulation fault test process of the simulation circuit;
s36, estimating the test eigenvalue of each test vector according to the hit times, and sequencing the test vectors according to the test eigenvalue to obtain the reordered test vector set.
7. The method of claim 6, wherein in step S34, the test vectors are ordered in a manner comprising: and (5) arranging in descending order.
8. The method of claim 1, further comprising:
s1', inputting the test vector into Automatic Test Equipment (ATE);
s2', sequentially testing the reordered set of test vectors with the automatic test equipment ATE to complete the testing of the integrated circuit under test.
9. The method of claim 8, wherein in step S2', when the test vector hits a fault of the ic under test, it is determined to screen out a corresponding chip of the ic under test.
10. A system for effective critical area parameter vector set reordering, the system comprising:
the vector set generating module is used for acquiring a circuit description language of the integrated circuit to be tested and generating a test vector set aiming at the integrated circuit to be tested by utilizing a test vector generating tool ATPG;
the fault injection module is used for performing fault injection on the analog circuit of the integrated circuit to be tested, acquiring and judging whether the integrated circuit to be tested has faults or not according to the current test response value in the analog circuit, and the fault injection module is connected with the vector set generation module;
and the reordering module is used for processing the total critical area of the transistors contained in different unit circuits relative to the area coverage of the unit circuit by referring to the structure diagram of the integrated circuit to be tested, counting the times of hitting faults of each test vector in the test vector set so as to obtain a test characteristic value, processing the test vectors according to the test characteristic value in an ordering mode so as to reorder the test vector set and test the integrated circuit to be tested, and the reordering module is connected with the fault injection module.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115308518A (en) * | 2022-10-10 | 2022-11-08 | 杭州三海电子有限公司 | Method and system for determining parameter measurement sequence of burn-in circuit |
| CN115308518B (en) * | 2022-10-10 | 2022-12-23 | 杭州三海电子有限公司 | Parameter measurement sequence determination method and system for burn-in circuit |
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