JPS5831549A - Inspecting system - Google Patents

Inspecting system

Info

Publication number
JPS5831549A
JPS5831549A JP56129675A JP12967581A JPS5831549A JP S5831549 A JPS5831549 A JP S5831549A JP 56129675 A JP56129675 A JP 56129675A JP 12967581 A JP12967581 A JP 12967581A JP S5831549 A JPS5831549 A JP S5831549A
Authority
JP
Japan
Prior art keywords
time
test
wafer
testing
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56129675A
Other languages
Japanese (ja)
Other versions
JPS6229901B2 (en
Inventor
Yasushi Matsukawa
靖 松川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56129675A priority Critical patent/JPS5831549A/en
Publication of JPS5831549A publication Critical patent/JPS5831549A/en
Publication of JPS6229901B2 publication Critical patent/JPS6229901B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Abstract

PURPOSE:To enable an inspecting system which can efficiently operate an inspecting facility by prenotifying the ending time of a testing work. CONSTITUTION:Wafer probes 2, 2' test by a testing unit 1 chips on a wafer, and when all chips are completely tested, a test end signal of one wafer is fed to a processor 3. The processor 3 reads out by a clock 4 a time of receiving the signal, and obtains a difference from the time of the previous test end signal, i.e., the testing time of one wafer. When the testing times of the wafers of the previously arbitrarily specified number are obtained, the mean testing time of one wafer can be decided. The processor 3 decides the planed test end time of the lot is estimated from the obtained mean testing time and indicates it on an indicator 6. When the time before the arbitrarily set prescribed time of the planted time comes, the finish of the test of this lot after the prescribed time is indicated on the indicator 6. The finishing time is prenotified by applying a simple device.

Description

【発明の詳細な説明】 本発明は検査システムにかかり、とくに集積回路環の測
定・試験を行う検査システムに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inspection system, and more particularly to an inspection system for measuring and testing an integrated circuit ring.

半導体集積回路はその製造工程中拡散工程の後にウー・
・°−ブロービング試験、ま羨組立工程の後に製品試験
が行われ一1電気的特性を検査されるがそのIA試験装
置と、ウェハーのハンドリングを行うウェハープロー六
、あるいは製品のハンドリングを行うハンドラといった
ハンドリング装置が使用される。しかるに近年の集積回
路の進歩は著しく、それに゛伴い試験装置は高性能化、
高機能化、高機能化されハンドリング装置はますます自
動化高機能化され共に非常に高価な装置になってきてい
る。そこで装置の有効利用が望まれるわけで本発明はこ
のよなな検査装置の有効利用を目的としている。
Semiconductor integrated circuits are manufactured by woofers after the diffusion process during their manufacturing process.
・Product testing is performed after the blobbing test and the assembly process, and the electrical characteristics are inspected using the IA test equipment, a wafer probe that handles the wafer, or a handler that handles the product. A handling device such as this is used. However, the progress of integrated circuits in recent years has been remarkable, and as a result, test equipment has become more sophisticated.
Handling equipment has become increasingly automated and highly functional, and both have become extremely expensive. Therefore, it is desirable to make effective use of the apparatus, and the present invention aims at making effective use of such an inspection apparatus.

本発明は試験装置と被試験物のハンドリング装置等によ
って構成される検査システムにおいて、個々の被試験物
の試験時間を計数する手段と、あらかじめ設定された被
試験物の数量と前記試験時間を基にして、被試験物全体
の試験終了時刻を予告する手段とを具備することを特徴
とする検査システムである。
The present invention provides an inspection system composed of a test device, a device for handling test objects, etc., which includes a means for counting the test time of each test object, and a means for counting the test time of each test object, and a means for counting the test time based on a preset number of test objects and the test time. The present invention is an inspection system characterized by comprising: a means for giving advance notice of a test end time for the entire test object;

以下ウェハーブロービング試験の場合について説明する
The case of the wafer roving test will be explained below.

半導体ウェハーには通常数百個の集積回路チップが形成
されるがその個数は当然品種によって異なシ、1チツグ
の測定時間も当然品種によって異なり、また通常、不良
チップの測定時間は良品のそれよシ短く、そして、歩留
シもまた品種によって異なる。従9て、lクエハー当シ
の試験時間は当然品種によりて異なり、長いものもあれ
ば短いものもある。ここでいう試験時間は、純粋の測定
時間ではなくインデックス時間等を含めた試験に要し要
時間の意である。ま九一般に1台の試験装置には2,3
台のハンドリング装置つまりクエハープロ:バが接続さ
れ、時分割動作によシ試験が行われるが、その場合、各
ウェハープローバにおいて扱われる品種は、同一とは限
らずしばしば異なる品種の組み合せで試験が行われるた
めに、1ウェハー当りの試験時間は他のウェハープロー
バにおいて試験されている品種によって変わる。促つて
数十枚のウェハーの10ツトの試験時間は、場合、場合
によって変わってくるわけで、その試験終了時刻を割り
出すことは困難である。従来、10ツトの試験終了紘試
験作業を行う作業者によって確認されていた。従って作
業者が気利くのが遅れると高価な検査設備は遅れた時間
、不稼働の状悴にあシ、検査設備の効率の良い運用がで
きなかった。本発明はこのような欠点を鱗決し、効率良
く検査設備を稼動させる検査システムを提供するもので
ある。
Several hundred integrated circuit chips are normally formed on a semiconductor wafer, and the number of integrated circuit chips naturally varies depending on the product type.The measurement time for one chip also naturally varies depending on the product type, and the measurement time for a defective chip is usually longer than that for a good chip. The length is short, and the yield also varies depending on the variety. Therefore, the testing time for l-quafer tests naturally varies depending on the variety, and some are longer while others are shorter. The test time here does not mean pure measurement time but the time required for the test including index time and the like. In general, one test device requires 2 to 3
A handling device for each wafer prober, that is, a wafer prober, is connected and tests are performed in a time-division operation.In this case, the types handled by each wafer prober are not necessarily the same, and tests are often performed using combinations of different types. Therefore, the testing time per wafer varies depending on the type of wafer being tested in other wafer probers. The time required for testing 10 tests on several dozen wafers varies from case to case, and it is difficult to determine the end time of the test. Conventionally, this has been confirmed by a worker who performs 10 test completion tests. Therefore, if the operator is slow to act, the expensive testing equipment will be left unused for a long time, and the testing equipment cannot be operated efficiently. The present invention provides an inspection system that eliminates these drawbacks and efficiently operates inspection equipment.

以下、本発明について説明する。第1図は本発明の一実
施例を示すもので、1れ試鹸装履、2,2’ハウエハー
プローバ、3はマイクロコンビエータ等で構成される処
理装置、4は時刻を計数する装置つまり時計、5はコン
ソール、6は表示装置でちる。動作を説明すnば次のと
&粉である、ウェハープローバ2.2′はウェハー上の
各テップの職鹸を試験装置11によって行い、全チップ
の試Ik′に終了すると1ウエハーの試験終了時刻を処
理装−3に送る。、処理I&置3は試験終了信号を受け
た時刻を時fft4より読み取り、前回の賦験終’/ 
(71号の時刻との差、すなわち1枚のウェハーの試験
時間を求める。これを、多らかしめ任意vc指定された
枚数のウェハーについて求めることにより、1枚のウェ
ハーの平均試験時間を割9出す。10ツトの試験作業開
始時に社、コンソール5より、10ツトのウェハ一枚数
等が入力されるので、処理装置3は求めた平均試験時間
よシ、そのロフトの試験終了予定時刻を割り出し、表示
装置6に表示する。また試験終了予定時刻の、任意に設
定される所定の時間前になりたらその所定時間後にその
ロフトの試験が終了することを表示部6に表示す番。
The present invention will be explained below. FIG. 1 shows an embodiment of the present invention, in which 1 is a sample mounting device, 2 is a Hauer prober, 3 is a processing device composed of a micro combinator, etc., and 4 is a device for counting time. In other words, the clock, 5 is the console, and 6 is the display device. To explain the operation, the wafer prober 2.2' tests each step on the wafer using the testing device 11, and when all the chips have been tested Ik', the test for one wafer is completed. Send the time to processing device-3. , processing I & position 3 reads the time when the test end signal was received from time fft4, and determines the end of the previous test '/
(Calculate the difference from the time in No. 71, that is, the test time for one wafer. By calculating this for the number of wafers specified by arbitrary vc, divide the average test time for one wafer. At the start of the 10 test work, the number of 10 wafers, etc. is input from the console 5, so the processing device 3 calculates the scheduled end time of the test for that loft based on the obtained average test time. It is displayed on the display unit 6. Also, when a predetermined time that is arbitrarily set before the scheduled test end time is reached, a number is displayed on the display unit 6 to indicate that the test for that loft will end after that predetermined time.

このように簡単な装置を付加することにより、終了時刻
を予告することが可能となる。本発明では時刻の予告を
行うのに、実績試験時間を遂次求めることによシ行うの
で、試験品種が変わっても、また他方のウェハープロー
パにおける試験品種がどう変わっても差しつかえない。
By adding such a simple device, it becomes possible to give advance notice of the end time. In the present invention, the time is announced by successively determining actual test times, so it does not matter how the test product changes or the test product in the other wafer proper.

なお、本実施例では、時刻の予告を行うための処理装置
3を試験装置1およびウェハープローパ2,2′と別に
扱ったが、一般に試験装置やウェハープローバ等の)〜
ンドリング装置はマイクロコンビエータあるいはミニコ
ンビエータ等によシ制御されておシ、処理装置3はその
コンビエータによって代用されうろことは明らかである
In this embodiment, the processing device 3 for giving advance notice of the time is treated separately from the test device 1 and the wafer probers 2, 2', but generally speaking
It is clear that the handling device may be controlled by a micro combinator or a mini combinator, and the processing device 3 could be replaced by the combinator.

また以上ウェハーブロービング試験の場合に9いて説明
したが、ウエノ・−プローバを製品のノ・ンドリング装
置とし、1ウニノー−の試験終了信号を1個の製品の試
験終了信号で、またウエノ・一枚数を製品個数で扱えば
製品の検−牽システムにも適用可能である。
In addition, as explained above in the case of the wafer roving test, the Ueno prober is used as a product nodding device, and the test end signal for one product is used as the test end signal for one product. If the number of sheets is treated as the number of products, it can also be applied to product inspection and checking systems.

以上説明したように、本発明によれば試験作業の終了時
刻を予告することが可能であり、これにより、高価な検
査設備の稼動率の向上が期待されまた計画的な試験作業
が可能となり、生産性の大きな向上が期待される。
As explained above, according to the present invention, it is possible to give advance notice of the end time of test work, which is expected to improve the operating rate of expensive testing equipment, and also enables systematic test work. A significant improvement in productivity is expected.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック図である。 同、図において、l・・・・・・試験装置、2.2’・
・・・・・クエハープローバ、3・・・・・・処理装置
、4・・・・・・時刻針数装置(時計)、5・・・・・
・コンソール、6・・・・・・表示装置である。 代理人 弁理士  内 原   晋
FIG. 1 is a block diagram showing one embodiment of the present invention. In the same figure, l... test device, 2.2'...
...Quehar prober, 3...Processing device, 4...Time hand count device (clock), 5...
- Console, 6...Display device. Agent Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】[Claims] 試験装置と被試験物のハンドリング装置等によって構成
される検査システムにおいて、個々の被試験物の試験時
間を計数する手段と、あらかじめ設定された被試験物の
数量と前記試験時間を基にして被試験物全体の試験終了
時刻を予告する手段とを具備することを特徴とする検査
システム。
In an inspection system consisting of a test device, a device for handling test objects, etc., there is a means for counting the test time for each test object, and a means for counting the test time for each test object, and a means for counting the test time for each test object, and counting the test time based on a preset number of test objects and the test time. An inspection system characterized by comprising: means for notifying the end time of the test for the entire test object.
JP56129675A 1981-08-19 1981-08-19 Inspecting system Granted JPS5831549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56129675A JPS5831549A (en) 1981-08-19 1981-08-19 Inspecting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56129675A JPS5831549A (en) 1981-08-19 1981-08-19 Inspecting system

Publications (2)

Publication Number Publication Date
JPS5831549A true JPS5831549A (en) 1983-02-24
JPS6229901B2 JPS6229901B2 (en) 1987-06-29

Family

ID=15015381

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56129675A Granted JPS5831549A (en) 1981-08-19 1981-08-19 Inspecting system

Country Status (1)

Country Link
JP (1) JPS5831549A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01291440A (en) * 1988-05-18 1989-11-24 Tokyo Electron Ltd Wafer prober

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01291440A (en) * 1988-05-18 1989-11-24 Tokyo Electron Ltd Wafer prober

Also Published As

Publication number Publication date
JPS6229901B2 (en) 1987-06-29

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