JPH01203983A - Ic test system - Google Patents

Abstract

PURPOSE:To shorten the time to make a device test by making the operation at the same time if settlement contents for a condition, specification, etc., of an I.C. test program are the same, and if the settlement contents are different, making the operation with the programming part corresponding to each station. CONSTITUTION:In case the settlement contents for the condition, specification and measurement of the I.C. test program 2 which is performed at each of 1st and 2nd stations 3, 4 are the same, each station 3, 4 is made to be operated at the same time respectively. If any of the settlement contents is different, the program 2 is used, which is provided with a sequence such as each station is made to operate with the programming part corresponding to each station. With this arrangement, the testing time can be shortened in case of making the device test at the different stations.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC test system used when testing an IC, and particularly to test programming for creating a program for the IC test system.

[Conventional technology]

FIG. 4 is a conceptual diagram showing a conventional IC test system described in the catalog of the IC tester 8000 series manufactured by Anjo Denki Co., Ltd. In the figure, l is the tester main body, 3 is the first station, and 4 is a second station, and 5 to 8 are first to fourth ICs under test (DUT), respectively. Further, 9 is a DUT program at the first station 3, and 10 is a DOT program at the second station 4, which are stored in the IC memory of the tester main body. Further, FIG. 5 shows parallel measurement operation blocks within each station, where time≠yard.

Next, the operation will be explained.

The tester is assigned an appropriate program depending on the Ic to be tested at that station. For example, the program 9 is applied to the first station 3 and the program 10 is applied to the second station 4, and the first to fourth DUTs 5 to 8 are tested based on the contents of each program. . At this time, irrespective of the type of DUTs 5 to 8, if the measurement conditions etc. differ, the programs used at the station will be different. As shown in FIG. 5, if the programs at the first station 3 and the second station 4 are different, only one of the programs will run within the same time TI, and the program at the first station 3 and the second station 4 will run within the same time TI. the second DUT or the third. 4th DU
Only either T is tested.

[Problem to be solved by the invention]

Conventional IC test system programs operate as described above, so when stations have different measurement conditions, each program must be run in completely different times from start to end. They had to be tested at different times regardless of whether there were any common parts within them. Therefore, there has been a problem in that it becomes an obstacle to shortening the test time, that is, improving the processing ability of the tester.

This invention was made to solve the above-mentioned problems.If there are common parts in each program, the DUTOs that are tested within the same time can be integrated into a single program including those parts. It is an object of the present invention to provide an IC test system operated by test programming that can increase the number of ICs, thereby shorten the test time per IC, and improve the throughput of a tester.

[Means to solve the problem]

An IC test system according to the present invention has a plurality of test stations and tests a semiconductor integrated circuit. A common program for each station that has a processing routine to determine whether the IC test program should be applied to each station, and that operates each station at the same time when the conditions, standards, and measurement settings of the IC test program performed at each station are the same. part and
This program consists of a sequence of program parts corresponding to the respective stations that operate the respective stations when any of the above settings differ.

[Effect]

In this invention, the program includes a program part common to each station that operates each station simultaneously when the conditions, standards, and measurement settings of the tC test program performed at each station are the same, and a program part common to each station that operates the tC test program at the same time. Since the system is provided with a sequence of program parts corresponding to each station that operates each station when one of them is different, the test time per IC is shortened and the throughput of the tester is improved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an IC test system according to an embodiment of the present invention. In the figure, 1 is a tester body, 2 is a program, 3 is a first station, 4 is a second station, and 5 to 8 are The 1st to 4th DUTs (ICs under test) are measured. Figure 2 is a chronological diagram of how the first to fourth DUTs 5 to 8 are measured in each station when the program is run. It is a diagram. TI is the time from the start to the end of the program, and Tt is the time during which the portion of the program common to the first station 3 and the second station 4 is running.

FIG. 3 is a flowchart representing the operations in the program.

Next, the effect will be explained.

Conventionally, within test time T1, the first. the second DUT or the third. Only one of the fourth DUT was tested, but during the program, the first. Second
When there is a common part between stations 3 and 4, as shown in FIG. 2, for example, the program is first run to test only the first and second DUT (that is, the first station) side. Next is the third program. 4th OU
Test only the T (second station) side, and when you come to the common area, test the first station at time T2. Second. Third. 4th DU
Test T at the same time. The following will also be tested separately and the program will end.

The program that executes the above operations operates as shown in FIG. In other words, there is a branch in the program, and the first... By giving something like a FLAG number to each of the second stations in advance and detecting it in a branch, the program portion to be run next is assigned. By doing this as many times as necessary, the partially parallel measurement program that was initially expected can be executed.

As described above, in this embodiment, in the IC test system, if the conditions, standards, and measurement settings of the IC test program performed at each station are the same, each station can perform the test at the same time; Since the program is operated using a program that has a sequence for operating each station in the program section corresponding to each station, it is possible to execute a program for partially parallel measurement, reducing the test time per IC ( The processing capacity of the tester can be improved.

In the above embodiment, there are two stations and the number of DUTs in each station is two, but the number of stations and the number of DUTs may be three or more, and the same effect as in the above embodiment can be obtained. .

〔Effect of the invention〕

As described above, according to the present invention, the conditions of the IC test program performed at each station.

If the standard and measurement settings are the same, use a program that has a sequence that operates each station at the same time, and if any of the above settings differ, use a program section that corresponds to each station. The system is configured to shorten the test time when testing devices at different stations, which can be expected to improve the productivity of the equipment.It also has the effect of reducing the program size and making effective use of the tester's memory capacity. be.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an IC test system according to an embodiment of the present invention, and FIG. 2 shows a program used in this embodiment.
Fig. 3 is a flowchart showing the operation of the program used in this example, and Fig. 4 is a diagram illustrating the state in which the DUT is measured in each station in chronological order. FIG. 5 is a conceptual diagram showing the IC test system of 2005, and FIG. 5 is a time chart showing parallel measurement operation blocks in each station in a conventional tester. 1 is the tester body, 2 is a program, 3 is a first station, 4 is a second station, and 5 to 8 are first to fourth DUTs (ICs to be measured). Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In an IC test system that has multiple test stations and tests semiconductor integrated circuits, the program for operating the IC test system must determine which station or multiple stations the following commands should be applied to. A program part common to each station that has a processing routine for making judgments and operates each station simultaneously when the conditions, standards, and measurement settings of the IC test program performed at each station are the same, and the above settings. 1. An IC test system comprising a sequence of program parts corresponding to respective stations that operate the respective stations when any of the above differs.