JPH02310478A - Semiconductor inspecting device - Google Patents

Abstract

PURPOSE:To reduce an inspecting time and to perform an effective inspection by performing a measuring action for a unit to be inspected such as an LSI, etc., and arithmetic processing by plural arithmetic processing units which independently act with each other in parallel. CONSTITUTION:In a CPU 1, a measuring condition fixed corresponding to a type of the unit to be measured 6 is written in a measuring condition memory 2 and also the evaluation of the inspection is performed on the basis of arithmetic results obtained from an arithmetic processing part 7 and an arithmetic results memory 8 through a system bus 91. And the arithmetic processing part 7 is constituted of the arithmetic processing units 71, 72...7n which independently act with each other, and the arithmetic processing for the results measured by a measuring system hard ware device 3 given through a measured results memory 4 is performed stepwise. And the measuring action by the device 3 and the arithmetic processing for the measured results by the processing part 7 are simultaneously and independently performed, so that the whole inspecting time drastically is reduced and the inspection of an LSI, etc., necessitating the complicated arithmetic processing effectively is performed.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a technique that is effective when applied to semiconductor inspection equipment and inspections that require arithmetic processing. It is related to effective technology that can be used for.

[Prior Art] In general, at semiconductor device manufacturing sites, there is a great concern as to how efficiently product inspection performed at the final stage of the process can be performed. Especially linear IC or LSI
In fields such as those that require complex tests or multi-item inspections, there is a strong demand for faster inspections.

Therefore, conventionally, as shown in FIG. 2, an inspection device automated using a computer has been provided.

The inspection device shown in FIG.
(Central processing unit) l', a measurement condition memory 2 that stores various measurement conditions given from this CPU 1' via the system bus 5, and a unit to be inspected ( That is, a measurement hardware device 3. that performs the measurement of IC) 6. This measuring hardware device! ! The measurement result memory 4 stores the measurement data obtained in step 3.

A series of operations for inspection are performed sequentially under the control of the CPUI'. First, measurement conditions are written into the measurement condition memory 2 via the system bus 5 from the CPUI'. When writing of the measurement conditions is completed, next, the measurement system hardware device 3 writes the ill'l written to the measurement condition memory 2.
The unit to be inspected 6 is measured according to the specified conditions. In this measurement, for example, a specified voltage or current is applied and the response at that time is measured.The obtained measurement data is written into the measurement result memory 4. When the measurement has finished, the CPU 1' reads out the measurement data written in the measurement result memory 4 via the bus 2, and performs predetermined arithmetic processing on the read measurement data.

Based on the result of this arithmetic processing, it is determined whether or not the unit to be inspected 6 has predetermined characteristics.

As described above, inspections of units to be inspected such as linear ICs or LSIs were carried out (for example, Signs Forum Co., Ltd. November 2, 1981)
Published on the 8th, “Very LSI Device Handbook JP, 27
0-273 Measurement results Memory tester type, p3412
, 413 Measurement Results Memory Testers and Testing Techniques)
.

[Problems to be Solved by the Invention] However, the inventors have found that the above-mentioned technique has the following problems.

In other words, the conventional inspection equipment described above has had some success in improving inspection efficiency by controlling a series of inspection operations using a computer, but linear IC or LS
There remained dissatisfaction with the speed when inspecting items such as I.

This is because the above-mentioned conventional inspection apparatus performs the measurement operation by the measurement hardware device and the arithmetic processing of the measurement results at separate times.

In other words, since the configuration was such that calculation processing of the measurement results was performed after waiting for the measurement operation by the measurement hardware device 3 to be completed, the overall inspection time was the sum of the time required for the measurement operation and the time required for calculation processing. The inventors of the present invention have clarified that this becomes a major impediment to increasing the speed of inspection, resulting in N.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique that enables testing of linear ICs, LSIs, etc., which require complex tests or multi-item tests, to be performed efficiently in a short period of time.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a measurement hardware device that measures the unit to be inspected according to predetermined measurement conditions, and arithmetic processing that processes the measurement results of the measurement hardware device step by step using a plurality of processing units that operate independently of each other. The calculation process for the H11 constant results is performed in parallel with the measurement operation, and the complicated calculation procedure is distributed to a plurality of calculation processing units.

[Operation] According to the above-mentioned means, the measurement operation and the arithmetic processing of the measurement results can be executed simultaneously, and complex arithmetic procedures are also processed in parallel by multiple arithmetic processing units, so that the overall Inspection time can be significantly shortened.

This allows linear ICs that require complex arithmetic processing to
Alternatively, the purpose of making it possible to test LSIs and the like efficiently in a short period of time is achieved.

[Embodiments] Five preferred embodiments of the present invention will be described below with reference to the drawings.

In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a semiconductor inspection device to which the technology of the present invention is applied, in which 1 is a CPU (central processing system) that centrally controls the entire inspection device, and 2 is a CPU that controls the measurement conditions. 3 is a measurement system hardware device that measures the unit to be inspected 6 according to the measurement conditions stored in the measurement condition memory 2; 4 is a measurement result memory that stores the measurement results of the measurement system hardware device 3; , 7 is an arithmetic processing unit that processes the measurement results stored in the measurement result memory 4, 8 is an arithmetic result memory that stores the arithmetic results of the arithmetic processing unit 7, and 91 is a CPU, the arithmetic processing unit 7, and the arithmetic result memory 8. system bus, 9, which connects
2 is a local bus that connects the measurement condition memory 2 and the measurement system hardware device 3;

A local bus 93 connects the measurement hardware device 3 and the measurement result memory 4.

Here, the CPU writes predetermined measurement conditions according to the type of the unit under test 6 into the measurement condition memory 2, and also writes the calculation results obtained from the calculation processing section 7 and calculation result memory 8 via the system bus 91. An inspection processing unit that performs inspection evaluation based on the above is formed. This CPUI is configured using a general-purpose information processing device that is a microcircuit, so-called a microcomputer.

The arithmetic processing unit 7 includes a plurality of arithmetic processing units 71, 72 . . . 7n, and performs arithmetic processing on the measurement results of the measurement system hardware device 3 given via the measurement result memory 4 in stages. Each arithmetic processing unit 71 to 7n is connected to a system bus 9.
1 and operate independently while maintaining a certain synchronization relationship with each other. Thereby, the measurement results stored in the measurement result memory 4 are divided into a plurality of simple calculation elements and are sequentially processed. Along with this, each arithmetic processing unit 71 to 7n has a data memory 1.
1. This data memory 11 mediates the transfer of operation data and intermediate results of operation to the system bus 91 for each operation processing unit.

Next, the operation will be explained.

First, measurement conditions are written into the measurement condition memory 2 from the CPU via the system bus 91.

According to the written measurement conditions, the measurement hardware device 3 measures the unit to be inspected 6. In this measurement,
For example, the response voltage or current when a reference voltage is applied is measured. The measurement results (measurement data) of the measurement hardware device 3 are sequentially written into the measurement result memory 4.

When a predetermined measurement result (data) is stored in the measurement result memory 4, the arithmetic processing unit 7 reads the stored data 11111J.
Read the fixed results and process them. This arithmetic processing is divided into simple arithmetic elements and sequentially executed by a plurality of arithmetic processing units 71 to 7n.

In this case, calculation data (for example, constants) required by each calculation processing unit is written in advance from the CPU 1 to the data memory 11 for each calculation processing unit via the system bus 91. The calculation results distributed and processed by the plurality of calculation processing units 71 to 7n are
The calculation result is temporarily stored in the memory 8.

The CPUI reads out the calculation results stored in the calculation result memory 8 via the system bus 91.

Furthermore, it is possible to store the intermediate results obtained for each arithmetic processing unit in the data format provided for each arithmetic processing unit.
Read from memory 11 via system bus 91. Based on the calculation results read out in this manner, the inspection and evaluation of the unit to be inspected 6 is performed.

As above, install the measurement system hardware! ! The measurement operation by 3 and the arithmetic processing of the measurement results by the arithmetic processing unit 7 are executed simultaneously and independently of each other.

At the same time, complex arithmetic processing procedures are processed in parallel by the plurality of arithmetic processing units 71 to 7n, thereby making it possible to significantly shorten the overall inspection time. As a result, testing of linear ICs, LSIs, etc. that require complex arithmetic processing can be performed efficiently in a short time.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. None).

For example, the arithmetic processing unit may be configured using a memory that stores arithmetic input data and integrated output data in a table format, a so-called arithmetic memory.

In the above description, the invention made by the present inventor was mainly applied to the inspection of linear ICs, which is the background of the invention.

The present invention is not limited thereto, and can be applied to, for example, the inspection of discrete circuit boards.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, it is possible to efficiently test linear ICs or LSIs that require complex arithmetic processing in a short period of time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor testing device to which the technology of the present invention is applied, and FIG. 2 is a block diagram showing an example of the configuration of a conventional semiconductor testing device. 1...CPU (central processing unit), 2...Measurement condition memory, 3...Measurement system hardware device, 4...
・Measurement result memory, 6...Unit to be inspected, 7.
...Arithmetic processing unit, 8...Arithmetic result memory, 91
...System bus, 92.93...Local bus.

Claims (1)

[Claims] 1. A measurement hardware device that measures the unit under test according to predetermined measurement conditions, and a plurality of arithmetic processing units that operate independently of each other to process the measurement results of the measurement hardware device step by step. 1. A semiconductor inspection device comprising: an arithmetic processing unit that performs arithmetic processing; and an inspection processing unit that performs an inspection evaluation of the unit to be inspected based on the calculation result of the arithmetic processing unit. 2. A measurement condition memory that stores predetermined measurement conditions, a measurement hardware device that measures the unit under test according to the measurement conditions stored in this measurement condition memory, and a measurement device that stores the measurement results of this measurement hardware device. A result memory, an arithmetic processing unit that performs step-by-step arithmetic processing on the measurement results stored in the measurement result memory by a plurality of arithmetic processing units that operate independently of each other, and a measurement result that stores the arithmetic results of this arithmetic processing unit. 2. The semiconductor inspection apparatus according to claim 1, further comprising a memory and an inspection processing section that performs inspection and evaluation of the unit to be inspected based on the calculation results of the processing section. 3. Each of the plurality of arithmetic processing units operates independently while maintaining a certain synchronization relationship with each other according to a program provided via a system bus, and
3. A semiconductor inspection device according to claim 1, further comprising a data memory for transferring calculation data and intermediate results of calculation via a system bus.