JPH0540595Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input control circuit for a phase comparator, and more particularly to an input control circuit for a phase comparator configured to provide a ternary output according to a phase difference between two input signals.

When reproducing recorded video information, it is necessary to detect and correct the time axis error of the reproduced signal. To do this, it is necessary to detect the phase difference between the horizontal synchronization signal in the reproduction signal and the reference horizontal synchronization signal. A phase comparator is used to obtain a time base error signal.

This phase comparator has a circuit having the configuration shown in FIG.
Reference signal B input to inverters 11 and 12
A three-value output is generated according to the phase difference between the signal A and the reproduced horizontal synchronization signal A. A reproduced horizontal synchronizing signal, a reference signal, and a phase comparison output signal are shown in FIGS. 2A to 2C, respectively, and are examples in which the reproduced horizontal synchronizing signal is in a phase lead state than the reference signal. That is, the output C falls at the rising edge of the reproduced horizontal synchronizing signal A, and rises at the rising edge of the reference signal B. Therefore, a comparison output C is obtained which has a polarity that corresponds to the polarity of the phase difference between both input signals and a pulse width that corresponds to the magnitude of the phase difference.Furthermore, when the phase difference is zero, Output C
maintains the zero level and assumes a so-called three-value output state. Note that the details of this circuit are well known and will not be explained here.

Here, if the reproduced horizontal synchronization signal A is missing as shown in FIG. 3, the polarity of the phase difference signal will subsequently be reversed as shown in FIG. C, and it will no longer indicate an accurate phase difference. Therefore, there is a drawback that it is impossible to correct the time axis of the reproduced signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input control circuit for a phase comparator that can make subsequent comparison outputs normal even if there is a loss of input of a reproduced horizontal synchronizing signal.

The input control circuit according to the present invention is an input of a phase comparator that generates a comparison output having a polarity corresponding to the polarity of a phase difference between an input signal and a reference signal and a pulse width corresponding to the magnitude of the phase difference. a control circuit, when detecting that the input signal does not exist for a predetermined period of time, a loss detection signal generating means that generates a loss detection signal until the input signal arrives again; gate means for prohibiting input of the reference signal to the phase comparator in accordance with the omission detection signal; pulse signal generation means for generating a pulse signal in response to the omission detection signal; The input signal is relayed to the phase comparator, and while the pulse signal is being generated, the input signal is inverted in polarity and relayed to the phase comparator.

The present invention will be explained below based on the drawings.

FIG. 4 is a circuit diagram of an embodiment of the present invention, in which the reproduced horizontal synchronization signal A serves as a trigger input of a retriggerable monostable multivibrator (hereinafter abbreviated as RMV) 1 and as one input of an exclusive OR gate 2. It's summery. Output B of this RMV1 is a monostable multivibrator (hereinafter referred to as
(abbreviated as MMV) 3, and the output C of this MMV3 serves as the other input to the OR gate 2 mentioned above. On the other hand, a two-input AND gate 4 is provided, to which the reference horizontal synchronizing signal E and the output B of the RMV1 are input. This and gate 4
The output F of the OR gate 2 and the output D of the OR gate 2 become comparison inputs of the phase comparator 5. This phase comparator 5
is the same as the circuit configuration shown in FIG. FIG. 5 is a waveform diagram illustrating the operation of the circuit in FIG. 4,
5A to 5G show respective signals A to G in FIG. 4, respectively. Note that G is the comparison output of the phase comparator 5. As shown in FIG. 5A, if the reproduced horizontal synchronization signal is missing by, for example, 2H (H indicates one horizontal scanning period), the RMV1 detects this loss and generates a low-level detection signal shown in B. . That is,
RMV1 is a retriggerable type of MMV with a time constant of 1H or slightly larger than 1H, so it maintains a high level output while the normal playback horizontal synchronization signal arrives, but only one pulse The loss of the output causes the output to flip to a low level.
This low level detection signal will appear until the arrival of the next reproduction horizontal synchronization pulse. The MMV 3 is triggered by the timing of this detection signal B and outputs the timing signal shown in FIG.

Since this timing signal C and the reproduced horizontal synchronizing signal A are applied to the two inputs of the exclusive OR gate 2, this timing signal A is obtained at the gate output together with the reproduced horizontal synchronizing signal as shown in Figure D. This is 1 of the phase comparator 5.
It becomes an input.

Since the gate 4 is closed during the existence period of the missing detection signal B by the RMV1, the gate output has a waveform in which the passage of the reference signal E is prohibited during that period, as shown in F, and this becomes the other input of the phase comparator 5. It is used as a reference signal.

In the phase comparator 5, the reproduced horizontal synchronization signal D
Since a pulse that rises at the rising edge of the falling reference signal F is obtained, the phase comparison output as shown in FIG. G is obtained. That is, in a period where the input signal is missing, one pulse b (see FIG. 5
reference) is generated. Therefore, the phase comparator 5 is reset by the timing signal a and thereafter controlled so as to be able to generate a correct phase comparison output. Therefore, as soon as the input signal missing period is passed, the device starts operating from the initial state, so that there will be no further malfunctions.

The timing chart in Fig. 5 shows an example in which the reproduced horizontal synchronizing signal is in a phase-advanced state compared to the reference signal, but in contrast, Fig. 6 A to G show cases in which the horizontal synchronizing signal is in a phase-lag state. This is an example. In this example as well, the phase comparator is reset to the initial state by the timing signal a, thereby preventing malfunction.

7A to 7G are waveform diagrams of various parts when the input signal A is delayed in phase with respect to the reference signal E, and when the missing section of the input signal A is clamped at a high level.

As described above, according to the present invention, the state of the phase comparator is reset to the initial state in response to a loss of an input signal, thereby enabling so-called automatic recovery, so that malfunctions after a period of loss can be prevented.

It is clear that the present invention can be used not only as a phase comparator for detecting a time axis error in a reproduced signal of a reproduction device, but also as a variety of other phase comparators.
Furthermore, the circuit examples shown in FIGS. 1 and 2 are not limited thereto.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of a well-known phase comparator circuit used in the present invention, Figs. 2 and 3 are timing charts explaining the operation of the circuit in Fig. 1, and Fig. 4 is an embodiment of the present invention. The circuit diagrams of FIGS. 5 to 7 are timing charts showing the operation of the circuit of FIG. 4. Explanation of symbols of main parts, 1...RMV, 2...
Exclusive or Gate, 3...MMV, 4
...and gate, 5...phase comparator.

Claims (1)

[Claims for Utility Model Registration] An input of a phase comparator that generates a comparative output having a polarity corresponding to the polarity of the phase difference between the input signal and the reference signal and a pulse width corresponding to the magnitude of the phase difference. A control circuit, when detecting that the input signal does not exist for a predetermined period of time, a loss detection signal generating means that generates a loss detection signal until the input signal arrives again; gate means for prohibiting input of the reference signal to the phase comparator in accordance with the omission detection signal; pulse signal generation means for generating a pulse signal in response to the omission detection signal; while the pulse signal is not being generated; An input control circuit comprising relay means for relaying the input signal to the phase comparator, and inverting the polarity of the input signal while the pulse signal is being generated, and relaying the polarity of the input signal to the phase comparator. .