JPH0536742A - Resin sealing method for electronic components - Google Patents

Resin sealing method for electronic components

Info

Publication number
JPH0536742A
JPH0536742A JP21427091A JP21427091A JPH0536742A JP H0536742 A JPH0536742 A JP H0536742A JP 21427091 A JP21427091 A JP 21427091A JP 21427091 A JP21427091 A JP 21427091A JP H0536742 A JPH0536742 A JP H0536742A
Authority
JP
Japan
Prior art keywords
resin
high voltage
partitioning
jig
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP21427091A
Other languages
Japanese (ja)
Inventor
Kingo Kayano
欽呉 茅野
Tsukasa Matsuzawa
主 松沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP21427091A priority Critical patent/JPH0536742A/en
Publication of JPH0536742A publication Critical patent/JPH0536742A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
  • Casting Or Compression Moulding Of Plastics Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To provide a resin sealing method for electronic components which is capable of reducing stress produced on sealing resin. CONSTITUTION:A partitioning jig 30 is mounted on a high voltage IC 14, which is divided into a plurality of blocks. The partitioning jig 30 comprises a partitioning board 32 which divides the high voltage IC 14 and a supporting board 34 which supports the partitioning board 32 and formed with 'Teflon(R)'. To resin-seal the high voltage IC 14, epoxy resin 24 is potted at first for each block. After the resin 24 is heated and cured, the partitioning jig 30 is removed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、たとえば、静電プリン
タや静電プロッタの静電記録ヘッド等に使用される長尺
状の基板に搭載された半導体素子等の電子部品を樹脂封
止する方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention seals an electronic component such as a semiconductor element mounted on a long substrate used in an electrostatic recording head of an electrostatic printer or an electrostatic plotter with resin. It is about the method.

【0002】[0002]

【従来の技術】静電プリンタや静電プロッタは、静電記
録ヘッドにより静電記録紙に静電潜像を形成し、これを
トナーを使って顕像化し、定着することにより印刷す
る。これらの装置に使用される静電記録ヘッドは、図3
に示すように表面及び裏面に多数の記録用電極52が形
成された基板50の先端部を樹脂封止することによりサ
イドプレートを形成し、先端を研磨仕上げすることによ
って得られる。また、この基板50の両面には、ハイボ
ルテージ用IC54と駆動用共通電源基板56とが搭載
されている。
2. Description of the Related Art An electrostatic printer or an electrostatic plotter forms an electrostatic latent image on an electrostatic recording paper by an electrostatic recording head, visualizes it with toner, and fixes it to print. The electrostatic recording head used in these devices is shown in FIG.
As shown in FIG. 5, the side plate is formed by resin-sealing the tip of the substrate 50 on which a large number of recording electrodes 52 are formed on the front and back surfaces, and the tip is polished and finished. A high voltage IC 54 and a drive common power supply board 56 are mounted on both sides of the board 50.

【0003】ところで、大型の静電プロッタ、たとえ
ば、A0サイズの用紙に印刷する装置の場合、基板の長
手方向の幅が約1mにもなり、この間に片面で7200
本、表裏両面で合計14400本もの記録用電極52が
形成される。これに伴い、記録用電極52に高電圧を印
加するためのハイボルテージ用IC54も基板50上に
高密度で多数実装される。
By the way, in the case of a large electrostatic plotter, for example, an apparatus for printing on A0 size paper, the width of the substrate in the longitudinal direction is about 1 m, and 7200 on one side during this period.
A total of 14,400 recording electrodes 52 are formed on both the front and back surfaces. Along with this, a large number of high voltage ICs 54 for applying a high voltage to the recording electrodes 52 are mounted on the substrate 50 at high density.

【0004】[0004]

【発明が解決しようとする課題】上記のように基板50
上に高密度で配置されているハイボルテージ用IC54
を樹脂封止する場合(COB)、エポキシ樹脂等の熱硬
化性樹脂64を個々のハイボルテージ用IC54上に塗
布しようとしても、樹脂が四方に流れてしまうため、図
3に示すように隣合った樹脂同士がひっつき、樹脂64
が一体化してしまう。このため、樹脂を硬化させる際の
樹脂の収縮や、ハイボルテージ用ICの発熱や環境温度
の変化等による樹脂の伸縮により、樹脂に大きな応力が
発生する。この樹脂に生じた大きな応力によって、ハイ
ボルテージ用IC54やボンディングワイヤ72が損傷
したり、基板50が変形したりする。このように従来の
方法では、特に基板上に高密度に配列された半導体素子
等を樹脂封止する場合、問題があった。
As described above, the substrate 50 is used.
High voltage IC54 placed on top with high density
In the case of resin encapsulation (COB), even if an attempt is made to apply thermosetting resin 64 such as epoxy resin onto the individual high voltage ICs 54, the resin will flow in all directions, and as shown in FIG. Resin sticks to each other, resin 64
Will be integrated. Therefore, a large stress is generated in the resin due to the contraction of the resin when curing the resin, the heat generation of the high voltage IC, and the expansion and contraction of the resin due to a change in the environmental temperature. Due to the large stress generated in the resin, the high voltage IC 54 and the bonding wire 72 are damaged or the substrate 50 is deformed. As described above, the conventional method has a problem particularly when the semiconductor elements arranged in high density on the substrate are sealed with resin.

【0005】本発明は上記事情に基づいてなされたもの
であり、封止樹脂に生ずる応力を軽減することができる
電子部品の樹脂封止方法を提供することを目的とするも
のである。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a resin sealing method for electronic components, which can reduce the stress generated in the sealing resin.

【0006】[0006]

【課題を解決するための手段】上記の目的を達成するた
めの本発明に係る電子部品の樹脂封止方法は、基板に配
列された電子部品を樹脂封止する方法において、仕切用
治具で前記電子部品を仕切った後に、樹脂で前記電子部
品を封止し、該樹脂が硬化した後に前記仕切用治具を取
り外すことを特徴とするものである。
A method for resin-sealing an electronic component according to the present invention for achieving the above object is a method for resin-sealing an electronic component arranged on a substrate, using a partitioning jig. After partitioning the electronic component, the electronic component is sealed with a resin, and after the resin is cured, the partitioning jig is removed.

【0007】また、前記仕切用治具をポリテトラフルオ
ロエチレン又は表面をフッ素処理した金属で形成するこ
とが望ましい。
Further, it is desirable that the partition jig is made of polytetrafluoroethylene or a metal whose surface is treated with fluorine.

【0008】[0008]

【作用】本発明は前記の構成によって、仕切用治具で電
子部品を、例えば複数のブロックに仕切った後、各ブロ
ック毎に樹脂封止することにより、各ブロック内の樹脂
が他に流れ出るのを防止する。
According to the present invention, the electronic device is divided into a plurality of blocks, for example, by a partitioning jig, and each block is resin-sealed so that the resin in each block flows out to the other side. Prevent.

【0009】また、仕切用治具をポリテトラフルオロエ
チレンで形成したり、表面をフッ素処理した金属で形成
することにより、仕切用治具は粘着性や摩擦抵抗が低く
なる。
Further, when the partition jig is made of polytetrafluoroethylene or the surface thereof is made of fluorinated metal, the partition jig has low adhesiveness and friction resistance.

【0010】[0010]

【実施例】以下に本発明の一実施例を図1及び図2を参
照して説明する。図1は本発明の一実施例である電子部
品の樹脂封止方法を説明するための図、図2はその電子
部品の樹脂封止方法に使用する仕切用治具の概略斜視図
である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a diagram for explaining a resin sealing method for an electronic component according to an embodiment of the present invention, and FIG. 2 is a schematic perspective view of a partitioning jig used in the resin sealing method for the electronic component.

【0011】図1に示す長尺状の基板10は、静電プリ
ンタや静電プロッタの静電記録ヘッドとして使用される
ものである。基板10の表面には、エッチング法等によ
り高密度に電極12が形成され、この電極12は静電記
録紙に静電潜像を形成するための針電極として利用され
る。また、基板10にはハイボルテージ用IC14と、
駆動用共通電源基板16と、抵抗やコンデンサ等の部品
18とが搭載されている。ハイボルテージ用IC14
は、静電記録紙に静電潜像を形成するために必要な高電
圧を印加するものであり、電極12を高密度に形成した
ことに伴い、基板10の長手方向に多数配列されてい
る。駆動用共通電源基板16にはマトリックス配線が施
されている。ハイボルテージ用IC14はボンディング
ワイヤ22により電極12及び駆動用共通電源基板16
のマトリックス配線と接続されている。
The elongated substrate 10 shown in FIG. 1 is used as an electrostatic recording head of an electrostatic printer or an electrostatic plotter. Electrodes 12 are formed on the surface of the substrate 10 at a high density by an etching method or the like, and the electrodes 12 are used as needle electrodes for forming an electrostatic latent image on electrostatic recording paper. In addition, the substrate 10 has a high voltage IC 14,
A drive common power supply board 16 and a component 18 such as a resistor and a capacitor are mounted. IC14 for high voltage
Is for applying a high voltage necessary for forming an electrostatic latent image on the electrostatic recording paper, and a large number of electrodes 12 are arranged in the longitudinal direction of the substrate 10 due to the high density of the electrodes 12. . Matrix wiring is provided on the common driving power supply substrate 16. The high voltage IC 14 includes the bonding wire 22 for the electrode 12 and the common power supply substrate 16 for driving.
It is connected to the matrix wiring.

【0012】ハイボルテージ用IC14とボンディング
ワイヤ22を保護するために、これらを樹脂24で封止
する必要がある。本実施例の樹脂封止方法では、まず基
板10上のハイボルテージ用IC14に仕切用治具30
を取り付け、ハイボルテージ用IC14を複数のブロッ
クに仕切る。この後、各ブロック毎にエポキシ樹脂等の
熱硬化性樹脂24をポッティングする。
In order to protect the high voltage IC 14 and the bonding wire 22, it is necessary to seal them with a resin 24. In the resin sealing method of this embodiment, first, the partitioning jig 30 is attached to the high voltage IC 14 on the substrate 10.
Is attached and the high voltage IC 14 is divided into a plurality of blocks. Then, a thermosetting resin 24 such as an epoxy resin is potted for each block.

【0013】ここで、本実施例で使用する仕切用治具3
0について説明する。図2に示す仕切用治具30は、ハ
イボルテージ用IC14を複数のブロックに分ける仕切
板32と、仕切板32を支持する支持板34とで構成さ
れ、各ハイボルテージ用IC14をコの字状に仕切って
いる。仕切板32は各ブロックに一個のハイボルテージ
用IC14を含むようにしている。ハイボルテージ用I
C14は直線的に配列されているので、支持板34も基
板10の長手方向の長さと略同じ長さを有する。仕切板
32の下端部には駆動用共通電源基板16と噛み合うよ
うに、段差部32aが設けられている。仕切板32と支
持板34は、それぞれテフロン(ポリテトラフルオロエ
チレン)を用いてテーパ状に形成されている。尚、テフ
ロンは成形性が悪いため、たとえば焼結法等の特別な成
形法を用いている。
The partitioning jig 3 used in this embodiment is as follows.
0 will be described. The partitioning jig 30 shown in FIG. 2 is composed of a partition plate 32 that divides the high-voltage IC 14 into a plurality of blocks, and a support plate 34 that supports the partition plate 32. Each high-voltage IC 14 has a U-shape. It is divided into The partition plate 32 includes one high voltage IC 14 in each block. I for high voltage
Since C14 are linearly arranged, the support plate 34 also has a length substantially the same as the length of the substrate 10 in the longitudinal direction. A step portion 32 a is provided at a lower end portion of the partition plate 32 so as to engage with the drive common power supply board 16. The partition plate 32 and the support plate 34 are each formed in a tapered shape using Teflon (polytetrafluoroethylene). Since Teflon has poor moldability, a special molding method such as a sintering method is used.

【0014】封止樹脂24をポッティングした後は、加
熱して樹脂24を硬化させた後、仕切用治具30を取り
外す。仕切用治具30の材質としてテフロンを使用して
いるので、耐熱性が良いだけでなく、粘着性や摩擦抵抗
が低い。このため、仕切用治具30は、エポキシ樹脂や
シリコーン樹脂等との接着力が非常に弱く、しかも仕切
用治具30がテーパ状に形成されているので、仕切用治
具30を容易に取り外すことができる。このようにし
て、ハイボルテージ用IC14の樹脂封止作業が終了す
る。尚、仕切用治具30は何度でも繰り返し使用するこ
とができる。
After potting the sealing resin 24, the resin 24 is cured by heating, and the partitioning jig 30 is removed. Since Teflon is used as the material of the partitioning jig 30, not only the heat resistance is good, but also the adhesiveness and the friction resistance are low. Therefore, the partitioning jig 30 has a very weak adhesive force with epoxy resin, silicone resin or the like, and the partitioning jig 30 is formed in a tapered shape, so that the partitioning jig 30 can be easily removed. be able to. In this way, the resin sealing work of the high voltage IC 14 is completed. The partition jig 30 can be used repeatedly as many times as desired.

【0015】このように製造された基板10を用いて静
電記録ヘッドを形成するには、たとえば二枚の基板の電
極が形成されていない面同士を対向させ、各基板の電極
が千鳥状になるように接合する。そして、基板10の上
部(電極が形成されている側)にサイドプレートを接着
して、先端を研磨仕上げすることにより、静電記録ヘッ
ドが形成される。
To form an electrostatic recording head using the substrates 10 thus manufactured, for example, the surfaces of the two substrates on which the electrodes are not formed are made to face each other, and the electrodes of the respective substrates are arranged in a zigzag pattern. Join so that. Then, a side plate is adhered to the upper portion of the substrate 10 (on the side where the electrodes are formed), and the tip is polished and finished to form an electrostatic recording head.

【0016】本実施例の電子部品の樹脂封止方法では、
仕切用治具を用いてハイボルテージ用ICを複数のブロ
ックに仕切った後に、各ブロック毎に樹脂封止するの
で、樹脂が隣のブロックに流れ込み、隣合ったブロック
の樹脂同士がひっついて一体的になるのを防止すること
ができる。このため、樹脂を硬化させる際に樹脂が収縮
したり、ハイボルテージ用ICの発熱により樹脂が膨張
したりしても、樹脂に大きな応力が発生することはな
い。したがって、例え熱収縮等により樹脂に応力が発生
しても、その応力により、ハイボルテージ用ICが損傷
したり、ボンディングワイヤが引っ張られて断線した
り、基板が変形したりすることはない。また、樹脂が隣
のブロックに流れ込まないため、確実に電子部品を樹脂
封止することができ、樹脂の無駄を防止することができ
る。さらに、封止樹脂が広がり、一体化することに注意
する必要がなくなるので、樹脂封止作業が簡単になり、
作業の自動化を図ることも可能である。
In the resin sealing method for electronic parts of this embodiment,
After partitioning the high voltage IC into multiple blocks using a partitioning jig, each block is resin-sealed, so the resin flows into the adjacent block, and the resins in the adjacent blocks are stuck together and integrated. Can be prevented. Therefore, even if the resin shrinks when the resin is cured or the resin expands due to heat generation of the high voltage IC, a large stress is not generated in the resin. Therefore, even if stress is generated in the resin due to heat shrinkage or the like, the stress does not damage the IC for high voltage, pull the bonding wire to break the wire, or deform the substrate. Further, since the resin does not flow into the adjacent block, the electronic component can be surely sealed with the resin, and the waste of the resin can be prevented. Furthermore, since it is not necessary to be careful that the sealing resin spreads and is integrated, the resin sealing work becomes easier,
It is also possible to automate the work.

【0017】尚、上記の実施例では、仕切用治具がテフ
ロンを用いて成形されている場合について説明したが、
本発明はこれに限定されるものではなく、金属で形成し
た仕切用治具の表面をフッ素処理してもよい。表面にフ
ッ素処理を施すことによっても粘着性や摩擦抵抗が低く
なり、封止樹脂から仕切用治具を取り外すのが容易にな
る。
In the above embodiment, the case where the partitioning jig is formed by using Teflon has been described.
The present invention is not limited to this, and the surface of the partitioning jig made of metal may be treated with fluorine. The fluorine treatment on the surface also reduces the adhesiveness and frictional resistance, and makes it easy to remove the partitioning jig from the sealing resin.

【0018】また、上記の実施例では、仕切用治具によ
り各ハイボルテージ用ICをコ字状に仕切る場合につい
て説明したが、本発明はこれに限定されるものではな
く、仕切用治具は、たとえば各ハイボルテージ用ICを
四角形に囲むように形成してもよい。このように、ハイ
ボルテージ用ICを完全に囲むことにより、他の部品に
樹脂が付いては困る部分や、まだ後工程を行う必要があ
る部分等に樹脂が流れ出すのを防ぐことができる。
In the above embodiment, the case where each high voltage IC is partitioned into a U shape by the partition jig has been described, but the present invention is not limited to this, and the partition jig is not limited to this. For example, each high voltage IC may be formed so as to surround a square. As described above, by completely surrounding the high voltage IC, it is possible to prevent the resin from flowing out to a portion where the resin does not adhere to other parts, a portion which needs to be subjected to a post process, or the like.

【0019】更に、上記の実施例では、1のブロックで
1のハイボルテージ用ICを仕切る場合について説明し
たが、1のブロックで2個以上のハイボルテージ用IC
を仕切るようにしてもよい。
Further, in the above embodiment, the case where one block divides one high voltage IC has been described. However, one block divides two or more high voltage ICs.
You may partition.

【0020】加えて、上記の実施例では、本発明を静電
記録ヘッドに適用した場合について説明したが、本発明
はこれに限定されるものではなく、多数の半導体素子が
搭載された基板であれば、たとえば静電プリンタ等の記
録ヘッドでなくてもよい。
In addition, in the above embodiment, the case where the present invention is applied to the electrostatic recording head has been described. However, the present invention is not limited to this, and a substrate on which a large number of semiconductor elements are mounted is used. If so, it may not be a recording head such as an electrostatic printer.

【0021】[0021]

【発明の効果】以上説明したように本発明によれば、仕
切用治具を用いて電子部品を樹脂封止したことにより、
樹脂が他に流れ出すのを防止し、所定のブロック毎に樹
脂封止することができるので、樹脂に大きな応力が発生
するのを防止し、封止樹脂の応力による半導体素子等の
電子部品の損傷や、基板の変形を防ぐことができ、した
がって特に高品質の静電プロッタ等の静電記録ヘッドに
搭載した半導体素子等の樹脂封止に好適な電子部品の樹
脂封止方法を提供することができる。
As described above, according to the present invention, since the electronic component is resin-sealed by using the partitioning jig,
Since resin can be prevented from flowing out to other parts and the resin can be sealed in predetermined blocks, it is possible to prevent large stress from being generated in the resin and damage to electronic parts such as semiconductor elements due to the stress of the sealing resin. Also, it is possible to provide a resin sealing method for an electronic component, which can prevent the deformation of the substrate and is therefore particularly suitable for resin sealing of a semiconductor element or the like mounted on an electrostatic recording head such as a high-quality electrostatic plotter. it can.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例である電子部品の樹脂封止方
法を説明するための図である。
FIG. 1 is a diagram for explaining a resin sealing method for an electronic component which is an embodiment of the present invention.

【図2】本実施例の電子部品の樹脂封止方法に使用する
仕切用治具の概略斜視図である。
FIG. 2 is a schematic perspective view of a partitioning jig used in the resin sealing method for electronic components of the present embodiment.

【図3】従来の電子部品の樹脂封止方法を説明するため
の図である。
FIG. 3 is a diagram for explaining a conventional resin sealing method for electronic components.

【符号の説明】[Explanation of symbols]

10 基板 12 電極 14 ハイボルテージ用IC 16 駆動用共通電源基板 18 抵抗等の部品 22 ボンディングワイヤ 24 封止樹脂 30 仕切用治具 32 仕切板 34 支持板 10 substrates 12 electrodes 14 High voltage IC 16 Common power supply board for driving 18 Parts such as resistors 22 Bonding wire 24 Sealing resin 30 Partition jig 32 partition boards 34 Support plate

フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/56 R 8617−4M // B29L 31:34 4F Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 21/56 R 8617-4M // B29L 31:34 4F

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板に配列された電子部品を樹脂封止す
る方法において、仕切用治具で前記電子部品を仕切った
後に、樹脂で前記電子部品を封止し、該樹脂が硬化した
後に前記仕切用治具を取り外すことを特徴とする電子部
品の樹脂封止方法。
1. A method of resin-sealing electronic components arranged on a substrate, wherein after partitioning the electronic components with a partitioning jig, the electronic components are sealed with a resin, and after the resin is cured, A resin sealing method for electronic components, characterized in that a partitioning jig is removed.
【請求項2】 前記仕切用治具をポリテトラフルオロエ
チレン又は表面をフッ素処理した金属で形成した請求項
1記載の電子部品の樹脂封止方法。
2. The resin sealing method for an electronic component according to claim 1, wherein the partitioning jig is made of polytetrafluoroethylene or a metal whose surface is treated with fluorine.
JP21427091A 1991-07-31 1991-07-31 Resin sealing method for electronic components Withdrawn JPH0536742A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21427091A JPH0536742A (en) 1991-07-31 1991-07-31 Resin sealing method for electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21427091A JPH0536742A (en) 1991-07-31 1991-07-31 Resin sealing method for electronic components

Publications (1)

Publication Number Publication Date
JPH0536742A true JPH0536742A (en) 1993-02-12

Family

ID=16652953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21427091A Withdrawn JPH0536742A (en) 1991-07-31 1991-07-31 Resin sealing method for electronic components

Country Status (1)

Country Link
JP (1) JPH0536742A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007335690A (en) * 2006-06-16 2007-12-27 Towa Corp Resin sealing molding method of electronic component

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007335690A (en) * 2006-06-16 2007-12-27 Towa Corp Resin sealing molding method of electronic component

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