JPH0532903B2 - - Google Patents
Info
- Publication number
- JPH0532903B2 JPH0532903B2 JP63132640A JP13264088A JPH0532903B2 JP H0532903 B2 JPH0532903 B2 JP H0532903B2 JP 63132640 A JP63132640 A JP 63132640A JP 13264088 A JP13264088 A JP 13264088A JP H0532903 B2 JPH0532903 B2 JP H0532903B2
- Authority
- JP
- Japan
- Prior art keywords
- hole
- resin
- semiconductor chip
- circuit board
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000011347 resin Substances 0.000 claims description 66
- 229920005989 resin Polymers 0.000 claims description 66
- 239000004065 semiconductor Substances 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 30
- 238000000465 moulding Methods 0.000 claims description 19
- 238000003825 pressing Methods 0.000 claims description 16
- 230000001681 protective effect Effects 0.000 claims description 9
- 238000007789 sealing Methods 0.000 claims description 9
- 239000007788 liquid Substances 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 230000035939 shock Effects 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000001723 curing Methods 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 229910015365 Au—Si Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000005007 epoxy-phenolic resin Substances 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Description
【発明の詳細な説明】
（発明の属する技術分野）
本発明は、混成集積回路（ハイブリツドIC）
の回路基板上に実装される半導体チツプの樹脂モ
ールド方法の改良に関するものである。[Detailed description of the invention] (Technical field to which the invention pertains) The present invention relates to a hybrid integrated circuit (hybrid IC)
This invention relates to improvements in resin molding methods for semiconductor chips mounted on circuit boards.
（従来技術とその問題点）
近年、電子機器の高機能化・小形化・経済化の
要求に対応して、膜回路集積化、混成集積回路化
が進められてきた。この混成集積回路において
は、回路基板上に集積された膜素子のほかに、受
動素子としてリード付部品や面実装部品（チツプ
部品）並びに能動素子として半導体ベアチツプ等
がその基板上に実装される。この半導体ベアチツ
プを回路基板上に直接実装する方法として、ワイ
ヤボンデイング、TAB（Tape Automated
Bonding）、フリツプチツプボンデイングなどが
実用化されている。すなわち半導体ベアチツプを
例えばAu−Si共晶、接着剤、はんだ付けなどに
より基板上にダイボンデイングした後、ベアチツ
プのアルミニウム（Al）電極と基板の導体配線
の電極とが金（Au）またはAlの細線（ワイヤ）
で熱圧着や超音波などによりボンデイングされ
る。(Prior art and its problems) In recent years, membrane circuit integration and hybrid integrated circuits have been promoted in response to demands for higher functionality, smaller size, and economicalization of electronic devices. In this hybrid integrated circuit, in addition to film elements integrated on a circuit board, leaded parts and surface-mounted parts (chip parts) as passive elements, and semiconductor bare chips as active elements are mounted on the board. Wire bonding, TAB (Tape Automated
Bonding), flip-chip bonding, etc. have been put into practical use. That is, after a semiconductor bare chip is die-bonded onto a substrate using, for example, Au-Si eutectic, adhesive, or soldering, the aluminum (Al) electrodes of the bare chip and the electrodes of the conductor wiring on the substrate are bonded to thin gold (Au) or Al wires. (wire)
Bonding is done using heat compression bonding, ultrasonic waves, etc.
このようなワイヤボンデイングの後、裸状の半
導体とワイヤを保護するために、その上からペー
スト状樹脂を塗布し、加熱硬化させるモールドが
なされる。この樹脂モールドの方法には、（）
第５図ａ，ｂに示すように、モールド樹脂５を直
接塗布し硬化する方法や、（）第５図ｃ，ｄに
示すように回転基板１上にペースト状樹脂が流れ
て広がらないように樹脂枠６を設けてその内側へ
モールド樹脂５を塗布して硬化する方法が実施さ
れているが、これらは次のような問題点がある。
（）の方法ではペースト状モールド樹脂５を塗
布した後、加熱硬化時に樹脂が一旦柔らかくなつ
てモールド部分の周囲に流れ広がりワイヤ４が露
出する場合が多く、それを防ぐために塗布量を多
くするため出来上がつた樹脂モールドの底面積が
大きくなる。 After such wire bonding, in order to protect the bare semiconductor and wires, a paste resin is applied thereon and cured by heating to form a mold. This resin molding method includes ()
As shown in FIGS. 5a and 5b, there is a method of directly applying and curing the molding resin 5, and a method of preventing the paste resin from flowing and spreading on the rotating board 1 as shown in FIGS. 5c and d. Methods have been implemented in which a resin frame 6 is provided and mold resin 5 is applied to the inside of the resin frame 6 and cured, but these methods have the following problems.
In method (), after applying the paste molding resin 5, the resin often becomes soft and spreads around the molded part during heating and hardening, and the wire 4 is exposed.To prevent this, the amount of application is increased. The bottom area of the finished resin mold becomes larger.
また、（）の方法では、
樹脂枠６を設けるためのスペースが必要とな
る。 Furthermore, the method () requires a space for providing the resin frame 6.
樹脂枠６は、流動性のあるレジスト樹脂を硬
化して形成するため、そのとき用いる有機溶剤
が残査となつてワイヤ４のポンタビリテイ（ボ
ンデイングの確実さ）が劣化するという品質上
の問題がある。 Since the resin frame 6 is formed by curing a fluid resist resin, there is a quality problem in that the organic solvent used at that time becomes a residue and deteriorates the portability (reliability of bonding) of the wire 4. .
樹脂枠６とモールド樹脂５の熱膨張係数の差
により急激な温度変化によつてモールド樹脂５
に機械的歪みが発生して品質を低下させる危険
性があるなど、耐熱衝撃性に問題がある。 Due to the difference in thermal expansion coefficient between the resin frame 6 and the mold resin 5, the mold resin 5 may
There are problems with thermal shock resistance, such as the risk of mechanical distortion occurring and degrading quality.
樹脂枠６を形成した後、ワイヤボンデイング
するとき枠の高さが装置の正常な動作の障害と
ならないように、樹脂枠６を広げて作られるた
め、仕上がつたモールド部分はモールドがなさ
れるべき面積より広い面積を占有することにな
る。 After forming the resin frame 6, the resin frame 6 is widened to prevent the height of the frame from interfering with the normal operation of the device during wire bonding, so the finished molded part should be molded. It will occupy a larger area than the area.
上記樹脂モールドの方法（）、（）の改良
方法として、封止用マスクを用いる方法があ
る。これは、回路基板のモールド所要部分に対
応する位置に穴が設けられた平板状封止用マス
クを回路基板に載置し、その穴の上から半液状
樹脂を滴下あるいはクリーム状樹脂をスキージ
によつて充填し、加熱硬化処理後、封止用マス
クを取り外す方法である。しかし、この方法で
は、マスクが薄い平板状のため、加熱処理によ
り軟化した樹脂がマスクと回路基板の〓間へ流
れ込む、あるいはスキージによつてクリーム状
樹脂がマスクと回路基板の〓間へ圧入されると
いう難点があり、マスクを外したときモールド
立ち上がり部分に「はみ出し」ができるという
欠点がある。 As an improved method of the above resin molding methods () and (), there is a method of using a sealing mask. This is done by placing a flat sealing mask with holes at positions corresponding to the required parts of the circuit board on the circuit board, and then dripping semi-liquid resin or creamy resin onto the holes using a squeegee. This is a method in which the sealing mask is removed after filling and heat curing treatment. However, in this method, since the mask is thin and flat, resin softened by heat treatment flows into the space between the mask and the circuit board, or creamy resin is press-fitted between the mask and the circuit board using a squeegee. There is a drawback that when the mask is removed, there is a ``protrusion'' in the rising part of the mold.
以上の樹脂モールドの方法以外の保護方法とし
て、セラミツク等により形成された底部のない箱
状の保護キヤツプを接着剤で回路基板に接合する
方法が知られている。しかし、この場合次のよう
な欠点がある。 As a protection method other than the resin molding method described above, a method is known in which a bottomless box-shaped protective cap made of ceramic or the like is bonded to the circuit board with an adhesive. However, this case has the following drawbacks.
１ 回路基板上に保護キヤツプの肉厚のスペース
が必要であり、さらに、接着剤を保護キヤツプ
の接合部分に塗布して回路基板に圧接するとき
の接着剤がはみ出す分の余裕のスペースが必要
である。1. A space for the thickness of the protective cap is required on the circuit board, and additional space is required for the adhesive to squeeze out when applying adhesive to the joint of the protective cap and pressing it onto the circuit board. be.
２ 回路基板と接着剤と保護キヤツプの熱膨張係
数に差があるため、熱衝撃性に問題がある。2. There is a problem with thermal shock resistance because there is a difference in the coefficient of thermal expansion between the circuit board, adhesive, and protective cap.
３ 保護キヤツプの厚さによつて占める回路基板
上の面積および高さが実装密度を上げるための
問題点となる。3. The area and height on the circuit board occupied by the thickness of the protective cap become a problem for increasing the packaging density.
４ 保護キヤツプを取付ける際にワイヤを破損す
る恐れがある。4. There is a risk of damaging the wire when installing the protective cap.
以上説明したように、混成集積回路の部品実装
密度は、回路基板上に占める搭載される実装部品
の底面積の大小の如何にかかつており、上述のよ
うな、半導体チツプの樹脂モールドを形成する従
来の方法、及び保護キヤツプを用いる方法では、
底面積を小さくすることができないので、実装密
度を上げるための大きい問題点であつた。 As explained above, the component mounting density of a hybrid integrated circuit depends on the size of the bottom area of the mounted components on the circuit board. In traditional methods and methods using protective caps,
Since the bottom area cannot be reduced, this is a major problem in increasing the packaging density.
（発明の目的）
本発明の目的は、上述のような従来方法の問題
点を解決し、ワイヤの露出を確実に防止し、耐熱
衝撃性に優れ、かつ、樹脂モールドの占める底面
積を小さくし、かつ、モールド立ち上がり部分に
「はみ出し」がなく、高密度実装に適した形状の
樹脂モールドを形成させることのできる混成集積
回路における半導体チツプの樹脂モールド方法を
提供することにある。(Objective of the Invention) The object of the present invention is to solve the problems of the conventional method as described above, to reliably prevent the wire from being exposed, to have excellent thermal shock resistance, and to reduce the bottom area occupied by the resin mold. To provide a resin molding method for a semiconductor chip in a hybrid integrated circuit, which is capable of forming a resin mold having a shape suitable for high-density packaging without "protrusion" in the rising part of the mold.
（発明の構成）
本発明による混成集積回路における半導体チツ
プの樹脂モールド方法は、混成集積回路の回路基
板上の所定の位置に接着されワイヤボンデイング
された少なくとも１つの半導体チツプと前記ワイ
ヤボンデイングのワイヤとを保護する樹脂モール
ドを形成するために、
前記半導体チツプがワイヤボンデイングされた
回路基板を水平基台上に載置し、該回路基板上の
前記半導体チツプとワイヤとが収容される容積の
穴が設けられ該容積の高さに等しい厚さの封止用
マスクを前記回路基板の上から前記半導体チツプ
と前記穴との位置が合うように載せた後、半液状
の樹脂を前記穴の上から前記半導体チツプと前記
ワイヤとが被われるまで滴下注入し、室温あるい
は高温で前記樹脂を硬化させた後、前記封止用マ
スクを取り外すことにより前記半導体チツプと前
記ワイヤとを保護する樹脂モールドを形成する混
成集積回路における半導体チツプの樹脂モールド
方法において、
前記封止用マスクをシート状弾性体とし該シー
ト状弾性体を前記回路基板の上から前記半導体チ
ツプと前記シート状弾性体に設けられた穴との位
置が合うように載せた後、前記シート状弾性体の
前記穴よりやや大きく該穴の周辺部分を上から押
さえる凸部を有する穴部が設けられた押さえ板を
前記穴と前記穴部の位置が合うように載せて前記
穴が変形しないような力で加圧して前記シート状
弾性体を前記回路基板に圧接し、前記半液状の樹
脂を前記押さえ板の穴部の上から前記半導体チツ
プと前記ワイヤとが被われるまで滴下注入し、室
温あるいは高温で前記樹脂を硬化させた後、前記
シート状弾性体と前記押さえ板を取り外すことに
より前記半導体チツプと前記ワイヤとを保護する
樹脂モールドを形成するようにしたことを特徴と
するものである。(Structure of the Invention) A resin molding method for a semiconductor chip in a hybrid integrated circuit according to the present invention includes at least one semiconductor chip bonded and wire bonded to a predetermined position on a circuit board of a hybrid integrated circuit, and a wire for the wire bonding. In order to form a resin mold that protects the semiconductor chip, a circuit board on which the semiconductor chip is wire-bonded is placed on a horizontal base, and a hole on the circuit board with a volume that accommodates the semiconductor chip and wires is formed. After placing a sealing mask with a thickness equal to the height of the volume on the circuit board so that the semiconductor chip and the hole are aligned, a semi-liquid resin is poured over the hole. Drop injecting until the semiconductor chip and the wire are covered, and after curing the resin at room temperature or high temperature, remove the sealing mask to form a resin mold that protects the semiconductor chip and the wire. In a resin molding method for a semiconductor chip in a hybrid integrated circuit, the sealing mask is a sheet-like elastic body, and the sheet-like elastic body is inserted into holes formed in the semiconductor chip and the sheet-like elastic body from above the circuit board. After placing the sheet-like elastic body so as to be aligned with the holes, a pressing plate provided with a hole slightly larger than the hole of the sheet-like elastic body and having a convex portion that presses the surrounding area of the hole from above is placed between the hole and the hole. The sheet-like elastic body is pressed against the circuit board by applying pressure such that the holes are not deformed, and the semi-liquid resin is applied to the semiconductor from above the holes in the holding plate. A resin mold that protects the semiconductor chip and the wire by injecting the resin dropwise until the chip and the wire are covered, curing the resin at room temperature or high temperature, and then removing the sheet-like elastic body and the holding plate. It is characterized in that it forms a .
以下図面により、本発明を詳細に説明する。 The present invention will be explained in detail below with reference to the drawings.
第１図ａ，ｂは、本発明の実施例を説明するた
めの部分断面図と平面図であり、ａはｂのＡ−Ａ
断面を示している。図において、半導体チツプ２
は混成集積回路の回路基板１の所定の位置に接着
され、金（Au）線などのワイヤ４で半導体チツ
プ２の電極と回路基板１に配設された配線導体電
極３とがワイヤボンデイングされている。第１図
ｂの平面図では回路基板１は図示を省略してあ
り、ワイヤボンデイングの数も４箇所の例を示し
てある。 Figures 1a and 1b are a partial sectional view and a plan view for explaining an embodiment of the present invention, and a and b are A-A in b.
A cross section is shown. In the figure, semiconductor chip 2
is adhered to a predetermined position on the circuit board 1 of the hybrid integrated circuit, and the electrodes of the semiconductor chip 2 and the wiring conductor electrodes 3 disposed on the circuit board 1 are wire-bonded with wires 4 such as gold (Au) wires. There is. In the plan view of FIG. 1b, the circuit board 1 is not shown, and the number of wire bonding is four.
７は本発明の第１の要部をなすシート状弾性体
で、モールド樹脂が付着したり、例えばエポキシ
樹脂やフエノール樹脂などの半液状モールド樹脂
と化学反応を起こさない材質、例えばシリコンシ
ートなどが用いられ、実装された半導体チツプ２
とワイヤ４とをモールドする部分に穴９があけら
れている。この穴９の横断面の大きさと形状は、
実装された半導体チツプ２とワイヤ４とを保護し
得る範囲で、できるだけ小さい底面積を有する形
成予定のモールドの横断面形状に一致する。この
穴９の横断面の形状は、第１図ｂでは角を落とし
た四角形の例を示してあるが、円形あるいは四角
形など、加工や作業が容易でモールド仕上りが良
くなるように任意に決定される。また、シート状
弾性体７の厚さは、半導体チツプ２とワイヤ４が
モールド樹脂で充分被われる高さ、例えば１mm程
度に設定されている。このようなシート状弾性体
７を水平に保持された回路基板１の上にモールド
部分と穴９の位置を合わせて載せられる。 Reference numeral 7 denotes a sheet-like elastic body which constitutes the first essential part of the present invention, and is made of a material such as a silicone sheet, to which the molding resin does not adhere or which does not cause a chemical reaction with the semi-liquid molding resin such as epoxy resin or phenolic resin. Semiconductor chip 2 used and mounted
A hole 9 is made in the part where the wire 4 and the wire 4 are to be molded. The size and shape of the cross section of this hole 9 are as follows:
It corresponds to the cross-sectional shape of the mold to be formed, which has the smallest possible bottom area within a range that can protect the mounted semiconductor chip 2 and wires 4. The cross-sectional shape of this hole 9 is shown as an example of a rectangular shape with rounded corners in FIG. Ru. Further, the thickness of the sheet-like elastic body 7 is set to a height such that the semiconductor chip 2 and the wire 4 are sufficiently covered with the molding resin, for example, about 1 mm. Such a sheet-like elastic body 7 is placed on the horizontally held circuit board 1 with the mold portion and the hole 9 aligned.
８は、シート状弾性体７の上から圧力Ｐで回路
基板１に圧接するための押さえ板であり、本発明
の第２の要部をなすものである。押さえ板８に
は、シート状弾性体７に設けられた穴９よりやや
大きく、しかも穴９の周囲が均一な圧力がかかる
ような形状、例えば第１図ａの凸部１１のような
形状を有する穴１０が設けられている。この押さ
え板８は、シート状弾性体７の上から穴９，１０
の位置が互いにずれないように載せられ、穴９が
変形しないような圧力Ｐで上から押さえられる。
しかも、シート状弾性体７は、回路基板１上に圧
接されたとき回路基板１との間にペースト状モー
ルド樹脂が入り込む隙間があかないように例え
ば、硬さが30〜35（JIS）程度の弾力性を有してい
る。 Reference numeral 8 denotes a pressing plate for pressing the sheet-like elastic body 7 against the circuit board 1 with a pressure P, and constitutes the second main part of the present invention. The pressing plate 8 has a shape that is slightly larger than the hole 9 provided in the sheet-like elastic body 7 and that applies uniform pressure around the hole 9, for example, a shape like the convex portion 11 in FIG. 1a. A hole 10 is provided. This pressing plate 8 has holes 9 and 10 from above the sheet-like elastic body 7.
are placed so that their positions do not deviate from each other, and are pressed from above with a pressure P that does not deform the hole 9.
Moreover, the sheet-like elastic body 7 has a hardness of, for example, about 30 to 35 (JIS) so that there is no gap between the sheet-like elastic body 7 and the circuit board 1 where the paste-like molding resin can enter when it is pressed onto the circuit board 1. It has elasticity.
この状態で、穴９，１０の上から半液状のモー
ルド樹脂をシート状弾性体７の厚さにほぼ等しく
なるまで滴下注入する。次に、その状態のまま室
温あるいは高温でモールド用樹脂を硬化させた
後、シート状弾性体７と押さえ板８とを取り去
る。 In this state, semi-liquid molding resin is dripped from above the holes 9 and 10 until it becomes approximately equal to the thickness of the sheet-like elastic body 7. Next, after the molding resin is cured at room temperature or high temperature in that state, the sheet-like elastic body 7 and the pressing plate 8 are removed.
第２図ｂは、このようにして形成された樹脂モ
ールドの状態を示す平面図であり、ａはそのＡ−
Ａ断面図である。５は硬化の完了したモールド樹
脂であり、本発明の方法によつて、側面が回路基
板１の面に対して垂直に近い立方形のモールド形
状が得られる。しかも、封止用マスクをシート状
弾性体にしたことと、このシート状弾性体の穴の
周辺部分を小さい加重で確実に抑える押さえ板の
凸部の効果とにより、回路基板１とシート状弾性
体７との〓間に高温でゲル化した樹脂が流れ込む
ことがないので、モールドの立ち上がり部分に
「はみ出し」がなく所望の床面積内に仕上げるこ
とができる。 FIG. 2b is a plan view showing the state of the resin mold formed in this way, and a is a plan view of the state of the resin mold formed in this way.
It is an A sectional view. Reference numeral 5 denotes a mold resin that has been completely cured, and by the method of the present invention, a cubic mold shape whose side surfaces are nearly perpendicular to the surface of the circuit board 1 is obtained. Moreover, by using the sheet-like elastic body as the sealing mask and the effect of the convex portion of the pressing plate that reliably suppresses the area around the hole in the sheet-like elastic body with a small load, the circuit board 1 and the sheet-like elastic body are Since the gelled resin at high temperature does not flow into the space between the mold and the body 7, there is no "protrusion" in the rising part of the mold, and the mold can be finished within the desired floor area.
一般の混成集積回路では、半導体チツプ７が複
数個搭載される場合が多く、第２図ｃは、２個の
半導体チツプ２が隣接して実装された場合の樹脂
モールド５の形状を示す断面図である。 In a general hybrid integrated circuit, a plurality of semiconductor chips 7 are often mounted, and FIG. 2c is a cross-sectional view showing the shape of the resin mold 5 when two semiconductor chips 2 are mounted adjacently. It is.
第３図ａ，ｂは本発明の方法で多数のワイヤ４
を有する半導体チツプ２が実装された混成集積回
路の例を示す斜視図である。第３図ａは、隣接す
る３個の半導体チツプ２が他の電子部品と同一面
に実装された完成品の斜視図を示し、第３図ｂは
隣接する２個の半導体チツプ２が上面に実装さ
れ、他の電子部品は裏面（図示省略）に実装され
た完成品の斜視図である。 FIGS. 3a and 3b show that a large number of wires 4 are
FIG. 2 is a perspective view showing an example of a hybrid integrated circuit on which a semiconductor chip 2 having a semiconductor chip 2 is mounted. FIG. 3a shows a perspective view of a completed product in which three adjacent semiconductor chips 2 are mounted on the same surface as other electronic components, and FIG. 3b shows a finished product in which two adjacent semiconductor chips 2 are mounted on the top surface. It is a perspective view of a completed product in which other electronic components are mounted on the back side (not shown).
第４図は、本発明による方法が実際の生産に適
用される場合の概要を示す斜視図である。 FIG. 4 is a perspective view showing an outline of the case where the method according to the present invention is applied to actual production.
一般に、混成集積回路は、品種毎に量産される
場合が多いので、約50mm平方のアルミナ回路基板
上に同一品種の単位基板を複数個、例えば５〜10
個同時に作業ができるように配置して生産能率を
上げ、工程の後半で個別加工、例えばリード付け
工程に至る直前で、単位基板に分割されている。 In general, hybrid integrated circuits are often mass-produced for each type, so multiple unit boards of the same type are placed on an approximately 50 mm square alumina circuit board, for example, 5 to 10 unit boards.
They are arranged so that they can be worked on individually to increase production efficiency, and are divided into unit boards in the latter half of the process, just before the individual processing, for example, the lead attaching process.
第４図では、水平に置かれた基台１５の上に、
上述の回路基板１が固設される。この例では、８
個の単位基板が配置されている。各単位基板に半
導体チツプ２が２個ずつ隣接して実装されてい
る。図ではボンデイングワイヤ、配線導体などは
省略してある。この回路基板１の上から、シート
状弾性体７と押さえ板８を矢印の方向に載せて圧
接し、位置合わせされたそれぞれの穴９，１０内
に半液状モールド樹脂が滴下注入される。図で
は、８個の単位基板毎に実装された２個の半導体
チツプを一つの樹脂モールドで固めるために、シ
ート状弾性体７と押さえ板８には単位基板の数に
対応してそれぞれ８個の穴９および１０が設けら
れている。押さえ板８の穴１０の下側周辺部には
第１図に示したような凸部１１がそれぞれ設けら
れているが図示を省略してある。このようにして
能率よく本発明による方法が実施される。 In FIG. 4, on the base 15 placed horizontally,
The circuit board 1 described above is fixedly installed. In this example, 8
unit boards are arranged. Two semiconductor chips 2 are mounted adjacent to each other on each unit board. In the figure, bonding wires, wiring conductors, etc. are omitted. A sheet-like elastic body 7 and a pressing plate 8 are placed on the circuit board 1 in the direction of the arrow and pressed against each other, and semi-liquid molding resin is dripped into the aligned holes 9 and 10, respectively. In the figure, in order to harden the two semiconductor chips mounted on each of eight unit boards with one resin mold, the sheet-like elastic body 7 and the holding plate 8 each have eight semiconductor chips, corresponding to the number of unit boards. Holes 9 and 10 are provided. Convex portions 11 as shown in FIG. 1 are provided at the lower peripheral portions of the holes 10 of the holding plate 8, but are not shown. In this way, the method according to the invention can be carried out efficiently.
（発明の効果）
以上詳細に説明したように、本発明の樹脂モー
ルド方法を実施することにより、次のような大き
い効果がある。(Effects of the Invention) As explained in detail above, by implementing the resin molding method of the present invention, the following great effects can be obtained.
１ 樹脂モールドの側面が基板の面に対して垂直
に近い形状になり、しかも、「はみ出し」部分
がないため、ワイヤが露出する危険が少ない上
にモールドの底面積が小さいので混成集積回路
の実装密度をさらに高めることができる。1 The sides of the resin mold are nearly perpendicular to the surface of the board, and there are no "protruding" parts, so there is less risk of wires being exposed, and the bottom area of the mold is small, making it easy to mount hybrid integrated circuits. Density can be further increased.
２ 肉厚の樹脂モールドを従来のような枠を設け
ることなく実現できるため、枠を形成する他の
樹脂との熱膨張係数の差による機械的歪が発生
する恐れは全くなく、熱衝撃に強い製品を提供
することができる。2. Because a thick resin mold can be created without the need for a conventional frame, there is no risk of mechanical strain occurring due to the difference in thermal expansion coefficient with other resins that form the frame, and it is resistant to thermal shock. products can be provided.
３ 保護キヤツプを用いる方法に比べて、実装密
度をさらに上げることができ、熱衝撃性に優れ
ている。3. Compared to the method using a protective cap, packaging density can be further increased and thermal shock resistance is excellent.
４ 本発明に用いられるシート状弾性体、押さえ
板のいずれも安価であり、繰り返し使用できる
ので、金型を用いるトランスフアーモールドに
比べて極めて経済的である。4. Both the sheet-like elastic body and the pressing plate used in the present invention are inexpensive and can be used repeatedly, so they are extremely economical compared to transfer molding that uses a metal mold.
第１図は本発明の実施例を説明するための部分
断面図と部分平面図、第２図は第１図により説明
された実施例によつて形成された製品の部分断面
図と部分平面図、第３図は本発明により形成され
た製品の斜視図、第４図は本発明を生産に適用し
た場合の概要を示す斜視図、第５図は従来の方法
により形成された製品の部分断面図と部分平面図
である。
１……回路基板、２……半導体チツプ、３……
配線導体、４……ワイヤ、５……樹脂モールド、
６……樹脂枠、７……シート状弾性体、８……押
さえ板、９，１０……穴、１１……凸部、１５…
…基台。
FIG. 1 is a partial sectional view and a partial plan view for explaining an embodiment of the present invention, and FIG. 2 is a partial sectional view and a partial plan view of a product formed by the embodiment explained in FIG. 1. , FIG. 3 is a perspective view of a product formed by the present invention, FIG. 4 is a perspective view showing an outline of the case where the present invention is applied to production, and FIG. 5 is a partial cross section of a product formed by the conventional method. FIG. 2 is a diagram and a partial plan view. 1... Circuit board, 2... Semiconductor chip, 3...
Wiring conductor, 4... wire, 5... resin mold,
6... Resin frame, 7... Sheet-like elastic body, 8... Pressing plate, 9, 10... Hole, 11... Convex portion, 15...
...base.
Claims (1)
着されワイヤボンデイングされた少なくとも１つ
の半導体チツプと前記ワイヤボンデイングのワイ
ヤとを保護する樹脂モールドを形成するために、 前記半導体チツプがワイヤボンデイングされた
回路基板を水平基台上に載置し、該回路基板上の
前記半導体チツプとワイヤとが収容される容積の
穴が設けられ該容積の高さに等しい厚さの封止用
マスクを前記回路基板の上から前記半導体チツプ
と前記穴との位置が合うように載せた後、半液状
の樹脂を前記穴の上から前記半導体チツプと前記
ワイヤとが被われるまで滴下注入し、室温あるい
は高温で前記樹脂を硬化させた後、前記封止用マ
スクを取り外すことにより前記半導体チツプと前
記ワイヤとを保護する樹脂モールドを形成する混
成集積回路における半導体チツプの樹脂モールド
方法において、 前記封止用マスクをシート状弾性体とし該シー
ト状弾性体を前記回路基板の上から前記半導体チ
ツプと前記シート状弾性体に設けられた穴との位
置が合うように載せた後、前記シート状弾性体の
前記穴よりやや大きく該穴の周辺部分を上から押
さえる凸部を有する穴部が設けられた押さえ板を
前記穴と前記穴部の位置が合うように載せて前記
穴が変形しないような力で加圧して前記シート状
弾性体を前記回路基板に圧接し、前記半液状の樹
脂を前記押さえ板の穴部の上から前記半導体チツ
プと前記ワイヤとが被われるまで滴下注入し、室
温あるいは高温で前記樹脂を硬化させた後、前記
シート状弾性体と前記押さえ板を取り外すことに
より前記半導体チツプと前記ワイヤとを保護する
樹脂モールドを形成するようにしたことを特徴と
する混成集積回路における半導体チツプの樹脂モ
ールド方法。[Scope of Claims] 1. In order to form a resin mold that protects at least one semiconductor chip bonded and wire-bonded to a predetermined position on a circuit board of a hybrid integrated circuit and the wire of the wire bonding, the semiconductor A circuit board on which a chip is wire-bonded is placed on a horizontal base, and a hole having a volume to accommodate the semiconductor chip and wires on the circuit board is provided, and a seal having a thickness equal to the height of the volume is provided. After placing a protective mask on the circuit board so that the semiconductor chip and the hole are aligned, semi-liquid resin is dripped and injected from above the hole until the semiconductor chip and the wire are covered. In a resin molding method for a semiconductor chip in a hybrid integrated circuit, the resin mold is formed to protect the semiconductor chip and the wires by curing the resin at room temperature or high temperature and then removing the sealing mask. The sealing mask is a sheet-like elastic body, and the sheet-like elastic body is placed on the circuit board so that the semiconductor chip and the hole provided in the sheet-like elastic body are aligned, and then the sheet A pressing plate provided with a hole slightly larger than the hole of the shaped elastic body and having a convex portion that presses the peripheral portion of the hole from above is placed so that the hole and the hole are aligned so that the hole does not deform. pressing the sheet-like elastic body against the circuit board by pressing with such force, and injecting the semi-liquid resin dropwise from above the hole of the holding plate until the semiconductor chip and the wire are covered; A hybrid assembly characterized in that, after the resin is cured at room temperature or high temperature, the sheet-like elastic body and the pressing plate are removed to form a resin mold that protects the semiconductor chip and the wire. Resin molding method for semiconductor chips in circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63132640A JPH01303729A (en) | 1988-06-01 | 1988-06-01 | Resin molding of semiconductor chip in hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63132640A JPH01303729A (en) | 1988-06-01 | 1988-06-01 | Resin molding of semiconductor chip in hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01303729A JPH01303729A (en) | 1989-12-07 |
| JPH0532903B2 true JPH0532903B2 (en) | 1993-05-18 |
Family
ID=15086056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63132640A Granted JPH01303729A (en) | 1988-06-01 | 1988-06-01 | Resin molding of semiconductor chip in hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01303729A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08327071A (en) * | 1995-04-07 | 1996-12-10 | Samsung Electronics Co Ltd | Illuminator of microwave oven and its control method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS548680U (en) * | 1977-06-21 | 1979-01-20 | ||
| JPS6352428A (en) * | 1986-08-22 | 1988-03-05 | Olympus Optical Co Ltd | Manufacture of semiconductor element |
-
1988
- 1988-06-01 JP JP63132640A patent/JPH01303729A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS548680U (en) * | 1977-06-21 | 1979-01-20 | ||
| JPS6352428A (en) * | 1986-08-22 | 1988-03-05 | Olympus Optical Co Ltd | Manufacture of semiconductor element |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08327071A (en) * | 1995-04-07 | 1996-12-10 | Samsung Electronics Co Ltd | Illuminator of microwave oven and its control method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01303729A (en) | 1989-12-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6448111B1 (en) | Method of manufacturing a semiconductor device | |
| US7037756B1 (en) | Stacked microelectronic devices and methods of fabricating same | |
| US5893726A (en) | Semiconductor package with pre-fabricated cover and method of fabrication | |
| US6521480B1 (en) | Method for making a semiconductor chip package | |
| JP4708401B2 (en) | Method for forming a compliant interface of a semiconductor chip | |
| US6983537B2 (en) | Method of making a plastic package with an air cavity | |
| JP3420057B2 (en) | Resin-sealed semiconductor device | |
| JP3491003B2 (en) | Chip size package semiconductor | |
| US20060205117A1 (en) | Solder masks used in encapsulation, assemblies including the solar mask, and methods | |
| JPH04233263A (en) | Molded hybrid package, lead frame for it | |
| JPH06252316A (en) | Method for forming plastic member on lead frame | |
| JPS5848442A (en) | Sealing of electronic parts | |
| JPH0532903B2 (en) | ||
| JP4485210B2 (en) | Semiconductor device, electronic device, method for manufacturing semiconductor device, and method for manufacturing electronic device | |
| JP4033780B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3024608B2 (en) | Method for manufacturing semiconductor device | |
| JP3340455B2 (en) | O-ring package | |
| JPH03160751A (en) | Semiconductor device | |
| JP2003109988A (en) | Mounting tool and method for mounting ic chip | |
| JP4656766B2 (en) | Manufacturing method of semiconductor device | |
| KR100203936B1 (en) | Module package | |
| JPH0530363Y2 (en) | ||
| JPH08107162A (en) | Semiconductor device and manufacture thereof | |
| US20010015489A1 (en) | Semiconductor device and its manufacturing method | |
| JPH011262A (en) | Electronic device and its manufacturing method |