JPH0535909B2 - - Google Patents
Info
- Publication number
- JPH0535909B2 JPH0535909B2 JP62197659A JP19765987A JPH0535909B2 JP H0535909 B2 JPH0535909 B2 JP H0535909B2 JP 62197659 A JP62197659 A JP 62197659A JP 19765987 A JP19765987 A JP 19765987A JP H0535909 B2 JPH0535909 B2 JP H0535909B2
- Authority
- JP
- Japan
- Prior art keywords
- simulation
- clock
- event
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004088 simulation Methods 0.000 claims description 44
- 239000013598 vector Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000012545 processing Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000010408 sweeping Methods 0.000 description 1
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62197659A JPS6441975A (en) | 1987-08-07 | 1987-08-07 | Simulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62197659A JPS6441975A (en) | 1987-08-07 | 1987-08-07 | Simulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6441975A JPS6441975A (en) | 1989-02-14 |
| JPH0535909B2 true JPH0535909B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1993-05-27 |
Family
ID=16378184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62197659A Granted JPS6441975A (en) | 1987-08-07 | 1987-08-07 | Simulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6441975A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2924968B2 (ja) * | 1989-07-20 | 1999-07-26 | 富士通株式会社 | 時間双方向シミュレーション装置 |
-
1987
- 1987-08-07 JP JP62197659A patent/JPS6441975A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6441975A (en) | 1989-02-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1215468A (en) | Method and apparatus for modeling of systems of complex circuits | |
| EP0450839A2 (en) | A logic simulation machine | |
| US5781718A (en) | Method for generating test pattern sets during a functional simulation and apparatus | |
| EP0472818A2 (en) | Built-in self test for integrated circuits | |
| JPS633344B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | ||
| JPS60164848A (ja) | モデリング動作の方法 | |
| Jephson et al. | A three-value computer design verification system | |
| JPH0511329B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | ||
| US5193068A (en) | Method of inducing off-circuit behavior in a physical model | |
| US20050055190A1 (en) | Circuit operation verification device and method | |
| JPH0535909B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | ||
| JPS6141017B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | ||
| US4995037A (en) | Adjustment method and apparatus of a computer | |
| JPH0696151A (ja) | ロジックシミュレーション装置 | |
| US6973422B1 (en) | Method and apparatus for modeling and circuits with asynchronous behavior | |
| CA1212770A (en) | Method for propagating unknown digital values in a hardware based complex circuit simulation system | |
| Bellon et al. | Taking into account asynchronous signals in functional test of complex circuits | |
| JP2845032B2 (ja) | 論理シミュレーション装置 | |
| JPS60173483A (ja) | 論理回路シミュレーション装置 | |
| JPH0391195A (ja) | メモリ回路 | |
| JPH08327703A (ja) | ベクトル・モジュール・テーブルを用いる自動テスト装置のためのメモリ・アーキテクチャ | |
| JPS60163141A (ja) | シミユレ−タ | |
| JP2824853B2 (ja) | パターンデータ書込み方式 | |
| SU1520534A1 (ru) | Устройство дл моделировани конечных автоматов | |
| JPH0821043B2 (ja) | シミュレーション方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |