JPH05343362A - Dry etching method - Google Patents

Abstract

PURPOSE:To satisfy high anisotropy, high selectivity, low contamination, low damage, etc., at a high level by using etching gas in which halogen compound containing thionyl group or sulfuryl group is added. CONSTITUTION:A pad oxide film 2 and a polycrystalline silicon layer 3 are laminated on a single crystalline silicon substrate 1, and a wafer formed with a resist mask 4 patterned in a predetermined shape is set on a wafer placing electrode of an RF bias application type magnetic microwave plasma etching apparatus. For example, SOBr2/SF6 mixture in which halogen compound containing thionyl group or sulfuryl group is added is used. Thus, even if an RF bias power is reduced by half, shallow trenches 1a, 1b each having an excellent anisotropic shape are formed, and resist selectivity is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method applied in the field of manufacturing semiconductor devices, etc., and in particular, performs high anisotropy, high selectivity, low contamination and low damage etching of a silicon-based material layer. Regarding the method.

[0002]

2. Description of the Related Art As semiconductor devices have become more highly integrated and have higher performance as seen in VLSI, ULSI, etc. in recent years, etching of silicon-based material layers such as single crystal silicon, polycrystalline silicon, amorphous silicon, etc. Also in the above, there is a strong demand for a technology that achieves the various requirements of high anisotropy, high selectivity, low contamination, and low damage without sacrificing any of them.

There are two typical fields for etching a silicon-based material layer: trench processing and gate electrode processing. Trench processing is a process for forming trenches for the purpose of isolating fine elements and securing the memory cell capacity area. The depth of the trench depends on the type and application of the device. It is 4-5 μm (deep trench) for the capacitive element, 1 μm for the MOS-FET (shallow trench) for element isolation, and 4 μm for the bipolar transistor.
It is considered as a degree. The opening diameter of each trench is 0.3
It is about 5 to 1 μm, and anisotropic processing of a high aspect ratio pattern is required.

Chlorine gas is generally used for trench processing. Since Cl ^* has a larger atomic radius than F ^* , there is little risk that it will spontaneously enter the Si crystal lattice and deteriorate the anisotropic shape, and especially in deep trench processing, silicon oxide is used. This is because high selectivity can be maintained with respect to the etching mask of the system. In reality, however, the cross-sectional shape of the trench is likely to change intricately due to changes in the mask pattern and etching conditions, and shape abnormalities such as undercut and bowing are often experienced. All of these make it difficult to fill trenches and control the capacitance in the subsequent process.

Therefore, in order to prevent the above-described deterioration of the cross-sectional shape of the trench, an etching gas capable of producing a depositable substance under discharge dissociation conditions is used, and the depositable substance is utilized to protect the sidewall. Several methods have been proposed in the past. For example, the applicant of the present invention first disclosed in Japanese Patent Laid-Open No. 63-
The SiCl ₄ / N ₂ mixed gas disclosed in Japanese Patent No. 73526 is a typical example. This, together to generate a Cl ^* and Cl ⁺ from SiCl ₄ as a main etching species, Si _x N in the gas phase by reaction with SiCl ₄ and N _{2
In this method, y} , Si _x N _y Cl _z, etc. are generated, and these are deposited to protect the side wall. According to this technique, particle contamination can be reduced far more than when a carbon-based polymer is used as a sidewall protective substance, and etching can be performed under clean conditions.

Further, the applicant of the present application is disclosed in Japanese Patent Laid-Open No. 64-599.
Japanese Patent No. 17 also discloses a technique of performing silicon trench etching using a Cl ₂ / N ₂ mixed gas. This technique also utilizes Si _x N _y , Si _x N _y Cl _z, etc. as the side wall protective material, but these are generated by the reaction of the etching reaction products SiCl _x and N ₂ . Therefore, the particle contamination can be further reduced as compared with the case where the depositable substance is generated in the gas phase due to the reaction between the constituent components of the etching gas as in the process using the SiCl ₄ / N ₂ mixed gas described above. It will be possible.

On the other hand, a typical etching process for polycrystalline silicon is gate processing. The pattern width of the gate electrode directly affects the channel length when the source / drain regions of the MOS-FET are formed in a self-aligned manner and the dimensional accuracy of the sidewall in the LDD structure. Therefore, this process also requires extremely high processing accuracy.

Conventionally, CFC11 has been used for processing the gate electrode.
CFC (chlorofluorocarbon) gas represented by 3 (C ₂ Cl ₃ F ₃ ) and the like has been widely used as an etching gas. Since CFC gas has F and Cl as constituent elements in one molecule, depending on the conditions, a radical reaction due to contributions of F ^* , Cl ^*, etc. and an ion-assisted reaction due to contributions of CCl _x ⁺ , Cl ⁺ etc. are balanced. It is possible to proceed with etching while controlling. Further, it is possible to achieve high anisotropy while protecting the side wall with the carbon-based polymer deposited from the gas phase.

However, it is known that CFC gas is one of the causes of the depletion of the ozone layer of the earth as well known, and the production and use thereof will be prohibited in the near future. Therefore, even in the field of dry etching, C
There is an urgent need to find alternatives to FC gas and establish effective ways to use them. Further, if the design rule of the semiconductor device is further miniaturized in the future, it is considered that carbon-based polymer deposited from the gas phase becomes a source of particle contamination, and from this point of view, countermeasures against CFC depletion are desired.

One of the promising technologies as one of the countermeasures against this CFC removal is a process of using a Br type chemical species as a main etching species. For example, Digest o
fPapers 1989 2nd MicroPro
cess Conference, p. 190 to H
Processing of n ⁺ type polycrystalline silicon gate electrodes using Br has been reported. Br has a large ionic radius and does not enter the crystal lattice or the crystal grain boundaries of the silicon-based material layer. Therefore, there is little possibility that the silicon-based material layer is spontaneously and isotropically etched like F ^* , and the ion
Anisotropic etching can be progressed by the assist mechanism. In addition, when the interatomic bond energies are compared, the Si-O bond (1077 kJ / mol) is Si-B.
As is clear from the fact that it is much larger than r-coupling (368 kJ / mol), high selectivity can be achieved for the gate oxide film made of SiO ₂ . Furthermore, since the surface of the resist mask can be coated with CBr _x having a low vapor pressure, the point that the resist selectivity can be improved is also a great advantage of the Br-based chemical species.

On the other hand, a technique has been proposed in which high anisotropy is not achieved by the side wall protecting action of the carbon-based polymer as described above, but this is achieved by lowering the temperature of the substrate (wafer) to be etched. .. This is a so-called low temperature etching process, and the wafer temperature is reduced to zero.
By keeping the temperature below ℃, the radical reaction on the pattern side wall is frozen or suppressed while the etching rate in the depth direction is maintained at a practical level by the ion assist effect, and shape abnormalities such as undercut are prevented. It is a technology. For example, in the 35th Joint Lecture on Applied Physics (Spring Annual Meeting 1988) Proceedings, p. 495, page No. 28a-G-2, the wafer was cooled to -130 ° C. and SF ₆ gas was used. An example in which a silicon trench etching and an n ⁺ type polycrystalline silicon layer are etched has been reported.

[0012]

However, if the design rules of semiconductor devices continue to progress at a rapid pace, it will be necessary to reduce particle contamination at a higher level than ever before. From this viewpoint, in trench processing, S
The above-described process utilizing i _x N _y , Si _x N _y Cl _z, etc. for sidewall protection satisfies the current requirements but has not fundamentally avoided particle contamination. In addition, since trench processing generally requires a long process time and a large amount of depositable substances are produced, it is premised that such substances can be easily and completely removed after etching even if they are used for sidewall protection.

Even in the process of using HBr for processing the gate electrode, it is difficult to avoid particle contamination due to SiBr _x or the like.

On the other hand, low temperature etching removes CFC.
It is expected to be one of the effective measures, but if we try to rely only on freezing or suppressing the reaction of radicals to achieve high anisotropy, it will be necessary to cool at a low temperature that requires liquid nitrogen as described above. .. However, this causes problems in hardware such as the need for a large-scale special cooling device and the reduction in reliability of the vacuum sealing material. Also,
Since it takes time to cool the wafer and heat it to return it to room temperature, there is a concern that throughput may be reduced, and there is a great risk of impairing economic efficiency and productivity.

In view of the above, the present invention provides a silicon-based material layer which can satisfy various properties that are difficult to achieve at the same time, such as high anisotropy, high selectivity, low contamination, and low damage, at a high level and can be carried out in a practical temperature range. It is an object of the present invention to provide a dry etching method of

[0016]

The dry etching method of the present invention is proposed in order to achieve the above-mentioned object, and has at least one functional group of a thionyl group or a sulfuryl group and a halogen atom in the molecule. It is characterized in that the silicon-based material layer is etched while depositing the carbon-based polymer on at least the sidewall surface of the etching pattern using an etching gas containing a halogen compound having

According to the present invention, a sulfur-based compound capable of releasing sulfur into plasma under discharge dissociation conditions is added to the etching gas containing the halogen compound, and a carbon-based polymer is added to at least the sidewall surface of the etching pattern. The silicon-based material layer is etched while depositing sulfur.

The present invention also uses the etching gas containing the halogen compound to etch the silicon-based material layer substantially by the thickness of the silicon-based material layer while depositing the carbon-based polymer on at least the sidewall surface of the etching pattern. Just etching step, adding a sulfur-based compound that releases sulfur into plasma under discharge dissociation conditions to the etching gas, while depositing carbon-based polymer and sulfur on at least the sidewall surface of the etching pattern. And an over-etching step of etching the remaining portion of the silicon-based material layer.

The present invention is further characterized in that after the etching is completed, at least the carbon-based polymer and / or the sulfur deposited on the sidewall surface of the etching pattern of the silicon-based material layer is removed by ashing.

[0020]

In order to achieve the above object, the present inventor has come to the conclusion that it is extremely effective to enhance the film quality of the carbon-based polymer forming the side wall protective film as compared with the conventional one and improve the etching resistance. It was This is because the following advantages can be expected in carbon-based polymer reinforcement.

First, since the side wall protection effect is improved, the incident ion energy required for anisotropic processing can be lowered. As a result, it is possible to suppress sputter removal of the etching mask and the gate oxide film, the selectivity for these is improved, and the damage is reduced. Secondly,
Since the deposition amount of the carbon-based polymer required to achieve high anisotropy and high selectivity can be reduced, particle contamination can be reduced as compared with the conventional technique. Further, since the extraction of O atoms from SiO ₂ by the C atoms constituting the carbon-based polymer is suppressed, the selectivity for the gate oxide film is improved when the gate electrode is processed.

Thirdly, by improving the side wall protection effect, F type chemical species and Cl type chemical species having high reactivity with Si can be utilized for etching, so that high anisotropy and high selectivity can be achieved. The etching rate is remarkably increased as compared with the case of relying only on the Br-based chemical species.

In the present invention, the carbon-based polymer is reinforced.
As a constituent of the etching gas that enables the
A thionyl group (> S = O) or a sulfuryl group (>
SO ₂) At least one functional group and a halogen atom
A halogen compound having is used. The above halogen compounds
Needless to say, the halogen atoms in the inside are silicon-based material layers.
Contributes as a main etching species.

On the other hand, the thionyl group and the sulfuryl group are
It can have a structure in which the S atom is positively charged and the O atom is negatively charged, and has a high polymerization promoting activity.
Therefore, the presence of these functional groups or atomic groups derived from them in the plasma increases the degree of polymerization of the carbon-based polymer, and can enhance resistance to ion injection and radical attack. Further, when the above-mentioned functional group or a fragment derived therefrom is introduced into the carbon-based polymer, it is more chemically than the conventional carbon-based polymer which is simply composed of a repeating structure of —CX ₂ — (X represents a halogen atom). ， Recent studies have also revealed that physical stability is increased. When comparing the binding energies between two atoms, this is the C—S bond (713.4 kJ
/ Mol) is larger than the CC bond (607 kJ / mol), which is also intuitively understood. Furthermore, the introduction of the functional groups as described above increases the polarity of the carbon-based polymer, and the electrostatic adsorption force to the wafer that is negatively charged during etching is also increased. Will improve.

The present invention is based on the above idea, but proposes a method aiming at further reduction of pollution and damage. The method is the above-mentioned etching
A sulfur-based compound capable of releasing sulfur (S) into plasma under discharge dissociation conditions is added to the gas. In this case, in addition to the carbon-based polymer which is the etching reaction product, S can also be used for sidewall protection. S
Will depend on the conditions, but will be deposited on the surface of the wafer if the temperature of the wafer is controlled below room temperature. Therefore, the incident ion energy can be further reduced, and the damage can be thoroughly reduced. In addition, the amount of carbon-based polymer deposited can be relatively reduced, and particle contamination can be reduced more effectively. Moreover, S easily sublimes when the wafer is heated to approximately 90 ° C. or higher, so that S itself does not become a source of particle contamination.

If the above halogen compound or an etching gas containing a sulfur compound added thereto is used,
Basically, the one-step etching of the silicon-based material layer becomes possible, and it is possible to obtain a sufficient effect with respect to the trench processing which does not need to consider the underlying selectivity. The present invention further proposes a method for improving high speed, low contamination, and underlayer selectivity in gate electrode processing which requires consideration of underlayer selectivity. It is a two-step etching in which the gas composition is switched between just etching and over etching.

First, in the just etching step of etching the silicon-based material layer substantially by the thickness thereof,
An etching gas containing the above halogen compound is used.
At this stage, the reinforced carbon-based polymer is deposited.
Next, in the overetching step of etching the remaining portion of the silicon-based material layer, a sulfur-based compound capable of releasing S into plasma is added to the etching gas containing the halogen compound to remove both carbon-based polymer and S. To deposit. As a result, even if the incident ion energy is reduced in order to reduce damage during overetching, the sidewall protection effect is enhanced, so that a good anisotropic shape of the etching pattern of the silicon-based material layer is maintained. ..

In each of the above etchings,
Carbon-based polymer and / or deposited on the sidewall surface of the pattern
Alternatively, S can be removed by ashing.
This ashing can also be performed by removing the resist mask if the process uses a resist mask. If the process uses an inorganic etching mask, such as deep trench processing, it is performed in a separate process. In any case, the amount of the carbon-based polymer deposited is much smaller than that in the conventional process, and therefore the removal is easy. On the other hand, sulfur is easily sublimated by plasma radiant heat or reaction heat during ashing, and is also burned by O ₂ , so there is no possibility of causing particle contamination.

[0029]

EXAMPLES Specific examples of the present invention will be described below.

Example 1 This example is an example in which the present invention is applied to shallow trench processing, and a single crystal silicon substrate is etched using SOBr ₂ (thionyl bromide) / SF ₆ mixed gas. This process will be described with reference to FIG. First, as shown in FIG. 1A, a pad oxide film 2 and a polycrystalline silicon layer 3 were sequentially laminated on a single crystal silicon substrate 1, and a resist mask 4 patterned into a predetermined shape was formed. A sample wafer was prepared. Here, the polycrystalline silicon layer 3 is formed, for example, by CVD to have a layer thickness of 0.15 μm, and is provided as a buffer layer for preventing the recession of the edge of the resist mask 4 during etching from being reflected in the deterioration of the trench shape. It is a thing. The pad oxide film 2 is formed to have a layer thickness of 0.01 μm by, for example, thermal oxidation of the single crystal silicon substrate 1, and is a stopper layer for etching back the polycrystalline silicon layer 3 after the trench processing is completed. Is provided as. Further, the resist mask 4 is
It is formed using a negative type three-component type chemically amplified negative type photoresist material (manufactured by Shipley Co .; trade name SAL-601) and has an opening diameter of 0.35 μm by KrF excimer laser lithography and alkali development. The first opening 5 and the second opening 6 having an opening diameter of 1 μm are formed.

Next, the above-mentioned wafer was set on the wafer mounting electrode of the RF bias application type magnetic field microwave plasma etching apparatus. The wafer mounting electrode has a built-in cooling pipe, and the wafer can be cooled to a desired temperature by receiving an appropriate coolant supply from a cooling facility such as a chiller installed outside the apparatus. Here, ethanol was used as a coolant, and etching was performed under the following conditions as an example.

SOBr ₂ flow rate 10 SCCM SF ₆ flow rate 10 SCCM Gas pressure 0.67 Pa (= 5 mTorr) Microwave power 850 W (2.45 GHz) RF bias power 50 W (2 MHz) Wafer temperature 0 ° C. Here, SOBr ₂ is liquid at room temperature He as a substance
After being vaporized by gas bubbling, it was introduced into the etching chamber.

In this process, the radical reaction due to Br ^* dissociated and produced from SOBr ₂ and F ^* dissociated and produced from SF ₆ causes S ⁺ , SO ⁺ , SOBr _x ⁺ , SF _x ^+.
Etching progressed by a mechanism assisted by the incident energy of ions such as. At the same time, CBr _x was generated due to the decomposition product of the resist mask 6, and thionyl groups and C—S bonds were incorporated into the structure to form a strong carbon-based polymer. However, since the surface of the resist mask 6 is also covered with CBr _x , the supply amount of the carbon-based polymer is not so large. This carbon-based polymer was deposited on the side wall of the pattern to form the side wall protection film 7 as shown in FIG. 1 (b), and although it was deposited in a small amount, it exhibited high etching resistance and contributed to anisotropic processing. ..
As a result, the shallow trench 1 having a good anisotropic shape even though the RF bias power is halved as compared with the conventional process using the CFC gas.
a and 1b are formed, and the resist selectivity is about 1.5 of the conventional level.
Doubled.

If only the anisotropic etching of the single crystal silicon substrate 1 is intended, the etching gas of this embodiment may be a single composition of SOBr ₂ . However, in the shallow trench processing, the polycrystalline silicon layer 3
Since the pad oxide film 2 and the pad oxide film 2 are also usually etched by a gas system having a common composition, SF ₆ is added in order to remove the pad oxide film 2 without generating a residue.
That is, F ^* that can etch the iO ₂ material is generated. This F ^* naturally contributes to speeding up of the shallow trench processing. This is also extremely effective in preventing the loading effect.

Generally, in the shallow trench processing, the area to be etched reaches 50% or more of the wafer area, and the area to be etched is an order of magnitude larger than that in the deep trench processing which is 5% or less. I won't. When the area to be etched increases in this way, the etching rate inevitably decreases due to the loading effect, and in some cases, the rate of decrease reaches nearly 50%. Therefore, in order to realize a practical process, it is essential to improve the etching rate. Therefore, the process in which F ^* can be used together and the anisotropy and the resist selectivity are not deteriorated as in this embodiment is extremely practical.

Finally, the wafer was transferred to a plasma ashing apparatus, and the resist mask 4 was removed by burning under the conditions of normal O ₂ plasma ashing. At this time, as shown in FIG. 1C, the side wall protective film 7 was also promptly removed. The sidewall protective film 7 is composed of the carbon-based polymer reinforced as described above, but the deposited amount thereof is much smaller than that of the conventional process, so that the particle level was not deteriorated at all.

Example 2 This example is also an example of shallow trench processing, but using SOF ₂ (thionyl fluoride) / S ₂ Cl ₂ mixed gas as an etching gas and depositing S (sulfur). Is used in combination to further improve resist selectivity and reduce contamination.

The wafer used as the etching sample in this example is the same as that shown in FIG. As an example, this wafer was etched under the following conditions. SOF ₂ flow rate 10 SCCM S ₂ Cl ₂ flow rate 10 SCCM Gas pressure 0.67 Pa (= 5 mTo
rr) Microwave power 850W (2.45GH)
z) RF bias power 30W (2MHz) Wafer temperature -30 ° C

The above S ₂ Cl ₂ is of course a source of Cl ^* , but also plays an important role of releasing S under discharge dissociation conditions. That is, in this embodiment, in addition to CCl _x reinforced by a thionyl group or a C—S bond, this S can also participate in the formation of the sidewall protective film 7. Moreover, in this embodiment, the radical reaction on the side wall surface of the pattern is suppressed by the effect of wafer cooling. Due to these effects, incident ions
Good anisotropic processing could be performed despite the condition that the energy was lowered. Further, since the amount of carbon-based polymer deposited could be reduced by the amount that S deposition can be expected, particle contamination was reduced.

When O ₂ plasma ashing was performed after the etching was completed, as shown in FIG. 1C, the resist mask 4 and the side wall protective film 7 were quickly removed. Here, the side wall protective film 7 contains a carbon-based polymer and S, but S is removed by sublimation by plasma radiant heat or reaction heat, and also by combustion reaction by O ^* , so that it does not exist on the wafer. No particle contamination was left.

Example 3 This example is an example in which the present invention is applied to deep trench processing, and a single crystal silicon substrate is etched using SO ₂ Cl ₂ (sulfuryl chloride) / CF ₄ mixed gas. This process will be described with reference to FIG. First, as an example, as shown in FIG. 2A, a sample wafer was prepared in which an etching mask composed of a SiO ₂ pattern 12 and sidewalls 13 was formed on a single crystal silicon substrate 11. Here, the SiO ₂ pattern 12 is formed by CVD or the like and has a layer thickness of 0.2 μm.
The iO ₂ deposited film was etched through a mask made of a novolac-based positive photoresist material (manufactured by Tokyo Ohka Kogyo Co., Ltd .; trade name TSMR-V3) patterned by g-ray exposure and alkali development to obtain a .0 5
An opening having a diameter of μm is formed. In addition, after removing the resist mask, the sidewall 13 is formed with a SiO ₂ deposited film on the entire surface of the wafer by CVD using TEOS (tetraethoxysilane) as a raw material gas, and the SiO ₂ deposited film is formed by RIE. It is formed by etching back. Thus, the opening diameter of the opening 14 formed in the etching mask exceeds the resolution limit of photolithography by 0.2 μm.
Has been reduced to.

This wafer was set in an RF bias application type magnetic field microwave plasma etching apparatus, and as an example, the single crystal silicon substrate 11 was etched under the following conditions. SO ₂ Cl ₂ flow rate 20 SCCM CF ₄ flow rate ₂ SCCM Gas pressure 0.27 Pa (= 2 mTorr
r) Microwave power 850 W (2.45 GHz) RF bias power 50 W (2 MHz) Wafer temperature 0 ° C. Here, since the SO ₂ Cl ₂ is a liquid substance at room temperature, it is vaporized by He gas bubbling. It was introduced into the etching chamber.

In this etching process, the radical reaction by Cl ^* generated from SO ₂ Cl ₂ causes S ⁺ , SO _x.
^The single crystal silicon substrate 11 was etched by a mechanism assisted by the incident energy of ions such as ⁺ , SOCl _x ⁺ , and CF _x ⁺ . At this time, sulfuryl group discharge dissociation products of CF _4, thionyl group its fragments, C
The -S bond and the like are incorporated to form a strong carbon-based polymer, which is deposited on the side wall surface of the pattern, as shown in FIG.
The side wall protective film 15 as shown in FIG. That is, CF ₄ has a function of supplying the fragment, which is a raw material of the carbon-based polymer, into the gas phase in the system in which the carbon-based polymer is not supplied from the etching mask as in the present embodiment. The RF bias power is almost halved as compared with the conventional etching using, for example, a Cl ₂ / N ₂ mixed gas system. Furthermore, the mean free path of ions is extended by greatly reducing the gas pressure,
Some efforts have been made to increase the vertical incidence component on the wafer surface. Due to these effects, the deep trench 11a having an anisotropic shape was formed.

[0044] It should be noted that, although from CF ₄ generated by the F ^*, C
Since the amount of F ₄ added is originally small, SiO ₂ pattern 1
Not lead to any decrease the selectivity to 2 and sidewall 13, and rather a pair SiO ₂ selectivity of the effect of the low bias of the above can be improved to twice the conventional method.

After the completion of etching, O ₂ plasma ashing was performed on the wafer, and the sidewall protection film 15 was quickly removed as shown in FIG. 2 (c), causing any particle contamination. It never happened.

Example 4 In this example, the present invention is applied to the processing of a gate electrode, and the SOC is
In this example, the polycrystalline silicon layer is just-etched by using l ₂ and then overetched by using SOCl ₂ / S ₂ Br ₂ mixed gas. This process is shown in FIG.
Will be described with reference to.

The wafer used as an etching sample in this example is as shown in FIG.
An n-type polycrystalline silicon layer 2 having a thickness of approximately 0.3 μm, which is formed by doping n-type impurities through a gate oxide film 22 having a thickness of approximately 0.01 μm and made of SiO ₂ on a single crystal silicon substrate 21.
3 is formed, and a resist mask 24 having a thickness of about 1 μm is further formed in a predetermined pattern on this.

This wafer is loaded with a magnetic field microwave plasma
The n-type polycrystalline silicon layer 23 was etched under the following conditions by setting in an etching apparatus. SOCl ₂ flow rate 10 SCCM gas pressure 0.67 Pa (= 5 mTo
rr) Microwave power 850W (2.45GH)
z) RF bias power 50 W (2 MHz) Wafer temperature −30 ° C. In this etching process, etching using Cl ^* as the main etching species proceeds. At this time, a thionyl group, C-
Since the CCl _x polymer reinforced by S bonds or the like is deposited to form the side wall protective film 25, the gate electrode 23a excellent in anisotropic shape was formed. This etching was completed when the surface of the gate oxide film 22 was exposed, but the remaining portion 23b of the n-type polycrystalline silicon layer 23 was partially left in the etched region.

Therefore, the etching conditions were switched as follows by way of example, and over-etching was performed to remove the residual portion 23b. SOCl ₂ flow rate 5 SCCM S ₂ Br ₂ flow rate 10 SCCM Gas pressure 0.67 Pa (= 5 mTo
rr) Microwave power 850W (2.45GH)
z) RF bias power 30 W (2 MHz) Wafer temperature -30 ° C. At this stage, S contributes to the sidewall protection in addition to the carbon-based polymers such as reinforced CCl _x and CBr _x , so that compared to the just etching process. It has become possible to further reduce the bias. In addition, because the wafer temperature is lowered and the radical reaction on the side wall of the pattern is suppressed, and the Br-based chemical species having low reactivity with Si is used, the gate oxide film 22 is extremely affected. High selectivity was achieved. Moreover, the surface of the resist mask 24 has CB whose vapor pressure is lower than that of CCl _x polymer.
As the r _x polymer is deposited, the resist mask 24
The selectivity for was also improved. Under such high selection and low damage conditions, the residual portion 23b could be completely removed as shown in FIG.

Finally, when the wafer after etching was transferred to an ashing device and O ₂ plasma ashing was carried out, the resist mask 24 and the side wall protective film 25 were cleanly removed as shown in FIG. 3D. Was removed.

Although the present invention has been described based on the four examples, the present invention is not limited to these examples. For example, as the halogen compound having a thionyl group and a halogen atom in the molecule, the above-mentioned S
In addition to OF ₂ and SOCl ₂ , SOF ₄ (thionyl tetrafluoride), SOBr ₂ (thionyl bromide; liquid), SOClB
r (thionyl chloride bromide; liquid) or the like can be used.

Similarly, as the halogen compound having a sulfuryl group and a halogen atom in the molecule, the above-mentioned SO ₂
In addition to Cl ₂ , SO ₂ F ₂ (sulfuryl fluoride), SO ₂
ClF (sulfuryl chloride), SO ₂ BrF (sulfuryl bromide bromide; liquid) and the like can be used.
The compounds described as "liquid" after the above Japanese name are liquid at room temperature, and those not described are gases.

Further, as the sulfur-based compound, the above-mentioned S
₂Cl₂, S₂Br₂And S₂F ₂, SF₂, S
F_Four, S₂F_TenSulfur fluoride such as S₃Cl₂, SCl
₂Other sulfur chlorides such as S₃Br₂, SBr₂Other of
Sulfur bromide, H₂S or the like can be used. More than
The combination of compounds is arbitrary, but especially Shallow To
When performing wrench processing, remove the pad oxide film immediately.
F under discharge dissociation conditions^*Supply
It is desirable to use the resulting gas system.

A rare gas such as He or Ar may be added to the etching gas for the purpose of obtaining a sputtering effect, a cooling effect and a dilution effect. The silicon-based material layer to be etched may be made of amorphous silicon in addition to the above-mentioned single crystal silicon and polycrystalline silicon. Furthermore, the etching equipment used,
It goes without saying that the etching conditions, the wafer configuration, etc. can be changed as appropriate.

[0055]

As is apparent from the above description, according to the present invention, by using an etching gas to which a halogen compound containing a thionyl group or a sulfuryl group is added in the etching of a silicon-based material layer, a carbon-based polymer of It is possible to achieve high anisotropy and high selectivity even if the film quality is enhanced and the deposition amount is reduced. Moreover, these can be achieved in a practical wafer temperature range. Further, by using the halogen compound in combination with a sulfur-based compound capable of releasing S under discharge dissociation conditions, further high selectivity, low pollution,
It is possible to reduce damage.

The present invention is extremely suitable for manufacturing a semiconductor device which is designed based on a fine design rule and which requires high integration, high performance and high reliability. Particularly in the gate electrode processing, it can provide a promising measure against CFC removal.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing an example of a process in which the present invention is applied to shallow trench processing in the order of steps, (a) showing a pad oxide film and a polycrystalline silicon layer on a single crystal silicon substrate. The state where the resist mask is formed, (b) shows the state where the sidewall trench is formed while forming the shallow trench, and (c) shows the state where the resist mask and the sidewall protective film are removed by ashing. ..

FIG. 2 is a schematic cross-sectional view showing an example of a process in which the present invention is applied to deep trench processing in the order of steps, (a) showing a state where an etching mask made of SiO ₂ is formed on a single crystal silicon substrate. , (B) show a state in which the deep trench is formed while the side wall protective film is formed, and (c) shows a state in which the side wall protective film is removed by ashing.

FIG. 3 is a schematic cross-sectional view showing an example of a process in which the present invention is applied to processing a gate electrode in the order of steps thereof,
(A) is a state where a resist mask is formed on the n-type polycrystalline silicon layer, (b) is a state where the n-type polycrystalline silicon layer is just-etched, and (c) is an over-type n-type polycrystalline silicon layer. Etched state, (d) shows a state in which the resist mask and the side wall protective film are removed by ashing.

[Explanation of symbols]

1,11,21 ・ ・ ・ Single crystal silicon substrate 1a, 1b ・ ・ ・ Shallow trench 2 ・ ・ ・ Pad oxide film 3 ・ ・ ・ Polycrystalline silicon layer 4,24 ・ ・ ・ Resist mask 7,15,25・ ・ ・ Sidewall protective film 11a ・ ・ ・ Deep trench 12 ・ ・ ・ SiO ₂ pattern 13 ・ ・ ・ Sidewall 22 ・ ・ ・ Gate oxide film 23 ・ ・ ・ n-type polycrystalline silicon layer 23a ・ ・ ・ Gate electrode

Claims (4)

[Claims] 1. A carbon-based polymer is deposited on at least a sidewall surface of an etching pattern by using an etching gas containing a halogen compound having a halogen atom and at least one functional group of a thionyl group or a sulfuryl group in a molecule. While etching the silicon-based material layer, a dry etching method. 2. An etching method comprising a halogen compound having at least one functional group of a thionyl group or a sulfuryl group and a halogen atom in the molecule, and a sulfur compound capable of releasing sulfur into plasma under discharge dissociation conditions. A dry etching method characterized in that a silicon-based material layer is etched while using a gas to deposit a carbon-based polymer and sulfur on at least a sidewall surface of an etching pattern. 3. A carbon-based polymer is deposited on at least a sidewall surface of an etching pattern by using an etching gas containing a halogen compound having a halogen atom and at least one functional group of a thionyl group or a sulfuryl group in a molecule. While just etching step of etching the silicon-based material layer substantially by the thickness of the layer, a sulfur-based compound that releases sulfur into plasma under discharge dissociation conditions is added to the etching gas, and at least the etching And a carbon-based polymer and sulfur on the side wall surface of the pattern while etching the remaining portion of the silicon-based material layer. 4. After the etching is finished, at least the carbon-based polymer and / or the sulfur deposited on the sidewall surface of the etching pattern of the silicon-based material layer is removed by ashing. The dry etching method according to claim 3.