JPH05342048A - Information processor - Google Patents

Abstract

PURPOSE:To exactly measure time at the time of performing pipeline processing. CONSTITUTION:By using a functional part state detection part 6 to detect the states of functional parts for executing instructions, following instructions are controlled so as to be continuously held in an instruction register 10 until all the functional parts 4a and 4b can execute them. Thus, time from the instruction execution to the end can be measured, and performance can be easily measured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a plurality of functional units capable of executing instructions simultaneously by pipeline control.

[0002]

2. Description of the Related Art In the conventional information processing apparatus of this type, since the processing of each instruction is pipelined, the processing of the subsequent instruction is started without waiting for the completion of the processing of the preceding instruction.

[0003]

However, this conventional information processing apparatus has a problem that the time at the completion of processing cannot be measured even if the processing execution time of the software processing routine is measured for the purpose of performance measurement or the like. It was Therefore, it is necessary to wait for the execution of the time measurement processing instruction until all the preceding instructions are completed.

[0004]

An information processing apparatus according to the present invention stores an instruction holding unit for reading and holding an instruction from a main storage unit, a plurality of functional units necessary for executing the instruction, and an instruction in the instruction holding unit. An information processing apparatus comprising a pipelined instruction control unit that decodes, creates information necessary for executing the instruction in accordance with the result of decoding the instruction, and activates and executes the functional unit In the command control unit, a plurality of state detecting means for detecting a use state of the functional units corresponding to the plurality of functional units, and a detection result of the detecting unit until all the functional units are processed. , And has means for continuing to hold subsequent instructions in the instruction holding means.

[0005]

EXAMPLES Next, examples of the present invention will be described.

Referring to FIG. 1 showing an embodiment of the present invention, this embodiment comprises a main memory unit 1, an instruction holding unit 2, an instruction control unit 3 and two functional units 4a and 4b.

The instruction holding unit 2 has an instruction register 10, and the instruction control unit 3 has a decoder unit 5, a function state detection unit 6, an instruction supply stop signal issuing unit 12 and an instruction control circuit 1.
Have four.

Further, the decoder section 5 has a functional section non-operation state generation instruction detection section 11 and a decoder 13, and
The functional unit state detection unit 6 has registers 15a and 15b for holding the states of the functional units 4a and 4b.

The functional units 4a and 4b are an addition pipeline and a multiplication pipeline, respectively. Only two types of functional parts are mentioned here for the sake of simplicity, but it is clear that this does not impair generality. Functional parts 4a, 4
Each of b can independently execute instructions at the same time.

The instruction in the main memory 1 is read to the instruction register 10 and then sent to the instruction controller 3. The instruction is decoded by the decode 13. The instruction decoded by the decoder 13 is sent to the instruction control circuit 14, and the instruction control circuit 1
When the functional units 4a and 4b that execute the instruction have completed the processing, 4 creates information necessary for executing the instruction in the functional units 4a and 4b and activates the execution. When the instruction is sent to the functional units 4a and 4b, the instruction control unit 3 sends a processing start signal 104 or 105 to the register 15a or 15b, the register is set to "1", and when the processing of the functional unit is completed. Processing end signals 106 and 107 are sent and this register is reset to "0".

The function unit non-operation state generation instruction detection unit 11 detects the instruction code of the instruction received in the instruction register 10 as follows.
It is determined whether or not the instruction is a functional unit non-operating state generation instruction. When the instruction is the functional unit non-operating state generation instruction, the signal line 101 is output to "1". At this time, the instruction supply stop signal issuing unit 12 determines whether or not all the functional units 4a and 4b have completed processing based on the information from the functional unit state detection unit 6, and if all functional units have not completed processing. “1” is output to the instruction supply stop signal line 100. While the instruction supply stop signal line 100 is “1”, the instruction register 10 continues to hold the instruction register 10 without issuing an instruction to the decoding unit 5. When the command supply is controlled in this way, all the functional units 4a and 4b are in the processing completed state.

FIG. 2 shows the format of the functional unit non-operating state generation command. The functional unit non-operation state generation instruction detection unit 11 detects whether the instruction code 20 in the instruction register 10 is the functional unit non-operation state life instruction code.

FIG. 3 shows a first configuration example of the instruction supply stop signal issuing section 12 in FIG. The signal line 101 indicates whether or not the instruction code 20 is the functional unit non-operation state generation instruction code, and the signal lines 102 and 103 are the functional units 4a and 4 respectively.
The processing incomplete state of b is shown. Reference numeral 200 is an AND circuit, and 201 is an OR circuit.

In this configuration, for example, when the functional unit 4a is in the processing incomplete state and the functional unit 4a is in the processing incomplete state, the signal line 101 is "1" and the signal line 102 is "1". , And the signal line 103 becomes “0”. At this time, the instruction supply stop signal line 100 becomes “1”, and the instruction is held in the instruction register 10. When the function unit 4a enters the processing completion state and the signal line 102 becomes "0", the instruction supply stop signal line 100 becomes "0", and the instruction register 10 sends an instruction to the instruction control unit 5.

FIG. 4 shows a second configuration example of the instruction supply stop signal issuing section 12 in FIG. The signal line 101 indicates whether or not the instruction code 20 is the functional unit non-operation state generation instruction code, and the signal lines 101-1 and 101-2 indicate the states of the specific functional units 4a and 4b waiting for the completion of processing, respectively. The signal line is indicated by the field portion 21 in the instruction register 10 and detected by the functional unit non-operation state generation instruction detection circuit 11 and sent to the instruction stop signal issuing unit 12 in the same manner as the signal line 101. The signal lines 102 and 103 are each functional unit 4
The processing incomplete state of a and 4b is shown. Reference numerals 202, 204 and 205 are AND circuits, and 203 is an OR circuit.

In this configuration, for example, when the functional unit 4a designated by the functional unit non-operation state generation command is in the unfinished state and the functional unit 4b is in the completed state, the command line 101,
102 and 101-1 are "1", and the signal lines 103 and 101-2 are "0". At this time, the instruction supply stop signal line 100 becomes “1”, and the instruction is held in the instruction register 2. The function unit 4a is in the processing completed state and the signal line 102
Is 0, the command supply stop signal line 100 is "0".
Then, the instruction register 10 sends an instruction to the instruction control unit 5.

[0017]

As described above, according to the present invention, it is possible to easily obtain a non-operating state of a functional unit, obtain an instruction execution time from the start to the end of instruction execution, and easily perform performance measurement.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a format of a functional unit non-operation state generation instruction.

3 is a diagram showing a first configuration example of an instruction supply stop signal issuing section 12 in FIG.

4 is a diagram showing a second configuration example of an instruction supply stop signal issuing unit 12 in FIG.

[Explanation of symbols]

 1 Main Storage Section 2 Instruction Holding Section 3 Instruction Control Section 4a, 4b Functional Section 5 Decoder Section 6 Functional Section Status Detection Section 10 Instruction Register 11 Functional Section Non-Operation Status Generation Instruction Detection Section 12 Instruction Supply Stop Signal Issuing Section 13 Decoder 14 Instruction Control circuit 15a, 15b register

Claims (2)

[Claims] 1. An instruction holding unit for reading and holding an instruction from a main storage unit, a plurality of functional units necessary for executing the instruction, an instruction in the instruction holding unit, and decoding the instruction according to the result of decoding the instruction. In an information processing device including an instruction control unit having a pipeline configuration including a plurality of stages that creates information necessary for executing an instruction and activates execution of the function unit, the instruction control unit includes the plurality of functions. A plurality of state detecting means for detecting the use state of the functional portion corresponding to each unit, and holding subsequent instructions in the instruction holding means until all the functional portions have been processed based on the detection result of the detecting means. An information processing apparatus comprising a means for continuing. 2. The instruction holding means corresponds to each of the plurality of functional units, and when the functional units are in a processing incomplete state, the subsequent instruction is kept to be held in the instruction holding unit. The information processing apparatus according to claim 1, wherein an instruction control field that defines an operation of the instruction control unit is provided, and a non-operation state is created for each functional unit.