JPH05342048A - Information processor - Google Patents

Information processor

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Publication number
JPH05342048A
JPH05342048A JP4151647A JP15164792A JPH05342048A JP H05342048 A JPH05342048 A JP H05342048A JP 4151647 A JP4151647 A JP 4151647A JP 15164792 A JP15164792 A JP 15164792A JP H05342048 A JPH05342048 A JP H05342048A
Authority
JP
Japan
Prior art keywords
instruction
unit
functional
holding
functional units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4151647A
Other languages
Japanese (ja)
Other versions
JP2789939B2 (en
Inventor
Yasuhiro Nishigaki
泰洋 西垣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4151647A priority Critical patent/JP2789939B2/en
Publication of JPH05342048A publication Critical patent/JPH05342048A/en
Application granted granted Critical
Publication of JP2789939B2 publication Critical patent/JP2789939B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Executing Machine-Instructions (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To exactly measure time at the time of performing pipeline processing. CONSTITUTION:By using a functional part state detection part 6 to detect the states of functional parts for executing instructions, following instructions are controlled so as to be continuously held in an instruction register 10 until all the functional parts 4a and 4b can execute them. Thus, time from the instruction execution to the end can be measured, and performance can be easily measured.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はパイプライン制御により
同時に命令実行可能な複数の機能部を有する情報処理装
置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a plurality of functional units capable of executing instructions simultaneously by pipeline control.

【0002】[0002]

【従来の技術】従来のこの種の情報処理装置は、各命令
の処理がパイプライン化されているため、後続命令の処
理の起動が先行命令の処理の完了を待たずに行われる。
2. Description of the Related Art In the conventional information processing apparatus of this type, since the processing of each instruction is pipelined, the processing of the subsequent instruction is started without waiting for the completion of the processing of the preceding instruction.

【0003】[0003]

【発明が解決しようとする課題】この従来の情報処理装
置では、性能測定等を目的として、ソフトウェアの処理
ルーチンの処理実行時間を計測しようとしても、処理完
了時の時間を計測できないという問題があった。そのた
め先行命令が全て完了するまで時間計測の処理命令の実
行を待たせることが必要となる。
However, this conventional information processing apparatus has a problem that the time at the completion of processing cannot be measured even if the processing execution time of the software processing routine is measured for the purpose of performance measurement or the like. It was Therefore, it is necessary to wait for the execution of the time measurement processing instruction until all the preceding instructions are completed.

【0004】[0004]

【課題を解決するための手段】本発明の情報処理装置
は、主記憶部から命令を読み出し保持する命令保持手段
と、命令実行に必要な複数の機能部と、前記命令保持手
段中の命令を解読し、該命令の解読結果に応じて該命令
の実行に必要な情報を作成し前記機能部に対して実行起
動をかける複数ステージからなるパイプライン構成の命
令制御部から構成される情報処理装置において、前記命
令制御部に、前記複数の機能部に対応して該機能部の使
用状態を検出する複数の状態検出手段と、該検出手段の
検出結果から全ての機能部が処理完了になるまで、後続
の命令を前記命令保持手段に保持し続ける手段を有する
ことを特徴とする。
An information processing apparatus according to the present invention stores an instruction holding unit for reading and holding an instruction from a main storage unit, a plurality of functional units necessary for executing the instruction, and an instruction in the instruction holding unit. An information processing apparatus comprising a pipelined instruction control unit that decodes, creates information necessary for executing the instruction in accordance with the result of decoding the instruction, and activates and executes the functional unit In the command control unit, a plurality of state detecting means for detecting a use state of the functional units corresponding to the plurality of functional units, and a detection result of the detecting unit until all the functional units are processed. , And has means for continuing to hold subsequent instructions in the instruction holding means.

【0005】[0005]

【実施例】次に、本発明の実施例について説明する。EXAMPLES Next, examples of the present invention will be described.

【0006】本発明の一実施例を示す図1を参照する
と、本実施例は主記憶部1,命令保持部2,命令制御部
3および2つの機能部4a,4bで構成される。
Referring to FIG. 1 showing an embodiment of the present invention, this embodiment comprises a main memory unit 1, an instruction holding unit 2, an instruction control unit 3 and two functional units 4a and 4b.

【0007】命令保持部2は命令レジスタ10を有して
おり、命令制御部3はデコーダ部5,機能部状態検出部
6,命令供給停止信号発行部12および命令制御回路1
4を有している。
The instruction holding unit 2 has an instruction register 10, and the instruction control unit 3 has a decoder unit 5, a function state detection unit 6, an instruction supply stop signal issuing unit 12 and an instruction control circuit 1.
Have four.

【0008】さらに、デコーダ部5は機能部無動作状態
生成命令検出部11およびデコーダ13を有し、また、
機能部状態検出部6は機能部4a,4bの状態を保持す
るレジスタ15a,15bを有する。
Further, the decoder section 5 has a functional section non-operation state generation instruction detection section 11 and a decoder 13, and
The functional unit state detection unit 6 has registers 15a and 15b for holding the states of the functional units 4a and 4b.

【0009】機能部4a,4bはそれぞれ加算パイプラ
イン,乗算パイプラインである。機能部はここでは説明
を簡単にするため2種類しか挙げていないが、このこと
が一般性を損ねないことは明白である。機能部4a,4
bはおのおの独立して同時に命令が実行できる。
The functional units 4a and 4b are an addition pipeline and a multiplication pipeline, respectively. Only two types of functional parts are mentioned here for the sake of simplicity, but it is clear that this does not impair generality. Functional parts 4a, 4
Each of b can independently execute instructions at the same time.

【0010】主記憶部1内の命令は命令レジスタ10に
読み出された後に命令制御部3に送られる。その命令は
デコード13で解読される。デコーダ13により解読さ
れた命令は命令制御回路14に送られ、命令制御回路1
4は命令を実行する機能部4a,4bが処理完了の場合
はその機能部4a,4bに命令実行に必要な情報を作成
し、実行起動をかける。命令が機能部4a,4bに送ら
れるとき、命令制御部3から処理開始信号104または
105がレジスタ15aもしくは15bに送られ、この
レジスタは“1”にセットされ、また機能部の処理が終
了すると処理終了信号106,107が送られこのレジ
スタは“0”にリセットされる。
The instruction in the main memory 1 is read to the instruction register 10 and then sent to the instruction controller 3. The instruction is decoded by the decode 13. The instruction decoded by the decoder 13 is sent to the instruction control circuit 14, and the instruction control circuit 1
When the functional units 4a and 4b that execute the instruction have completed the processing, 4 creates information necessary for executing the instruction in the functional units 4a and 4b and activates the execution. When the instruction is sent to the functional units 4a and 4b, the instruction control unit 3 sends a processing start signal 104 or 105 to the register 15a or 15b, the register is set to "1", and when the processing of the functional unit is completed. Processing end signals 106 and 107 are sent and this register is reset to "0".

【0011】機能部無動作状態生成命令検出部11は命
令レジスタ10に受信された命令の命令コードにより、
その命令が機能部無動作状態生成命令であるか否かを判
断し、命令が機能部無動作状態生成命令である場合は信
号線101は“1”に出力される。この時、命令供給停
止信号発行部12は、機能部状態検出部6の情報により
全ての機能部4a,4bが処理完了であるか否かを判断
し、全ての機能部が処理完了でなければ命令供給停止信
号線100は“1”が出力される。この命令供給停止信
号線100が“1”の間、命令レジスタ10はデコード
部5に命令を発行しないで命令レジスタ10に保持し続
ける。このように命令供給を制御すると、全ての機能部
4a,4bが処理完了状態になる。
The function unit non-operation state generation instruction detection unit 11 detects the instruction code of the instruction received in the instruction register 10 as follows.
It is determined whether or not the instruction is a functional unit non-operating state generation instruction. When the instruction is the functional unit non-operating state generation instruction, the signal line 101 is output to "1". At this time, the instruction supply stop signal issuing unit 12 determines whether or not all the functional units 4a and 4b have completed processing based on the information from the functional unit state detection unit 6, and if all functional units have not completed processing. “1” is output to the instruction supply stop signal line 100. While the instruction supply stop signal line 100 is “1”, the instruction register 10 continues to hold the instruction register 10 without issuing an instruction to the decoding unit 5. When the command supply is controlled in this way, all the functional units 4a and 4b are in the processing completed state.

【0012】図2は機能部無動作状態生成命令の形式を
示す。命令レジスタの10中の命令コード20が機能部
無動作状態生命命令コードであるか否かを機能部無動作
状態生成命令検出部11で検出するのである。
FIG. 2 shows the format of the functional unit non-operating state generation command. The functional unit non-operation state generation instruction detection unit 11 detects whether the instruction code 20 in the instruction register 10 is the functional unit non-operation state life instruction code.

【0013】図3は図1における命令供給停止信号発行
部12の第1の構成例である。信号線101は命令コー
ド20が機能部無動作状態生成命令コードであるか否か
を示し、信号線102,103は各々の機能部4a,4
bの処理未完了状態を示す。200はAND回路であり
201はOR回路である。
FIG. 3 shows a first configuration example of the instruction supply stop signal issuing section 12 in FIG. The signal line 101 indicates whether or not the instruction code 20 is the functional unit non-operation state generation instruction code, and the signal lines 102 and 103 are the functional units 4a and 4 respectively.
The processing incomplete state of b is shown. Reference numeral 200 is an AND circuit, and 201 is an OR circuit.

【0014】この構成では、例えば命令は機能部無動作
状態生成命令で機能部4aが処理未完了状態で4bが処
理完了状態であるとき、信号線101が“1”、信号線
102が“1”、信号線103は“0”になる。この
時、命令供給停止信号線100が“1”になり、命令が
命令レジスタ10に保持される。機能部4aが処理完了
状態になり信号線102が“0”になると命令供給停止
信号線100が“0”になり、命令レジスタ10は命令
制御部5に命令を送る。
In this configuration, for example, when the functional unit 4a is in the processing incomplete state and the functional unit 4a is in the processing incomplete state, the signal line 101 is "1" and the signal line 102 is "1". , And the signal line 103 becomes “0”. At this time, the instruction supply stop signal line 100 becomes “1”, and the instruction is held in the instruction register 10. When the function unit 4a enters the processing completion state and the signal line 102 becomes "0", the instruction supply stop signal line 100 becomes "0", and the instruction register 10 sends an instruction to the instruction control unit 5.

【0015】図4は図1における命令供給停止信号発行
部12の第2の構成例である。信号線101は命令コー
ド20が機能部無動作状態生成命令コードであるか否か
を示し、信号線101−1,101−2は処理完了を待
つ特定の機能部4a,4bの状態をそれぞれ示すもので
あり、命令レジスタ10内のフィールド部21で示され
機能部無動作状態生成命令検出回路11で検出し命令停
止信号発行部12へ信号線101と同様に送られてきた
信号線である。信号線102,103は各々の機能部4
a,4bの処理未完了状態を示す。202,204およ
び205はAND回路であり203はOR回路である。
FIG. 4 shows a second configuration example of the instruction supply stop signal issuing section 12 in FIG. The signal line 101 indicates whether or not the instruction code 20 is the functional unit non-operation state generation instruction code, and the signal lines 101-1 and 101-2 indicate the states of the specific functional units 4a and 4b waiting for the completion of processing, respectively. The signal line is indicated by the field portion 21 in the instruction register 10 and detected by the functional unit non-operation state generation instruction detection circuit 11 and sent to the instruction stop signal issuing unit 12 in the same manner as the signal line 101. The signal lines 102 and 103 are each functional unit 4
The processing incomplete state of a and 4b is shown. Reference numerals 202, 204 and 205 are AND circuits, and 203 is an OR circuit.

【0016】この構成では、例えば命令は機能部無動作
状態生成命令で指定した機能部4aが処理未完了状態で
機能部4bが処理完了状態であるとき、信号線101,
102および101−1が“1”、信号線103および
101−2は“0”となる。この時、命令供給停止信号
線100が“1”になり、命令が命令レジスタ2に保持
される。機能部4aが処理完了状態になり信号線102
が“0”になると、命令供給停止信号線100が“0”
になり、命令レジスタ10は命令制御部5に命令を送
る。
In this configuration, for example, when the functional unit 4a designated by the functional unit non-operation state generation command is in the unfinished state and the functional unit 4b is in the completed state, the command line 101,
102 and 101-1 are "1", and the signal lines 103 and 101-2 are "0". At this time, the instruction supply stop signal line 100 becomes “1”, and the instruction is held in the instruction register 2. The function unit 4a is in the processing completed state and the signal line 102
Is 0, the command supply stop signal line 100 is "0".
Then, the instruction register 10 sends an instruction to the instruction control unit 5.

【0017】[0017]

【発明の効果】本発明により容易に機能部無動作状態が
得られ、命令実行開始から終了までの命令実行時間が得
られ、性能測定が容易に行えるという効果がある。
As described above, according to the present invention, it is possible to easily obtain a non-operating state of a functional unit, obtain an instruction execution time from the start to the end of instruction execution, and easily perform performance measurement.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のブロック図である。FIG. 1 is a block diagram of an embodiment of the present invention.

【図2】機能部無動作状態生成命令の形式を示す図であ
る。
FIG. 2 is a diagram showing a format of a functional unit non-operation state generation instruction.

【図3】図1における命令供給停止信号発行部12の第
1の構成例を示す図である。
3 is a diagram showing a first configuration example of an instruction supply stop signal issuing section 12 in FIG.

【図4】図1における命令供給停止信号発行部12の第
2の構成例を示す図である。
4 is a diagram showing a second configuration example of an instruction supply stop signal issuing unit 12 in FIG.

【符号の説明】[Explanation of symbols]

1 主記憶部 2 命令保持部 3 命令制御部 4a,4b 機能部 5 デコーダ部 6 機能部状態検出部 10 命令レジスタ 11 機能部無動作状態生成命令検出部 12 命令供給停止信号発行部 13 デコーダ 14 命令制御回路 15a,15b レジスタ 1 Main Storage Section 2 Instruction Holding Section 3 Instruction Control Section 4a, 4b Functional Section 5 Decoder Section 6 Functional Section Status Detection Section 10 Instruction Register 11 Functional Section Non-Operation Status Generation Instruction Detection Section 12 Instruction Supply Stop Signal Issuing Section 13 Decoder 14 Instruction Control circuit 15a, 15b register

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】主記憶部から命令を読み出し保持する命令
保持手段と、 命令実行に必要な複数の機能部と、 前記命令保持手段中の命令を解読し、該命令の解読結果
に応じて該命令の実行に必要な情報を作成し前記機能部
に対して実行起動をかける複数ステージからなるパイプ
ライン構成の命令制御部から構成される情報処理装置に
おいて、 前記命令制御部に、前記複数の機能部に対応して該機能
部の使用状態を検出する複数の状態検出手段と、該検出
手段の検出結果から全ての機能部が処理完了になるま
で、後続の命令を前記命令保持手段に保持し続ける手段
を有することを特徴とする情報処理装置。
1. An instruction holding unit for reading and holding an instruction from a main storage unit, a plurality of functional units necessary for executing the instruction, an instruction in the instruction holding unit, and decoding the instruction according to the result of decoding the instruction. In an information processing device including an instruction control unit having a pipeline configuration including a plurality of stages that creates information necessary for executing an instruction and activates execution of the function unit, the instruction control unit includes the plurality of functions. A plurality of state detecting means for detecting the use state of the functional portion corresponding to each unit, and holding subsequent instructions in the instruction holding means until all the functional portions have been processed based on the detection result of the detecting means. An information processing apparatus comprising a means for continuing.
【請求項2】前記命令保持手段中に、前記複数の機能部
の各々に対応し、該機能部が処理未完了状態である場合
には後続の命令を前記命令保持部に保持し続けるよう前
記命令制御部の動作を規定する命令制御フィールドを設
け、前記機能部単位で無動作状態を作成することを特徴
とする請求項1記載の情報処理装置。
2. The instruction holding means corresponds to each of the plurality of functional units, and when the functional units are in a processing incomplete state, the subsequent instruction is kept to be held in the instruction holding unit. The information processing apparatus according to claim 1, wherein an instruction control field that defines an operation of the instruction control unit is provided, and a non-operation state is created for each functional unit.
JP4151647A 1992-06-11 1992-06-11 Information processing device Expired - Lifetime JP2789939B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4151647A JP2789939B2 (en) 1992-06-11 1992-06-11 Information processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4151647A JP2789939B2 (en) 1992-06-11 1992-06-11 Information processing device

Publications (2)

Publication Number Publication Date
JPH05342048A true JPH05342048A (en) 1993-12-24
JP2789939B2 JP2789939B2 (en) 1998-08-27

Family

ID=15523140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4151647A Expired - Lifetime JP2789939B2 (en) 1992-06-11 1992-06-11 Information processing device

Country Status (1)

Country Link
JP (1) JP2789939B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01114944A (en) * 1987-10-28 1989-05-08 Mitsubishi Electric Corp Pipe-line system processor
JPH02181236A (en) * 1989-01-05 1990-07-16 Nec Corp Debug device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01114944A (en) * 1987-10-28 1989-05-08 Mitsubishi Electric Corp Pipe-line system processor
JPH02181236A (en) * 1989-01-05 1990-07-16 Nec Corp Debug device

Also Published As

Publication number Publication date
JP2789939B2 (en) 1998-08-27

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