JPH02181236A - Debug device - Google Patents

Abstract

PURPOSE:To efficiently execute the debug even if a software for a test is not developed, and also, to easily execute the debug by a software used by a general user by providing an instruction prefetching circuit and an OR gate, etc. CONSTITUTION:When an instruction prefetch instruction signal is inputted through a signal line 101, an instruction prefetching circuit 1 prefetches one piece of instruction and sends it out to an arithmetic circuit 2. The circuit 2 executes a processing of an instruction prefetched by the circuit 1, and outputs an instruction processing end signal to an OR gate 3, when the processing is ended. The gate 3 takes OR of the instruction processing end signal from the circuit 2, a debug mode signal from a mode register 4 inputted through an inverter 5, and an instruction processing start signal from an external debug instructing circuit 6, and outputs an instruction prefetch instructing signal to the circuit 1. In this regard, to the register 4, a debug mode is set from the circuit 6. In such a way, even if a software for a test is not developed, the debug can be executed efficiently, and also, the debug can be executed easily by a software used by a general user.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a debugging device, and particularly to debugging processing for an information processing device.

BACKGROUND ART Conventionally, in an information processing apparatus having an instruction prefetching means, internal operations may differ depending on the previous and subsequent instructions even when processing the same instruction.

For example, if the instruction to be processed 17 uses a specific register, and the contents of that specific register have been rewritten by the preceding instruction, processing of that instruction must wait until the contents of that specific register are updated. Must be.

As mentioned above, even when processing the same instruction, the internal operation differs depending on the order of the instructions, so the output obtained by processing the instruction sequence using software and the output between the instruction sequence Instructions that do not affect the result [for example, N0P (no operation 1n
The device was debugged by inserting a step (struction) step, etc., and comparing the output obtained by processing the instruction sequence.

In such conventional information processing devices, an instruction that does not affect the output result is inserted between the output obtained by processing a sequence of instructions using software and the sequence of instructions. Since we were debugging the device by comparing the output obtained by processing the sequence, we could confirm that only that sequence of instructions was working without any errors.
3.2 In order to ensure the operation of many other instruction sequences, many rough pieces of software must be created, which has the disadvantage of poor efficiency.

Okay, the above method uses rough 1~ used by general users.
This has the drawback that it does not confirm that the software is working properly, and debugging is less effective.

OBJECTS OF THE INVENTION The present invention provides &1. This was developed to eliminate the shortcomings of the previous version, and allows for efficient debugging without developing test software. The aim is to provide 1% of devices that can perform this.

Composition of the Invention A debugging device according to the present invention is an information processing device for processing 1j instructions prefetched by t instruction prefetching means; The present invention is characterized in that it includes means for restricting the instruction prefetching means to prefetch the instructions.

Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, an instruction prefetch circuit 1 prefetches one instruction when an instruction prefetch instruction signal is input via a signal line 101. . This prefetched instruction is sent to the arithmetic circuit 2 via the signal line 102.

The arithmetic circuit 2 executes processing of the instruction prefetched by the instruction prefetch port I\81, and when the processing of the instruction is completed, outputs an instruction processing end signal to the OR gate 3 via the signal line 103.

The OR gate 3 receives an instruction processing end signal from the arithmetic circuit 2,
A debug mode signal from the mode register 4 input via the inverter 5 and signal lines 106 and 107;
The logical OR with the instruction processing start signal from the external debug instruction circuit 6 input via the signal line 105 is taken, and the signal line 1 is
An instruction prefetch instruction signal is output to the instruction prefetch circuit 1 via 01.

A debug mode is set in the mode register 4 from the external debug instruction circuit 6 via the signal line 104.

FIG. 2 is a diagram showing the flow of instruction processing during normal operation in one embodiment of the present invention, and FIG. 3 is a diagram showing the flow of instruction processing in debug mode in one embodiment of the present invention. In these figures, D represents the instruction decode cycle, A represents the virtual address creation cycle, P represents the paging cycle, C represents the cache marketing cycle, T represents the align cycle, E represents the arithmetic processing cycle, and W represents the arithmetic processing cycle. A write cycle is shown respectively.

Further, the instruction decode cycle D, the virtual address creation cycle A, the paging cycle P, and the cache read cycle C are cycles for instruction prefetching, and these cycles are processed by the instruction prefetching circuit 1.

The operation of one embodiment of the present invention will be explained using these FIGS. 1 to 3.

First, during normal operation, since the debug mode is not set in the mode register 4, "1" is input to the OR gate 3 as a debug mode signal, and "1" is input from the OR gate 3 to the instruction prefetch circuit 1 as an instruction prefetch instruction signal.
is output continuously.

Therefore, the instruction prefetch circuit 1 performs each of the instruction decode cycle D, virtual address creation cycle A, paging cycle P, and cache read cycle C for instructions ① to IV, and the outputs thereof are sequentially transferred to the arithmetic circuit 2. 6 The arithmetic circuit 2 executes the processing of the arithmetic processing cycle E and the write cycle W of instructions 1 to IV based on the transferred output from the instruction prefetch circuit 1, and the information obtained in the arithmetic circuit 2 by executing the instructions The calculated results are stored in a memory (not shown).

Next, when debugging, the external debug instruction circuit 6 writes “1” to the mode register 4 as the debug mode.
is set, and "1pa" is output from the external debug instruction circuit 6 to the OR gate 3 for one cycle as an instruction start signal.

As a result, the OR gate 3 outputs °'1'' to the instruction prefetch circuit 1 as an instruction prefetch instruction signal.

When the instruction prefetching instruction signal is inputted to the instruction prefetching circuit 1, the instruction prefetching circuit 1 prefetches one instruction 1.

That is, the instruction prefetch circuit 1 performs the instruction decode cycle D, virtual address creation cycle A, paging cycle P, and cache read cycle C for this instruction 1, and transfers the output to the arithmetic circuit 2.

In the arithmetic circuit 2, the processing of the arithmetic processing cycle E and the write cycle W of the instruction T is executed based on the transferred output from the instruction prefetch circuit 1, and when the processing of this instruction "1" is output for only one cycle as a processing end signal.

When the OR gate 3 receives the instruction processing end signal from the arithmetic circuit 2, it outputs "1" to the instruction prefetch circuit 1 as an instruction prefetch instruction signal for one cycle.

As a result, the instruction prefetch circuit 1 prefetches the next instruction (2) in the same way as the above-mentioned processing, and processes the instruction decode cycle D, virtual address creation cycle A, paging cycle P, and cache read cycle C of the instruction (2). is performed, and its output is transferred to the arithmetic circuit 2.

Similarly, when the processing of the instruction ■ is completed in the arithmetic circuit 2,
The arithmetic circuit 2 outputs "1pa" for one cycle as an instruction processing end signal to the OR gate 3, and the instruction prefetch circuit 1 prefetches the next instruction (2).

As mentioned above, when the debug mode is set in the mode register 4 by the external debug instruction circuit 6 and the instruction start signal is output to the OR gate 3, from then on, every time the processing of the instructions ■ and ■ is completed in the arithmetic circuit 2, In the instruction prefetch circuit 1, the next instructions (2) and (2) are sequentially prefetched one by one.

Therefore, by comparing the calculation result obtained by the calculation circuit 2 at this time with the calculation result obtained by the calculation circuit 2 during normal operation and stored in the memory, software for debugging and testing the device is developed. You can debug efficiently without any trouble.

Further, in the debug mode, instructions are prefetched every time the processing of one instruction is completed, so it is easy to debug using software used by general users.

In this way, by causing the instruction prefetch circuit 1 to prefetch one instruction each time the arithmetic circuit 2 finishes processing one instruction in the debug mode, the processing results during normal operation and the debug mode can be Since you can easily compare the processing results at the time of testing, you can debug efficiently without developing test software.
Debugging can be easily performed using software used by general users.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, instructions are prefetched in response to the completion of instruction processing in debug mode, thereby efficiently debugging without developing test software. This has the advantage that debugging can be easily performed using software used by general users.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a diagram showing the flow of instruction processing during normal operation in an embodiment of the invention, and Fig. 3 is an embodiment of the invention. FIG. 3 is a diagram showing the flow of instruction processing in debug mode in FIG. Explanation of symbols of main parts■・・・Instruction prefetch circuit 2・・・Arithmetic circuit 3・・・OR gate 4・・・Mode register 6・・・External Debug instruction circuit

Claims (1)

[Claims] (1) A debugging device for an information processing device that processes an instruction prefetched by an instruction prefetching means, wherein the instruction prefetching means is configured to prefetch the instruction in response to completion of processing of the instruction in a debug mode. A debugging device characterized by having a means for controlling.