JPH05340996A - Burn-in method for bare chip ic - Google Patents

Abstract

PURPOSE:To achieve a method for carrying out required burn-in conveniently on a bare chip IC. CONSTITUTION:Electrode pads 1a of a bare chip IC 1 to be tested and corresponding electrode pads 2a on a testing substrate 2 are arranged through an anisotropic rubber layer 6, while being connected electrically, on the testing substrate 2 provided with the electrode pads 2a corresponding with the electrode pads 1a on the bare chip IC 1 to be tested, and then required burn-in is carried out. In other words, pressure is applied selectively between the electrode pads 1a on the bare chip IC 1 to be tested and the corresponding electrode pads 2a on the testing substrate 2 in order to provide a conductive region 6a at a corresponding position on the interposed anisotropic rubber layer 6, and then burn-in is carried out while connecting the electrode pads 1a, 2a electrically.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burn-in method for bare chip ICs.

[0002]

2. Description of the Related Art As is well known, an IC element is, for example, Si.
A large number of wafers are formed on a wafer, which are cut and separated to form a so-called bare chip. And this kind of I
For the C element, a tentative electrical evaluation (initial evaluation) is performed in the wafer state, and after packaging or assembling a selected acceptable bare chip IC,
Burn-in test is being conducted. That is, an IC element which is determined as a non-defective product by being classified into a non-defective product and a defective product in the initial evaluation is put into practical use as a non-defective product as it is after being formed into a bare chip.

[0003]

However, the method of performing the burn-in test after packaging or assembling the bare chip IC as described above has the following disadvantages. That is, if the product is judged to be defective in the accelerated test (usually, a voltage 1.2 times higher than the standard voltage is applied at a constant high temperature) as a predictive life test after packaging or assembling, the packaging or The assembled product will be discarded as a defective product. That is, as a result, a bare chip IC, which becomes a defective product in the life test, is packaged or assembled, which causes a large loss in terms of manufacturing cost. Moreover, the accelerated test after packaging or assembly requires a comparatively large space and a comparatively large burn-in furnace, which causes a problem in terms of equipment.

Further, C for directly mounting the bare chip IC
In the OB (chip on board) method and the flip chip method, it is effective to electrically connect and arrange the minute input / output terminals (electrode pads) of the bare chip IC with the corresponding electrode pads on the test substrate. Since there is no such method, the burn-in test may be omitted in some cases, and there was a problem in the reliability of the mounted product. That is, in order to connect the fine electrode pad of the bare chip IC to the corresponding electrode pad on the test substrate, a fine conductive ball is selectively supplied / placed between the electrode pad surfaces by a printing method or the like. It has also been attempted to selectively supply the minute conductive spheres.
Since the arrangement is complicated or difficult and not practical,
Often, the in-line test is omitted, resulting in reduced reliability of the mounted product and eventually cost increase.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a method capable of easily performing a required burn-in in the form of a bare chip IC.

[0006]

A bare chip IC burn-in method according to the present invention is a bare chip IC to be tested on a test substrate having an electrode pad group corresponding to the electrode pads of the bare chip IC to be tested. It is characterized in that the electrode pad of the IC and the corresponding electrode pad on the test substrate are electrically connected and arranged through the anisotropic conductive rubber layer to perform the required burn-in.

[0007]

According to the present invention, the bare chip IC under test is tested.
An anisotropic conductive rubber layer is interposed between the corresponding electrode pad on the surface of the test substrate and the corresponding electrode pad on the surface of the test substrate. The anisotropically conductive rubber layer regions that are in contact with each other can be selectively made conductive to make electrical connection. That is, the anisotropic conductive rubber layer and the bare chip IC under test are sequentially aligned and stacked on the surface of the test substrate, and the anisotropic conductive rubber layer contacts the electrode pad surface when the bare chip IC under test is pressed. The region is selectively made conductive so that the electrical connection between both electrode pads is easily and surely achieved, and the required burn-in can be achieved with high reliability.

[0008]

EXAMPLES Examples of the present invention will be described below with reference to FIG. 1 which schematically shows the embodiments of the present invention.

FIG. 1 is a sectional view of an embodiment,
First, a test substrate 2 configured as follows is prepared. That is, a test substrate 2 including an electrode pad 2a corresponding to the electrode pad 1a of the bare chip IC1 to be tested, a wiring 2b connected to these electrode pads 2a, and an external connection terminal 2c is prepared. Then, the test substrate 2 is placed on the base substrate 3 including the lock mechanism 3a and the hinge mechanism 3b. It should be noted that one end is rotatably supported by the hinge mechanism 3b, and the other end side is locked by the lock mechanism 3a, and the pressing plate 5 is arranged to face the base substrate 3 via a required spacer 4. ing. Here, the height of the spacer 4 is the thickness of the bare chip IC 1 under test, the electrode pad 1
It is selected and set according to the heights of a and 2a, the thickness of the anisotropic conductive rubber layer 6 (the amount of deformation required for making it conductive), and the like.

An anisotropic conductive rubber layer (for example, anisotropic conductive silicone rubber layer) 6 having a thickness of about 0.1 to 0.3 mm is positioned on the surface of the test substrate 2 arranged on the base substrate 3 by a mounter. After the placement, the bare chip IC1 to be tested prepared in advance is positioned and placed on the anisotropic conductive silicone rubber layer 6 by the mounter. The anisotropically conductive rubber layer used here may be a material other than the anisotropically conductive silicone rubber as long as its pressed portion (area) is selectively made conductive by so-called pressing. As the conductor for imparting conductivity, the same kind of metal powder as the electrode pad 1a of the bare chip IC1 to be tested, the electrode pad 2a or the wiring 2b of the test substrate 2 and the like is preferable.

Next, while controlling the distance between the test substrate 2 and the pressing plate 5 by the spacer 4, a lock mechanism is used.
By driving the hinge mechanism 3b and the hinge mechanism 3a, the bare chip IC1 under test is pressed with an appropriate pressure. Due to this pressurization, the anisotropic conductive silicone rubber layer 6 interposed between the electrode pad 1a surface of the bare chip IC1 under test and the electrode pad 2a surface of the test substrate 2 comes into contact with both electrode pad 1a, 2a surfaces. A conductive area 6a is selectively formed between the area surfaces to be formed, and the electrode pads 1a and 2a are electrically connected easily and reliably. In this state, a predetermined current / signal is applied to the external connection terminal of the test board 2.
Left in a high-temperature furnace maintained at a predetermined temperature while flowing to the electrode pad 2a via the connector 7 connected to 2c or applying a required voltage to the electrode pad 2a of the test substrate 2 via the connector 7. And the bare chip IC under test
Perform the required accelerated test (burn-in) for 1. In this burn-in, the predetermined region 6a of the anisotropic conductive silicone rubber layer 6 is selectively made conductive, so that the electrode pad 1a of the bare chip IC1 to be tested and the corresponding electrode pad 2a on the test substrate 2 are made. , And the required electrical connection is achieved reliably and reliably, and the required burn-in test is performed.

[0012]

As described above, according to the burn-in method of the present invention, the required accelerated life test can be easily and surely performed on the bare chip IC. That is, prior to packaging, or flip-chip mounting or chip
Prior to on-board mounting, bare chip ICs that have been left bare are subjected to the required burn-in (accelerated life test) without the need for complicated operations or special microfabrication.
The quality of life characteristics can be judged and identified. Therefore, after packaging the bare chip IC or after mounting or assembling, occurrence of a situation requiring replacement and repair can be completely avoided. Moreover, in the required burn-in (accelerated life test), an anisotropic conductive rubber layer is used for electrical connection between the electrode pad 1a of the bare chip IC1 to be tested and the corresponding electrode pad 2a on the test substrate 2. Since it uses, the damage and defects can be prevented by avoiding direct contact between both electrode pads.
As the metal diffusion between both electrode pads is reduced or prevented, deterioration of the electrode pads also disappears. Thus,
It can be said that the burn-in method for a bare chip IC according to the present invention brings many advantages in putting this type of bare chip IC into practical use by packaging it.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing an embodiment of a burn-in method for a bare chip IC according to the present invention.

[Explanation of symbols]

1 ... Bare chip IC for test 1a ... Electrode pad of bare chip IC for test 2 ... Test substrate 2a ... Electrode pad 2b of test substrate
Connection wiring 2c External connection terminal 3 Base board
3a ... Lock mechanism 3b ... Hinge mechanism 4 ... Spacer 5 ... Press plate 6 ... Anisotropic conductive rubber layer 6a ... Conductive area of anisotropic conductive rubber layer 7 ... Connector

Claims (1)

[Claims] 1. An electrode pad of the bare chip IC to be tested and a corresponding electrode pad on the test substrate are different on a test substrate having an electrode pad group corresponding to the electrode pad of the bare chip IC to be tested. A burn-in method for a bare chip IC, characterized in that the burn-in is performed by electrically connecting and arranging via a conductive rubber layer and performing a required burn-in.