JPH05335270A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing a semiconductor device with a wiring structure which is brought into contact with both P and N regions simultaneously at a low resistance. CONSTITUTION:(A): A gate oxide film 3 is formed all over an Si substrate 1 and a gate electrode of polysilicon 5 and high melting point silicide 6 is provided on a gate region of each MOSFET. A layer insulating film 4 is laminated all over, contact holes 10, 11 are formed in the layer insulating film 4 on an N-type drain region 12 and a P-type source region 13, and an electrode material 14 of good ohmic property with an N-type semiconductor is formed to a film on the contact holes 10, 11 and the layer insulating film 4. (B): Then, the electrode material 14 at the part of the contact hole 10 on the N-type drain region 12 is annealed. (C): The electrode material 14 excepting the part which is annealed is etched and a barrier metal 7is formed. (D): Lastly, a wiring 8 is formed of an electrode material 16 of good ohmic property with a P-type semiconductor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, it is suitable for simultaneously forming electrodes / wirings for connecting a p-type region and an n-type region formed on the same substrate. The present invention relates to a wiring forming method.

[0002]

2. Description of the Related Art Generally, as an electrode material of a semiconductor device,
Al (Aluminum) or A, which has many advantages such as low resistance and excellent workability, is cheap and easily available.
1 alloy is used. Considering the contact between the p-type and n-type regions of a semiconductor device using a Si (silicon) substrate and the Al electrode, ohmic contact can be made with the p-type region, but a pn junction is formed with the n-type region, which is high. It becomes resistance. This phenomenon becomes more remarkable as the fine processing is performed. Further, in the contact between the Al electrode and the Si substrate, Si is contained in the Al in an amount of 1 to 2% in order to prevent Al spikes. This Si is subjected to heat treatment (about 450 ° C.) after deposition of the Al film and During the subsequent cooling, there is a problem that it precipitates on the contact surface to increase the resistance, and this problem is becoming a major obstacle as the contact size becomes finer. For this reason, recently, Al electrodes and S
A structure in which a metal called a barrier metal is inserted between the i substrate and the i substrate is adopted.

FIG. 2 shows a partially enlarged view of a MOSFET as an example of a conventional semiconductor device using this barrier metal.
In the semiconductor device shown in the figure, an impurity diffusion layer (drain region) 2 is provided in a Si substrate 1, and a gate oxide film 3 is provided on the surface of the Si substrate 1. A gate electrode made of polysilicon 5 and high melting point silicide 6 is provided on the gate region, and an interlayer insulating film 4 is laminated on the entire surface. Contact holes 9 are formed in the interlayer insulating film 4 on the impurity diffusion layer 2 and the refractory silicide 6, respectively, and wirings 8 made of aluminum metal are provided in the contact holes 9 via the barrier metal 7. ing. At this time, by appropriately selecting the material of the barrier metal 7, it is possible to make ohmic contact with the n-type region, but in this case, it is not possible to make ohmic contact with the p-type region at the same time. Therefore, in many cases including the case shown in FIG. 2, as the electrode / wiring material, a material that can make contact with a certain resistance value in both p and n regions is selected and used.

[0004]

SUMMARY OF THE INVENTION When manufacturing CMOS, etc.
When an electrode is to be formed in both the type region and the n-type region at the same time, if a material having a low resistance is selected for one of the regions, the resistance becomes high for the other region, resulting in a low resistance at the same time for both regions. I couldn't. Further, when the barrier metal is used, it is possible to prevent the resistance increase of the Al electrode due to the precipitation of Si, but it is not possible to simultaneously make a low resistance ohmic contact to both the p and n regions.

These problems are remarkable especially when fine processing is performed, and there is a problem that it hinders the speeding up of the semiconductor device. Therefore, it is an object of the present invention to provide a method of manufacturing a semiconductor device having a contact structure with low resistance in both regions at the same time.

[0006]

As means for achieving the above object, a p-type region and an n-type region formed on the same substrate are used.
In a method of manufacturing a semiconductor device in which an electrode is formed on a mold region, a step of forming an insulating film on at least the p-type region and the n-type region on the substrate;
Forming contact holes at respective positions on the mold region and the n-type region, and forming a first electrode material having a good ohmic property with the n-type semiconductor on the insulating film and each contact hole. A step of annealing the first electrode material formed in the contact hole on the n-type region, and etching the first electrode material other than the annealed portion on the n-type region. Only as a barrier metal, and a step of forming a second electrode material having a good ohmic property with a p-type semiconductor to form a wiring on the barrier metal and on a region including the contact hole on the p-type region. An object of the present invention is to provide a method for manufacturing a semiconductor device, which comprises:

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method of manufacturing a semiconductor device of the present invention will be described with reference to FIGS. In addition, FIG. 1 shows CM
FIG. 3 is a partially enlarged cross-sectional view showing an embodiment of a method for manufacturing an OS, in each of which the left side is a drain region of an n-type MOSFET and the right side is a partially enlarged view showing a source region of a p-type MOSFET. First, a predetermined portion in the Si substrate 1 has n
N-type MOSFET by diffusing p-type and p-type impurities
Type drain region 12, an n-type source region (not shown) (hereinafter, only the n-type drain region 12 is representatively described), p
P-type source region 13 of p-type MOSFET and p (not shown)
A type drain region (hereinafter, only the p type source region 13 will be described as a representative) is formed. Then, the gate oxide film 3 is formed on the entire surface of the Si substrate 1, and the polysilicon 5 and the refractory silicide 6 are formed on the portions to be the gate regions of each MOSFET.
Gate electrodes made of Further, an interlayer insulating film 4 is laminated on the entire surface by a CVD method, and contact holes 10 and 11 are formed in the interlayer insulating film 4 on the n-type drain region 12 and the p-type source region 13 by dry etching using photolithography. This contact hole 1
When an n-type semiconductor such as WSi ₂ (tungsten silicide) and an electrode material (first electrode material) 14 having a good ohmic property are formed on 0 and 11 and the interlayer insulating film 4 by a sputtering method or a CVD method, the same figure ( It becomes like A).

Next, as shown in FIG. 1B, lamp annealing or laser annealing is performed using a mask 15 having a window opened only at the contact hole 10 on the n-type drain region 12 to perform the n-type drain. The electrode material 14 in the portion of the contact hole 10 on the region 12 is annealed.
Then, when isotropic plasma etching is performed using a CF ₄ -based gas having an appropriate output and gas pressure, the electrode material 14 other than the previously annealed portion is etched, and as shown in FIG. A barrier metal 7 is formed on the mold drain region 12. Finally, an electrode material (second electrode material) 16 composed of a barrier metal 7 and a metal such as Al having a good ohmic property with a p-type semiconductor or metal silicide (second electrode material) 16 is formed by a sputtering method or the like, and the wiring 8 is formed by etching. A semiconductor device as shown in (D) can be obtained.

At this time, the wiring 8 includes the barrier metal 7 and p.
Since the electrode material 16 having a good ohmic property is used with the n-type semiconductor, both the barrier metal 7 and the p-type source region 13 can be in ohmic contact, and the barrier metal 7 is in ohmic contact with the n-type drain region 12. Therefore, this semiconductor device has a low resistance contact structure in both the p and n regions.

Although the CMOS has been described as an example,
Any semiconductor device having a p-type region and an n-type region on the same substrate can be used, such as a bipolar transistor or B
It can be applied to a wide variety of semiconductor devices such as iCMOS.

[0011]

According to the method of manufacturing a semiconductor device of the present invention, the p-type region and the n-type region formed on the same substrate can be simultaneously wired with low resistance contacts. As a result, the semiconductor device can be driven at a low voltage, and the LSI
There is an effect that it is possible to increase the speed and improve the reliability.

[Brief description of drawings]

1A to 1D are partially enlarged cross-sectional views showing an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a configuration diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Si substrate 2 Impurity diffusion layer 3 Gate oxide film 4 Interlayer insulating film 5 Polysilicon 6 High melting point silicide 7 Barrier metal 8 Wiring 9, 10, 11 Contact hole 12 n-type drain region 13 p-type source region 14 Electrode material (first Electrode material) 15 Mask 16 Electrode material (second electrode material)

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device in which electrodes are formed on a p-type region and an n-type region formed on the same substrate, wherein an insulating film is formed on at least the p-type region and the n-type region on the substrate. A step of forming a contact hole at each position on the p-type region and the n-type region of the insulating film, and a step of forming an ohmic contact with the n-type semiconductor on the insulating film and each contact hole. Forming a good first electrode material, annealing the first electrode material formed in the contact hole on the n-type region, and forming the first electrode material other than the annealed portion. A step of etching the first electrode material to leave it as a barrier metal only on the n-type region; and forming a second electrode material having a good ohmic property with the p-type semiconductor on the barrier metal and before. The method of manufacturing a semiconductor device comprising more becomes that the step of forming a wiring in a region including the contact on holes on the p-type region.