JPH05328403A - Time base correction device - Google Patents

Abstract

PURPOSE:To obtain the time base correction device having an excellent characteristic to eliminate the time base fluctuation component of a low frequency by solving a band limit caused by even balance between a lockin range and a cut-off frequency of a PLL in the time base correction device controlling variably a delay in a CCD due to a phase error voltage of the PLL. CONSTITUTION:The device is provided with an integration means 9 integrating a phase correction error voltage from a phase correction circuit 7 receiving an error voltage resulting from the phase comparison by a phase comparator 5 being a component of the PLL, and an oscillating signal from a 2nd voltage controlled oscillator 8 controlled by an output voltage of the integration means 9 is fed to a clock of a CCD 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction device for removing a time axis fluctuation component from a signal having a time axis fluctuation component such as a reproduced signal in a video tape recorder, and more particularly to a charge coupled device ( The present invention relates to a time axis correction device using a so-called clock-driven analog variable delay line in which a delay time is controlled according to the frequency of a clock such as CCD: charge coupled device).

[0002]

2. Description of the Related Art Conventionally, as means for removing a time-axis fluctuation component included in a reproduced signal from a recording medium in a video signal reproducing apparatus, a synchronization signal included in the reproduced signal is a face-locked loop (hereinafter referred to as PLL). Type in
The phase comparison error voltage is used as a control signal to control the oscillation output of the voltage-controlled oscillator, and an analog variable delay line whose delay amount is controlled using the oscillation output as a clock is used. There is a time axis correction method that changes. The outline is shown in FIG.

In FIG. 4, a video signal input from a video signal input terminal 1 is input to a horizontal synchronizing signal separation circuit 4 and a clock-driven analog variable delay line 3, in this example a charge coupled device (hereinafter referred to as CCD). Supplied. The horizontal synchronizing signal separated by the horizontal synchronizing signal separating circuit 4 is applied to a phase comparator 5 and phase-compared with an oscillation output signal of a first voltage controlled oscillator 6 whose oscillation frequency is substantially the same as that of the horizontal synchronizing signal. It The error voltage phase-compared by the phase comparator 5 is applied to the second voltage controlled oscillator 8 as a control voltage, and the phase difference is corrected by the phase correction circuit 7.
The voltage controlled oscillator 6 is applied as a control voltage. Here, the loop including the phase comparator 5, the phase correction means 7, and the first voltage controlled oscillator 6 constitutes a PLL.
The oscillation signal of the second voltage controlled oscillator 8 is the CCD 3
It is supplied as a clock. Therefore, the CCD is changed by the frequency change of the oscillation signal of the second voltage controlled oscillator 8.
In 3, the video signal has its delay time varied so as to correct the time base fluctuation, and is guided to the output terminal 2 as a signal which does not include the time base fluctuation or is improved. in this way,
The time axis correction circuit shown in FIG. 4 variably controls the delay amount of the CCD 3 by the phase error voltage obtained from the PLL.

[0004]

As is well known, such a conventional device does not operate unless the PLL is locked. Therefore, the PLL is designed so that its lock-in range (capture range) is relatively wide. But,
If the cutoff frequency of the PLL is lowered to detect a low frequency phase error, the lock-in range is also narrowed. Therefore, the PLL lock-in range and P
Since the balance of the cutoff frequency of LL must be found, the band in which the time axis fluctuation component can be removed is limited. Further, since the error voltage is a differential system with respect to the phase below the cutoff frequency of the PLL and a low frequency phase error component is difficult to detect, the low frequency time due to the drive system of the recording medium of the video signal reproducing apparatus is low. There is a drawback that it is not suitable for removing the axial fluctuation component.

[0005]

In order to solve the above-mentioned problems, the time axis correction apparatus of the present invention is provided with means for integrating the phase comparison error voltage of the PLL, and the clock frequency of the CCD is varied by the output voltage thereof. It controls the voltage controlled oscillator.

[0006]

With the above structure, the present invention can detect a phase error component of a low frequency equal to or lower than the cutoff frequency of the PLL in a state where the cutoff frequency of the PLL is optimized so that the lock-in range of the PLL is widened. I can.

[0007]

1 is a block diagram showing a first embodiment of a time axis correction apparatus of the present invention, and the same parts as those of the conventional structure shown in FIG. 4 are designated by the same reference numerals. The difference is that the error voltage phase-corrected by the phase correction circuit 7 is applied as a control voltage to the second voltage-controlled oscillator 8 via the integrator 9, so that the phase is maintained below the cutoff frequency of the PLL. In contrast, the phase error voltage of the differential system is integrated. Therefore, the output voltage of the integrator 9 has a constant level regardless of the frequency. In other words, at a frequency equal to or lower than the cutoff frequency of the PLL, a constant level phase error voltage can be obtained, so that a low frequency phase fluctuation component can be detected. In the CCD 3 which is supplied with the oscillation signal of the second voltage controlled oscillator 8 controlled by the output voltage of the integrator 9 as a clock, the delay time of the video signal is varied so as to correct the time base fluctuation. , Is introduced to the output terminal 2 as a signal which does not include time axis fluctuation or is improved. As described above, the time axis correction device shown in FIG. 1 variably controls the delay amount of the CCD 3 by the phase error voltage obtained by integrating the error voltage obtained from the PLL.

FIG. 2 shows the transfer functions of the elements shown in FIG.
A block diagram is shown. In the figure, Kd is the gate of the phase comparator 5.
In, Ku is the gain of the voltage controlled oscillator 6, τ₁ And τ₂ 
(Τ ₁ > Τ₂ ) Is the time constant of the phase compensation circuit 7, Kv is the voltage
Gain of control oscillator 8, N is the number of shift stages of CCD 3, T
_H Indicates the cycle of the horizontal synchronizing signal. Here, in the figure
Transfer function Y related to phase of system₁ (S) is the input signal
Signal and output signal₁ (S) and θ₂ (S) and
Then, it is represented by (Equation 1).

[0009]

[Equation 1]

Now, K ₁ = K _d K _u , K ₂ = 2πNK _d K _v
/ When T _H (Equation 1) is (the number 2).

[0011]

[Equation 2]

However,

[0013]

[Equation 3]

[0014] FIG. 3 is a block diagram showing a second embodiment of the time axis correction apparatus of the present invention. The difference from the block diagram of the first embodiment is that the output of the phase compensation circuit 7 is input to the integrator 9. Instead of this, the output of the phase comparator 5 is directly applied.

FIG. 4 is a block diagram showing the transfer function of each element of FIG. Here, the transfer function Y ₂ (S) related to the phase of the system in the figure is represented by (Equation 4).

[0016]

[Equation 4]

Now, K ₁ = K _d K _u , K ₂ = 2πNK _d K _v
/ When T _H (Equation 4) becomes (5).

[0018]

[Equation 5]

However,

[0020]

[Equation 6]

[0021] In the above (Equation 2) and (Equation 5), y = 20log ₁₀ | Y (jω) with s = jω
The frequency characteristic of | is shown in FIG. However, Y is Y ₁ and Y ₂
Is. In the figure, when the vertical axis is y (dB) and the horizontal axis is the angular frequency ω, and the vertical axis is 0 dB, the jitter is not corrected at all, and the larger the absolute value is with the negative sign, the better the jitter is corrected. It means that.

Therefore, the jitter of the CCD output signal is y = 20 log ₁₀ when the jitter angular frequency is smaller than ω _0.
It is corrected to be | 1-K ₂ / K ₁ | dB, and increases from ω ₀ to ω ₁ with a slope of +12 dB / oct, and when it is larger than ω ₁ , y = 0 dB and no correction is made. ..

[0023]

As described above, according to the configuration of the present invention, P
Since it is possible to detect a low-frequency phase error in a state in which the cut-off frequency is optimized so that the lock-in range of the LL becomes wide, it is possible to detect a low-frequency phase error particularly due to the drive system of the recording medium of the video signal reproducing apparatus. It is possible to remove the time-axis fluctuation component, which is extremely effective in practice.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a time axis correction device according to a first embodiment of the present invention.

FIG. 2 is a block diagram in which each element of the time axis correction device in the first embodiment of the present invention is displayed as a transfer function.

FIG. 3 is a block diagram showing a main part of a time axis correction device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing the transfer function of each element of the time axis correction device according to the second embodiment of the present invention.

FIG. 5 is a frequency characteristic diagram of a transfer function of the time axis correction device in the first and second embodiments of the present invention.

FIG. 6 is a block diagram showing a main part of a conventional time axis correction device.

[Explanation of symbols]

 1 video signal input terminal 2 video signal output terminal 3 CCD 4 horizontal synchronizing signal separation circuit 5 phase comparator 6 voltage controlled oscillator 7 phase correction circuit 8 voltage controlled oscillator 9 integrator

Claims (2)

[Claims] 1. An analog variable delay line whose delay time is controlled according to the frequency of a clock signal, a horizontal sync signal separation circuit for separating a horizontal sync signal in a video signal supplied to the analog delay line, and 1. A phase comparator for phase-comparing the oscillation output signal of the voltage-controlled oscillator and the horizontal synchronizing signal separated by the horizontal synchronizing signal separating circuit, and the phase comparison of the phase comparison error voltage of the phase comparator. It has a phase correction circuit supplied to the voltage controlled oscillator as a control voltage, a means for integrating the phase comparison error voltage by the phase correction circuit, and a second voltage controlled oscillator whose oscillation frequency is controlled by the output of the integration means. A time axis correction device, wherein the output of the second voltage controlled oscillator is supplied as a clock of the analog variable delay line. 2. An analog variable delay line whose delay time is controlled according to the frequency of a clock signal, a horizontal sync signal separation circuit for separating a horizontal sync signal in a video signal supplied to the analog delay line, and 1. A phase comparator for phase-comparing the oscillation output signal of the voltage-controlled oscillator and the horizontal synchronizing signal separated by the horizontal synchronizing signal separating circuit, and the phase comparison of the phase comparison error voltage of the phase comparator. It has a phase correction circuit which is supplied as a control voltage to the voltage controlled oscillator, a means for integrating the phase comparison error voltage of the phase comparator, and a second voltage controlled oscillator whose oscillation frequency is controlled by the output of the integrating means. A time axis correction device, wherein the output of the second voltage controlled oscillator is supplied as a clock of the analog variable delay line.