JP2679032B2 - Video disk playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention provides a video disc reproducing apparatus with a low-cost configuration that does not deteriorate the transfer characteristic of jitter (deviation in the time axis direction) of the reproduced signal. Regarding what can be corrected. [Prior Art] A video disc recording system is an analog system in which an FM-modulated signal is recorded as it is with pit lengths, short densities, and density. For this reason, if there is a time-axis fluctuation due to rotation unevenness or eccentricity of the disc, it immediately appears as a fluctuation or color unevenness in the reproduced image. Therefore, the video disc reproducing apparatus has a TBC (time base collector) function for correcting the jitter of the reproduced signal. Regarding the TBC, the following two methods have been put into practical use in the conventional video disc reproducing apparatus. One is a three-axis optical pickup 10 configured by adding a tangential mirror 12 for time axis correction to a two-axis actuator 11 as shown in FIG. 2 (a), which is, so to speak, a mechanical TBC system. In this method, the tangential mirror 12 is shaken to correct a large shift corresponding to the fluctuation of the image, and the video detection circuit 14 performs FM detection to obtain a video signal, which is further based on the color burst signal. The color TBC16 corrects a minute shift corresponding to the shift of the color phase in the video signal to obtain a jitter-free video signal. The other one of the conventional TBC methods is, as shown in FIG. 2 (b), the binarized HF signal from the two-axis pickup 18 is first detected by the video detection circuit 20 and then converted into an analog video signal. TBC processing is performed. That is, in the video TBC22, a CCD (Charge Coupled Device) is used to resample this analog video signal and
A large shift corresponding to the fluctuation of the image is corrected by shaking the clock, and a slight shift corresponding to the color phase is corrected by the color TBC 23 as in the system of FIG. 2A. [Problems to be Solved by the Invention] In the system shown in FIG. 2 (a), since the optical pickup 10 is controlled by three axes, the structure is complicated, high working accuracy is required, and adjustment is difficult. It had the drawback of being very expensive. In addition, the reproduction band is limited by the color TBC16 after video demodulation, and there is a drawback that the resolution is reduced. In the system shown in FIG. 2 (b), the optical pickup
Although 18 requires only two axes, since the process of re-sampling the analog video signal with the video TBC22 and then restoring it again is interposed, the playback band is further limited as compared with the method of FIG. 2 (a). there were. SUMMARY OF THE INVENTION The present invention aims to solve the above-mentioned drawbacks of the prior art, and to provide a video disc reproducing apparatus capable of performing time axis correction at a low cost with almost no deterioration in transfer characteristics. [Means for Solving Problems] Pickup means for obtaining a binarized HF signal pulse-FM-modulated from a recording pit on a video disc, and the binarization
A CMOS inverter circuit to which the HF signal is directly input and a circuit for detecting a time base error included in the binarized HF signal are provided, and the power supply voltage of the CMOS inverter circuit is changed according to the detected time base error. A time axis correcting means for electrically changing the time axis of the binarized HF signal and an FM detecting means for obtaining a video disk reproduction signal by pulse FM detecting the time axis corrected binarized HF signal. Is to have. [Operation] According to the solving means of the present invention, the binarized HF signal from the pickup is directly input to the CMOS inverter circuit for time axis correction, and then pulse FM detection is performed.
According to this, since the time axis correction is performed using the CMOS inverter circuit as the binarized HF signal, the time axis correction can be performed with almost no deterioration in the signal transfer characteristic, and a wide reproduction band is secured. It is possible to realize high image quality. Further, the optical pickup need only be a biaxial type having a simple structure and can be constructed at low cost. Embodiment 1 One embodiment of the present invention is shown in FIG. In FIG. 1, a disk 11 is recorded with a pulse width modulated video + audio + synchronization signal that can take a continuous value on the time axis (that is, can change in an analog manner).
The optical pickup 10 uses a biaxial type that is movable in the vertical direction and the radial direction with respect to the disk 11. The reproduction signal of the disk 11 reproduced by the optical pickup 10 is a binarized signal having information on the time axis, and includes a fluctuation in the information track direction which is too fast to be compensated for by the disk rotation servo, that is, jitter. I'm out. This playback signal
It is input to the variable delay circuit 24 configured by a CMOS inverter circuit via the HF amplifier 22, and is output with a delay time that continuously changes according to the control voltage Vc. The output signal of the variable delay circuit 24 is passed through the buffer amplifier 26 to the bandpass filters 28, 30, 32 and the FM detection circuits 34, 3
The audio signals and the video signals of the left and right channels are output. The horizontal sync signal separation circuit 40 separates the horizontal sync signal included in the reproduction signal of the disk 11. The separated horizontal synchronizing signal controls the motor 18 via the disk servo circuit 16 to make the rotation of the disk 11 constant. Further, the horizontal synchronizing signal is phase-compared in the phase comparator 42 with the reference frequency signal created by dividing the oscillation signal of the crystal oscillator 44 by the division period, and the time axis error is detected. The output signal of the phase comparator 42 is smoothed by the low-pass filter 44, and the control voltage Vc thus obtained is passed through the buffer amplifier 46 to the variable delay circuit.
Join 24 control inputs. This series of loops constitutes a PLL (Phase Locked Loop), and the delay time of the variable delay circuit 24 is controlled so that the horizontal synchronizing signal is synchronized with the reference frequency signal. This is the time axis correction control by the horizontal synchronizing signal. A system for controlling the delay time of the variable delay circuit 24 according to the time axis error detection output of the phase comparator 42 corresponds to the time axis correcting means. That is, when the reproduction signal advances in the time axis direction with respect to the reference frequency signal, the control voltage
The delay time of the variable delay circuit 24 is lengthened by Vc, and the reproduction signal operates so as to be delayed in the time axis direction. Further, when the reproduction signal is delayed with respect to the reference frequency signal in the time axis direction, the delay time of the variable delay circuit 24 is shortened by the control voltage Vc, and the reproduction signal is operated to advance in the time axis direction. In this way, the jitter is absorbed. By the way, the variable delay circuit 24 is configured using the CMOS inverter as described above. As shown in FIG. 3, the CMOS inverter has a p-channel MOS-FET 50 and an n-channel MOS.
-FET52 is connected to each other between gates and drains, power supply voltage V _DD and V _SS are applied to the source, a signal is input to the gate through the input terminal 54, and the input signal is inverted from the drain to the output terminal 56. It is designed to output a signal. In this CMOS inverter 60, a delay time occurs between the input and the output. The delay time, as shown in FIG. 4, dependent on the supply voltage V _DD -V _SS, the power supply voltage V _DD -V _SS is small enough large delay time, greater rate of change. This is because the conductance of the device changes depending on the power supply voltage V _DD −V _SS and temperature. Therefore, using this property, the control voltage Vc
By controlling the voltage applied to the CMOS inverter 60, the delay time can be controlled arbitrarily. A delay time of about 3 to 5 ns is obtained for each COMS inverter 60, and a longer delay time can be obtained by connecting the COMS inverters 60 in multiple stages as shown in FIG. For example, if 10,000 stages are connected, a delay time of 30 to 50 μs can be obtained. 6 to 12 show examples of the configuration of the variable delay circuit 24 using the CMOS inverter. The variable delay circuit 24 of FIG. 6 is an MO for controlling the applied voltage between one of the MOS-FET 50 of the CMOS inverter 60 and the power supply voltage VDD.
The S-FET 62 is inserted. The binarized signal having information on the time axis obtained from the HF amplifier 22 of FIG. 1 is input from the input terminal 54, and the delayed signal is output from the output terminal 56. The control voltage Vc is input from the control input terminal c2,
When the control voltage Vc decreases with reference to the power supply voltage V _SS , C
The applied voltage of the MOS inverter 60 becomes large and the delay time becomes short. When the control voltage Vc becomes large with reference to the power supply voltage V _SS , the applied voltage of the CMOS inverter 60 becomes small and the delay time becomes long. The variable delay circuit 24 of FIG. 7 has voltage control system elements provided on both sides of a CMOS inverter 60. That is, the p-channel MOS-FET 50 and the power-supply voltage V _DD are connected between the p-channel MOS-
In addition to inserting the FET 62, an n-channel MOS-FET 64 is inserted between the n-channel MOS-FET 52 and the power supply voltage V _SS . In this case, two types of control voltages, Vc1 and Vc2, are used and input to the n-channel MOS-FET and the p-channel MOS-FET 62, respectively. These control voltages Vc1 and Vc2 are symmetrical voltages (V _DD −Dc2 =
Vc1−V _SS ). The variable delay circuit 24 of FIG. 8 includes control MOS-FETs 62 and 64 as C
It is provided inside the MOS inverter 60. The variable delay circuit 24 shown in FIG. 9 is provided with two control systems. The MOS-FET 62, 64 shown in FIG.
64 'are connected in parallel. As will be described later, this is used for dual control such as coarse control by a horizontal synchronizing signal and fine control by a color burst signal. The variable delay circuit 24 shown in FIG. 10 is obtained by connecting the voltage control elements shown in FIG. 9 in series. The variable delay circuit 24 of FIG. 11 has a control MOS-FET 64 inserted between the MOS-FETs 50 and 52 forming the CMOS inverter 60, and the
A control MOS-FET 62 is inserted between the OS-FET 50 and the power supply V _DD . The variable delay circuit 24 of FIG. 12 is a case where the CMOS inverters 60 are connected in a plurality of stages, and the applied voltage is controlled commonly by each stage by the control MOS-FETs 62 and 64. Here, a concrete example of the embodiment shown in FIG. 1 is shown in FIG. In FIG. 13, reference numeral 70 denotes a power supply circuit, which regulates a DC voltage by a regulator 72 to supply power supply voltages V _DD , V _SS (v _SS = O
V) is output. Reference numeral 74 is a delay time stabilizing circuit. That is, the applied voltage of the gate circuit is controlled so that the delay time of the gate circuit is always constant regardless of variations in the power supply voltages V _DD , V _SS and temperature. In the delay time stabilization circuit 74, the ring oscillator 76 uses the delay characteristic of the inverter, and an odd number of inverters 78, 80, 82 are connected in cascade, and the output of the final stage inverter 82 is fed back to the first stage inverter 78. Configured. Each of the inverters 78, 80, 82 is constructed, for example, as shown in FIG. The oscillation frequency of the ring oscillator 76 is determined by the delay time of its open loop. The oscillation output of the ring oscillator 76 is waveform-shaped by the applied voltage 84 and then input to the phase comparator 86. The phase comparator 86 is
This signal and the reference frequency signal obtained by dividing the output pulse of the crystal oscillator 88 by the frequency divider 90 are compared in frequency and phase, and a signal having a pulse width corresponding to the difference is output. The output pulse of the phase comparator 86 is smoothed by the low pass filter 92. The control voltage generation circuit 94 generates control voltages Vc1 and Vc2 based on the output of the low pass filter 92. This control voltage
Inverter 7 in which Vc1 and Vc2 form the ring oscillator 76
It is input to the control input terminals c1 and c2 of 8,80 and 82 to control the applied voltage. Since the delay characteristics of the inverters 78, 80, and 82 change depending on the applied voltage, if they are configured to provide negative feedback with the above loop, a so-called PLL is created, and an extremely stable oscillation frequency (frequency divider) is generated from the ring oscillator 76.
Accuracy of the reference frequency from 90) is obtained. In other words, regardless of fluctuations in power supply voltage V _DD , V _SS and temperature, each inverter
78, 80 and 82 are controlled with a constant delay time. Therefore, the entire circuit shown in Fig. 13 is created on one IC board, and the power supply voltages V _DD and V _SS and the control voltages Vc1 and V
If c2 is added in common, the delay time of each inverter will be stable without being affected by variations in the power supply voltages V _DD , V _SS and temperature. The variable delay circuit 24 includes a plurality of stages of inverters 24-1 to 24.
-N is connected in cascade. Here, the jitter signal (AC signal) output from the buffer amplifier 46 is added to the control voltages Vc1 and Vc2 via the capacitors C10 and C12 and added to the inverters 24-1 to 24-n, and the delay time is variably controlled. doing. The FM detection circuit 34 connects the inverters 34-1 to 34-4 in cascade, inputs the output of the bandpass filter 28 from the first stage inverter 34-1, and outputs the output of the final stage inverter 34-4 and the bandpass filter 28. It is configured by directly inputting the output from the exclusive OR circuit 100. Each inverter 34 to 34
-4 is a power supply voltage whose applied voltage is controlled by control voltages Vc1 and Vc2 input to terminals c1 and c2 using V _DD and V _SS as power supplies.
Controlled to a constant delay time regardless of fluctuations in _DD , V _SS and temperature. [Embodiment 2] FIG. 14 shows another embodiment of the present invention. This is to double-control the time axis with the color burst signal included in the composite signal in order to achieve more accurate synchronization. That is, the above-described time-axis correction control using the horizontal synchronization signal uses the horizontal synchronization signal having a relatively low frequency as the detection signal for the time-axis fluctuation, so the control accuracy for low-frequency fluctuation is sufficient, but the color image In the case of a signal, appropriate correction control is required even for high-frequency fluctuations on the time axis, and the horizontal synchronization signal alone is often insufficient as a detection signal for the high-frequency fluctuations on the time axis. . This embodiment uses a color burst signal, which is a frequency signal much higher than the horizontal synchronization signal, as a fluctuation detection signal for accurately detecting and correcting the time base fluctuation in the higher frequency band, Both of the long period time axis correction control (coarse control) mainly by the horizontal synchronization signal and the short period time axis control (fine control) mainly by the color burst signal are both realized. The same parts as those in FIG. 1 are designated by the same reference numerals. In FIG. 14, the first variable delay circuit 24 is the variable delay circuit 24 itself of FIG. 1, in which the horizontal synchronizing signal and the reference frequency signal from the frequency divider 103 are compared by the phase comparator 42 and smoothed by the low pass filter 44. The control voltage Vc is applied via the buffer amplifier 46. The system that controls the delay time of the first variable delay circuit 24 according to the time axis error detection output of the phase comparison circuit 42 corresponds to the time axis correction means that performs rough control by the horizontal synchronization signal. The burst gate 102 extracts a color paste signal (3.58 MHz) from the reproduced signal using the horizontal synchronizing signal. The color burst signal is inserted in the back porch of the horizontal synchronizing signal as shown in FIG. Phase comparator 104
Now, the extracted color burst signal and the reference frequency signal from the frequency divider 101 are compared in phase, and the low pass filter 10
After smoothing by 6, the voltage Vc 'is applied as a control voltage to the second variable delay circuit 110 via the buffer amplifier 108. The system for controlling the delay time of the second variable delay circuit 110 according to the time axis error detection output of the phase comparison circuit 104 corresponds to the time axis correction means for performing the fine control by the color burst signal. As described above, the first variable delay circuit 24 and the second variable delay circuit 110 doubly perform the time-axis control to achieve accurate synchronization. The second variable delay circuit 110 may be provided at the position shown by the dotted line 110 'in FIG. In this case, dotted line 11
As indicated by 1, the output of the second variable delay circuit 110 'is applied to the horizontal sync signal separation circuit 40 and the burst gate 102. Further, instead of providing two variable delay circuits, as shown in FIG. 16, the control voltages Vc and Vc ′ are added by the adder 112,
One variable delay circuit 24 may be controlled by the added value Vc + Vc '. Alternatively, the variable delay circuit 24 itself may be replaced with the variable delay circuit 24 shown in FIG.
As shown in Fig. 10, it is configured to have two control systems, and each control system has control voltages Vc (Vc1, Vc2), Vc '(Vc1', Vc
2 ') may be added. [Effects of the Invention] As described above, according to the present invention, since the binarized HF signal obtained from the video disc is directly input to perform the time axis correction, the time axis correction is performed with almost no deterioration of the signal transfer characteristic. Can be performed, a wide reproduction band can be secured, and high image quality can be realized. Further, a complicated mechanism for tangential control in the reproducing head is not needed, and the mechanism of the reproducing head can be simplified and the cost can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2A is a block diagram showing a conventional time axis correction method. FIG. 2B is a block diagram showing another conventional time axis correction method. FIG. 3 is a circuit diagram showing a CMOS inverter. FIG. 4 is a characteristic diagram showing power supply voltage-delay time characteristics in the CMOS inverter of FIG. FIG. 5 is a circuit diagram in which the CMOS inverters of FIG. 3 are connected in multiple stages. 6 to 12 are circuit diagrams showing configuration examples of the variable delay circuit 24 of FIG. FIG. 13 is a circuit diagram showing a specific example of the circuit shown in FIG. FIG. 14 is a circuit diagram showing another embodiment of the present invention. FIG. 15 is a waveform diagram showing a horizontal synchronizing signal and a color burst signal. FIG. 16 is a circuit diagram showing another configuration example in which the time axis control is doubled by the horizontal synchronization signal and the color burst signal. 10 …… Optical pickup, 11 …… Video disc, 24 ……
Variable delay circuit (CMOS inverter circuit), 34, 36, 38 …… FM
Detection circuit, 42, 104 ... Phase comparator (circuit for detecting time axis error).

Claims (1)

(57) [Claims] Pickup means for obtaining a binarized HF signal pulse-FM-modulated from a recording pit on a video disc, a CMOS inverter circuit to which the binarized HF signal is directly input, and a time axis error included in the binarized HF signal. And a circuit for detecting the
A time axis correcting means for electrically changing the time axis of the binary HF signal by changing the power supply voltage of the inverter circuit, and a video disc reproduction signal by pulse FM detecting the time axis corrected binary HF signal. And a video disc reproducing device having an FM detecting means for obtaining the same. 2. 2. The video disc reproducing apparatus according to claim 1, wherein the time axis correction means performs time axis correction including coarse control by a horizontal synchronizing signal and fine control by a color burst signal. apparatus.