JPS6159652A - Pll circuit - Google Patents

Abstract

PURPOSE:To use a phase comparing circuit made into a one-chip IC to make switching between a reference signal and a phase synchronizing signal of this signal possible by connecting a frequency varying varicap of a variable frequency oscillating circuit to a power source and applying the phase comparison output as a difference of the power source voltage. CONSTITUTION:The cathode side of a varicap 66 of a variable frequency oscillating circuit 60 having an oscillation center frequency 4fSC is connected to a power supply terminal 67, and an output VL of a phase comparing circuit 20 is supplied to the connection point between the anode and a capacitor 64 through an LPF40. The oscillated output of the circuit 60 is supplied to a terminal B of a comparator 23 through a terminal 20b of the circuit 20 and an 1/N frequency dividing circuit 22, and the output of a quartz oscillating circuit 70 having an oscillation frequency 4fCK is supplied to a terminal A through a terminal 20a and a 1/M frequency dividing circuit 21. The output signal of the circuit 60 is supplied to a frequency dividing circuit 81 to obtain a subcarrier SC having a frequency fSC, and the output signal of the circuit 70 is supplied to a frequency dividing circuit 82 to obtain a clock CK and horizontal and vertical synchronizing pulses.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PLL circuit suitable for use in, for example, a color video camera system to synchronize clocks and subcarriers.

[Conventional technology]

For example, some PAL color video camera systems use CCD solid-state image sensors;
A PLL circuit is used to clock the solid state t+'3 image element and the subcarriers of the color video signal.

Figure 2 shows an example of this PLL circuit, where 00) is a variable frequency oscillation circuit, which includes an inverter (11), a resistor (12), a crystal oscillator (13), a capacitor (14), (15) and a varicap (16). Consists of. The oscillation frequency is controlled in accordance with the voltage applied to the varicap (16) with the oscillation center frequency set to a frequency four times the clock frequency fIJ.

(20) is a phase comparator circuit that is integrated into an I-chip IC together with a frequency divider circuit, which includes a ]/M frequency divider circuit (21), a 1/N frequency divider circuit (22), and a phase ratio calibrator (23). ). Then, the output signal of variable frequency oscillation 5 (101) is passed through the input terminal (20a) to the 1/M frequency dividing circuit (2I).
supplied to

Also, the sub-rear frequency f of the PAL color video signal is
Crystal oscillation'1 whose oscillation frequency is four times the frequency of SC
The 4fsc signal from 5 (30) is sent to the phase comparator circuit (20
) through the input terminal (20b) of the 1/'N frequency divider circuit (
22). Then, the output of the frequency dividing circuit (21) is connected to one input terminal A of the comparator (23).
) are respectively supplied to the other input terminal B. In this case, 4 fcy/M = 4 fsc/
M, N are determined such that the comparator (2
The re-input signal frequencies of 3) are made equal and this comparator (2)
From 3), an output corresponding to the phase error of both human power signals can be obtained. This phase error output is then filtered through a low-pass filter (4
0) to the varicap (16) of the variable frequency oscillation circuit α0), and the oscillation signal is supplied to the crystal oscillation circuit (3).
It is controlled to have a constant phase relationship with respect to the output signal of 0).

In this conventional PLL circuit, a varicap (16) is used with its anode grounded. Therefore, the output of the phase comparison circuit (20), that is, the low-pass filter (
When the potential of the output VL of 40) becomes high, the oscillation frequency of the variable frequency oscillation circuit αω becomes high. In other words, the direction of change in the phase comparison output and the direction of change in the oscillation frequency of the variable frequency oscillation circuit αψ are the same.

Then, the output signal of the variable frequency oscillator circuit 0ω is supplied to the frequency dividing circuit (51), thereby obtaining the clock CK of frequency fC1+ and the horizontal and vertical synchronizing signal H.
D and VD are obtained.

In addition, the output signal of the crystal oscillator (30) is transmitted to the frequency dividing circuit (52).
) from which a subcarrier SC of frequency r sc is obtained.

In this way, the clock CK and the subcarrier SC are synchronized.

[Problem that the invention seeks to solve]

By the way, in the PLL circuit having the configuration shown in FIG. 2, the clock CK is synchronized with the subcarrier SC using the subcarrier SC as a reference. However, in general, the phase comparison circuit (20)
The output is affected by signal leakage and has fluctuations similar to so-called jitter. Therefore, the output signal of the variable frequency oscillation circuit α0) is also influenced by the fluctuation, and the fluctuation is included in the clock CK from the frequency dividing circuit (51). Since this clock GK is used to read the output from the COD solid-state image sensor, if the clock basis weight includes a variation like this, there is a drawback that it affects the CCD imaging output.

Therefore, as a configuration of the PLL circuit, it is conceivable to use the clock CK as a reference and to synchronize the phase of the subcarriers with this clock.

In this case, if the phase comparator circuit (20), which is a one-chip IC shown in Fig. 2, is used, two inputs are compared at the same frequency, so unlike the example shown in Fig. 2, the variable frequency oscillator circuit is used. The output is passed through the divide-by-one circuit (22) to the comparator (
23), the output of the crystal oscillation circuit must be supplied to the comparator (23) via the divide-by-one circuit (21). However, when the inputs are switched in this way, the direction of change in the output from the phase comparison circuit (20) and the direction of change in the oscillation frequency of the variable frequency oscillation circuit become opposite, making it impossible to use it as is. A phase inversion circuit must be provided between the phase comparison circuit and the variable frequency oscillation circuit. For this reason, the number of components increases, which is undesirable as the circuit (20) in Figure 2 as a 0 phase comparator circuit.
If the insertion positions of the frequency divider circuits (21) and (22) are reversed, there will be no increase in the number of parts, but this will require a new IC, which has the disadvantage of becoming more expensive. .

The present invention aims to provide a PLL circuit that can eliminate the above-mentioned drawbacks.

[Means for solving the problem] In the present invention, subcarriers are locked by a PLL circuit using a clock as a reference,
Although the phase comparator circuit (20), which is a one-chip IC shown in the example of FIG. 2, is used, the method of connecting the varicap for frequency variation of the variable frequency oscillation circuit is changed. That is, in a variable frequency oscillator circuit, the varicap, which conventionally had one end grounded, is connected to the power supply without being grounded, and the phase comparison output is applied as a difference from the power supply voltage.

[Effect]

Conventionally, the voltage applied to the varicap is determined by a comparator circuit (20
) was applied as is, whereas in this invention, the difference between the power supply voltage and the comparison output is applied.
Even if a conventional one-chip IC phase comparison circuit is used, the direction of change in the comparison output and the oscillation frequency of the variable frequency oscillation circuit will match.

〔Example〕

FIG. 1 shows an embodiment of the present invention. In the same figure, (60)
is a variable frequency oscillator circuit whose oscillation center frequency is 4fS
It is said to be C. This oscillation circuit (6o) includes an inverter (61) and a resistor (62) like the circuit α0).

Crystal oscillator (63), capacitor (64) (65
) and a varicap (66), the cathode side of the varicap (66) is connected to the power supply terminal (67), and the connection point between the anode of this varicap (66) and the capacitor (64) low-pass filter (4
The output ■L of the phase comparator circuit (2o) is supplied through the phase comparator circuit (2o).

The oscillation output of this variable frequency oscillation circuit (60) is passed through the input terminal (20b) of the phase comparator circuit (20), and then through the 1/N frequency dividing circuit (22) to the other input terminal B of the comparator (23).
supplied to

Further, (70) is a crystal oscillation circuit with an oscillation frequency of 4fax, and its output is the input terminal (20) of the phase comparator circuit (20).
a), the comparator (
23) is supplied to one input terminal A of 23).

Then, the output signal of the variable frequency oscillation circuit (60) is supplied to the frequency division circuit (81), from which a subcarrier SC of frequency rgc is obtained, and the output signal of the crystal oscillation circuit (7) is supplied to the frequency division circuit (81). It is supplied to the circuit (82) from which the clock CK is obtained, as well as the horizontal and vertical synchronizing pulses HD.
, VD is obtained. That is, since the clock is obtained from a fixed crystal oscillator circuit, the drawbacks of the conventional method do not occur even if this clock is used for CCD reading.

Since the output signal of the variable frequency oscillation circuit and the output signal of the crystal oscillation circuit are supplied to the phase comparison circuit (20) with input terminals opposite to the conventional ones separated by 1ffl, the output of this phase comparison circuit (20) Although the direction of is opposite to that of the conventional one, one end of the varicap of the variable frequency oscillation circuit (60) is connected to the power supply, and the comparison output is supplied to this varicap as the difference between the power supply voltage and the power supply voltage. Oscillation circuit (
The direction of change in the oscillation frequency of 60) and the direction of change in the comparison output match, and in this case, the reference signal is set to the clock CK, and this clock CK and the subcarrier SC are synchronized in the same way as in the conventional case. It will be done.

〔Effect of the invention〕

According to this invention, it is possible to use a conventionally used phase comparator circuit implemented as a single-chip IC as is,
Furthermore, the reference signal and a signal whose phase is synchronized therewith can be alternated without using a phase inversion circuit. Therefore, there is no risk of increased costs due to an increase in the number of parts or the manufacture of new ICs.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of an example of a PLL circuit of the present invention, and FIG. 2 is a system diagram of an example of a conventional PLL circuit. α0) and (60) are variable frequency oscillation circuits, (20) is a phase comparator circuit integrated into a single chip IC, (21) and (2
2) is a frequency dividing circuit, (16) and (66) are varicamps, and (30) and (70) are crystal oscillation circuits. Figure 1 Figure 2

Claims (1)

[Claims] A variable frequency oscillation circuit using a varicap, dividing the first signal to 1/N, dividing the second signal to 1/M,
One end side of the varicap when the direction of change in the output from this IC is opposite to the direction of change in the oscillation frequency of the variable frequency oscillation circuit is provided. is connected to the power supply terminal, and the output from the IC is applied to the varicap as a difference from the power supply voltage.