JPH01218214A - Phase locked oscillating circuit - Google Patents
Phase locked oscillating circuitInfo
- Publication number
- JPH01218214A JPH01218214A JP63042350A JP4235088A JPH01218214A JP H01218214 A JPH01218214 A JP H01218214A JP 63042350 A JP63042350 A JP 63042350A JP 4235088 A JP4235088 A JP 4235088A JP H01218214 A JPH01218214 A JP H01218214A
- Authority
- JP
- Japan
- Prior art keywords
- output
- phase
- vcd
- edge
- vco
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims abstract description 15
- 230000010354 integration Effects 0.000 claims abstract 4
- 230000001360 synchronised effect Effects 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、比例増幅器および積分回路を介して電圧制御
発振器(以下、vco ) ’1制御し、位相誤差零の
発振出力を得る位相同期発振回路に関するものでるる。[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a phase synchronized oscillation system in which a voltage controlled oscillator (hereinafter referred to as VCO) '1 is controlled through a proportional amplifier and an integrating circuit to obtain an oscillation output with zero phase error. There are things related to circuits.
かかる発振回路は、発振出力と外部入力信号との位相誤
差を問題とする装置において特に用いられでおり、IJ
2図のブロック図に示すとおり、基準とする外部入力信
号S1とVCOlの発振出力OUTとの位相を位相北端
器2により比較し、この出力を比例増幅器3により比例
的に増幅すると共に、積分回路4により積分し、これら
の出力を加算器5により加算したうえ、抵抗器6を介し
てvcotの制御端子へ与え、これによってvcotの
発振出力位相を外部入力信号S1の位相と同期させるも
のとなっている。Such oscillation circuits are particularly used in devices in which a phase error between the oscillation output and an external input signal is a problem;
As shown in the block diagram of Fig. 2, the phase of the reference external input signal S1 and the oscillation output OUT of the VCOl is compared by the phase north terminal device 2, and this output is proportionally amplified by the proportional amplifier 3, and the integrator circuit 4, these outputs are added by an adder 5, and then applied to the control terminal of vcot via a resistor 6, thereby synchronizing the oscillation output phase of vcot with the phase of external input signal S1. ing.
しかし、上述の構成においては、加算器5を必要とする
と共に、比例増幅器3の比例係数および積分回路4の積
分係数を各個別に調整する必要があり、これに応じて回
路構成が複雑化し、量産上不適当であり、かつ、高価に
なる等の欠点を生じている。However, in the above configuration, the adder 5 is required, and the proportional coefficient of the proportional amplifier 3 and the integral coefficient of the integral circuit 4 must be adjusted individually, and the circuit configuration becomes complicated accordingly. It is unsuitable for mass production and has drawbacks such as being expensive.
〔l1題を解決するための手段〕
前述の課題を解決するため、本発明はりぎの手RKより
構成するものとなっている。[Means for Solving Problem 11] In order to solve the above-mentioned problem, the present invention is constituted by a hand RK.
すなわち、可変容量ダイオード(以下、van )へ印
加する電圧により発振周波数の制御されるVCOと、こ
のVCOの出力と外部入力信号との位相を比較する位相
比較器と、これの出力を比例的に増幅しVCDの一端へ
印加する比例増幅器と、位相比較器の出力を積分しVC
Dの他端へ印加する積分回路とを備えたものである。That is, a VCO whose oscillation frequency is controlled by a voltage applied to a variable capacitance diode (hereinafter referred to as van), a phase comparator that compares the phase of the output of this VCO and an external input signal, and a phase comparator that compares the output of this VCO proportionally. The proportional amplifier amplifies and applies it to one end of the VCD, and the output of the phase comparator is integrated and the VC
and an integrating circuit that applies voltage to the other end of D.
したがって、比例増幅器および積分回路のも出力により
VCOが直接制御され、加算器が不要となる。Therefore, the VCO is directly controlled by the outputs of the proportional amplifier and the integrating circuit, eliminating the need for an adder.
以下、実施例を示す第1図のブーツク図によって本発明
の詳細な説明する。Hereinafter, the present invention will be explained in detail with reference to the boot diagram of FIG. 1 showing an embodiment.
同図においては、VCD7へ印加する電圧により発振周
波数の制御されるvcoaが設けてあり、これの発振出
力OUTと外部入力信号Slとの位相を位相比較器2に
より比較し、この出力を比例増幅器3により比例的に増
幅のうえ、抵抗器9を介してVCD7の一端へ印加する
と共に1位相比較器2の出力を積分回路4により積分し
、抵抗器10t−介してVCD7の他端へ印加しており
、これによってvcoaの発振位相を外部入力信号S1
の位相と同期させている。In the figure, a VCOA whose oscillation frequency is controlled by the voltage applied to the VCD 7 is provided, and the phase of the oscillation output OUT of this VCOA and the external input signal Sl is compared by a phase comparator 2, and this output is connected to a proportional amplifier. 3, and then applied to one end of the VCD 7 through a resistor 9. At the same time, the output of the 1-phase comparator 2 is integrated by an integrating circuit 4, and applied to the other end of the VCD 7 through a resistor 10t. This allows the oscillation phase of vcoa to be adjusted to the external input signal S1.
It is synchronized with the phase of
したがって、比例増幅器3および積分回路4の各出力に
より、VCD7の端子間電圧が直接定まり、加算回路5
が不要になると共に、抵抗器9.10により各係数の個
別調整が自在となり、簡単な構成によって目的を達する
ことができる。Therefore, each output of the proportional amplifier 3 and the integrating circuit 4 directly determines the voltage between the terminals of the VCD 7, and the adding circuit 5
is not necessary, and each coefficient can be adjusted individually using the resistors 9 and 10, so that the purpose can be achieved with a simple configuration.
以上の説明により明らかなとお9本発明によれば、比例
増幅器の出力をVCDの一端へ印加すると共に、積分回
路の出力をVCDの他端へ印加するものとし次ことによ
り、構成の簡略化および各係数の個別調整が自在となシ
、位相誤差零を必要とする場合の同期発振において顕著
な効果が得られる。As is clear from the above description, according to the present invention, the output of the proportional amplifier is applied to one end of the VCD, and the output of the integrating circuit is applied to the other end of the VCD. Each coefficient can be adjusted individually, and a remarkable effect can be obtained in synchronous oscillation when zero phase error is required.
81図は本発明の実施例を示すブロック図、第2図は従
来例のブロック図である。
2@・・・位相比較器、3・・拳・比例増幅器、4拳・
・・積分回路、7・・・・可変容量ダイオード、8・・
・・電圧制御発振器、sl ・・・・外部入力信号、0
υT・・・・発振出力。FIG. 81 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. 2 @... Phase comparator, 3... Fist/proportional amplifier, 4 Fist/
... Integrating circuit, 7... Variable capacitance diode, 8...
...Voltage controlled oscillator, sl ...External input signal, 0
υT...Oscillation output.
Claims (1)
制御される電圧制御発振器と、該発振器の出力と外部入
力信号との位相を比較する位相比較器と、該比較器の出
力を比例的に増幅し前記可変容量ダイオードの一端へ印
加する比例増幅器と、前記比較器の出力を積分し前記可
変容量ダイオードの他端へ印加する積分回路とを備えた
ことを特徴とする位相同期発振回路。a voltage controlled oscillator whose oscillation frequency is controlled by a voltage applied to a variable capacitance diode; a phase comparator that compares the phase of the output of the oscillator with an external input signal; and a phase comparator that proportionally amplifies the output of the comparator. A phase-locked oscillator circuit comprising: a proportional amplifier that applies voltage to one end of a variable capacitance diode; and an integration circuit that integrates the output of the comparator and applies it to the other end of the variable capacitance diode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63042350A JPH01218214A (en) | 1988-02-26 | 1988-02-26 | Phase locked oscillating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63042350A JPH01218214A (en) | 1988-02-26 | 1988-02-26 | Phase locked oscillating circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01218214A true JPH01218214A (en) | 1989-08-31 |
Family
ID=12633583
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63042350A Pending JPH01218214A (en) | 1988-02-26 | 1988-02-26 | Phase locked oscillating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01218214A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2424325A (en) * | 2005-03-18 | 2006-09-20 | Agilent Technologies Inc | Tuning phase locked loops |
DE102006041804A1 (en) * | 2006-09-06 | 2008-03-27 | Infineon Technologies Ag | Phase-locked loop |
-
1988
- 1988-02-26 JP JP63042350A patent/JPH01218214A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2424325A (en) * | 2005-03-18 | 2006-09-20 | Agilent Technologies Inc | Tuning phase locked loops |
US7315217B2 (en) | 2005-03-18 | 2008-01-01 | Avago Technologies General Ip (Singapore) Pte Ltd. | Linear phase-locked loop with dual tuning elements |
DE102006041804A1 (en) * | 2006-09-06 | 2008-03-27 | Infineon Technologies Ag | Phase-locked loop |
US7733188B2 (en) | 2006-09-06 | 2010-06-08 | Infineon Technologies Ag | Phase locked loop |
DE102006041804B4 (en) * | 2006-09-06 | 2014-04-03 | Infineon Technologies Ag | Phase-locked loop |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH01218214A (en) | Phase locked oscillating circuit | |
JPS6372204A (en) | Modulation sensitivity correction circuit for voltage controlled oscillator | |
JPH10327043A (en) | Frequency tracing device | |
JPH04329016A (en) | Equivalent inductance circuit | |
JP4283664B2 (en) | Frequency lock loop circuit, clock recovery circuit, and receiver | |
JPH04170219A (en) | Duty correction circuit | |
JPH09200046A (en) | Phase difference control pll circuit | |
JPH022721A (en) | Phase locked loop oscillation circuit | |
JPS6326030A (en) | Pll circuit | |
JPH07297641A (en) | Clock oscillator | |
JPH05268109A (en) | Ic for receiver and receiver using the ic | |
JPH02171026A (en) | Analog pll circuit | |
JPH07135425A (en) | Fm receiver | |
JP3081418B2 (en) | Automatic filter adjustment circuit | |
JPH024019A (en) | Oscillation controller | |
KR100213233B1 (en) | Apparatus for adjusting filter frequency | |
JPH0537370A (en) | Frequency synthesizer | |
JPH03242017A (en) | High speed stabilized voltage controlled oscillation circuit | |
JPH0548643B2 (en) | ||
JPH03117026A (en) | Filter and phase locked loop circuit | |
JPS59202707A (en) | Fm modulator | |
JP2002141799A (en) | Pll circuit | |
JPH02142221A (en) | Phase locked loop circuit | |
JPS63308406A (en) | Automatic adjusting circuit for constant current | |
JPH0242817A (en) | Stabilized voltage controlled oscillator |