JPH02142221A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To output the signal of an arbitrary frequency in the case of a self- traveling oscillation mode by outputting the pulse with pulse width to be specified by a time constant, which is determined according to the values of a resistor and a capacitor, and adding a direct current voltage component, which is obtained through a low-pass filter, to a crystal oscillator when a digital signal is interrupted. CONSTITUTION:A crystal oscillator 300 is connected to a low-pass filter 200 and an output frequency is changed in correspondence to the output voltage of the low-pass filter. A frequency dividing circuit 400 is connected to the crystal oscillator 300 and the output frequency of the crystal oscillator 300 is divided into a prescribed frequency. When an input signal is interrupted, a phase comparator 100 outputs the pulse of the pulse width to be supplied by the time constant which is determined according to the values of a resistor R and a capacitor C. For such a pulse, by adding the direct current component, which is obtained through the low-pass filter 200, to the crystal oscillator 300, the signal of the frequency to correspond to the pulse width can be outputted. Thus, when the input signal is interrupted, the signal of the desired arbitrary frequency can be outputted in the case of the self-traveling oscillation mode.

Description

[Detailed Description of the Invention] [Summary] Regarding phase-locked circuits used in communication devices, etc., the purpose of this invention is to provide a phase-locked circuit that can output a signal of any frequency in free-running oscillation mode. It has an input terminal and a resistor and capacitor whose values can be adjusted.A digital signal is applied to one of the input terminals, and the output of a frequency dividing circuit is applied to the other.The phases of the two are compared and the phase difference is accommodated. A phase comparator that outputs a pulse with a pulse width, and when the digital signal is interrupted, outputs a pulse with a pulse width given by a time constant determined by the values of the resistor and capacitor. A low-pass filter that inputs the voltage and outputs the DC voltage component contained in the input, a crystal oscillator that is connected to the low-pass filter and whose output frequency changes according to the output voltage of the low-pass filter, and a crystal oscillator that outputs the DC voltage component contained in the input. The frequency dividing circuit is connected to the crystal oscillator and divides the output frequency of the crystal oscillator into a predetermined frequency.

[Industrial application field]

The present invention relates to improvements in phase synchronized circuits used in communication devices and the like.

At this time, there is a demand for a phase locked circuit that can output a signal of any frequency in free-running oscillation mode.

[Conventional technology]

FIG. 4 is a block diagram showing the configuration of an example of a phase locked circuit.

FIG. 5 is a block diagram showing the circuit configuration of a phase comparator (hereinafter referred to as PC) used in a conventional example.

FIG. 6 is a time chart explaining the operation of the conventional example.

As is well known, the phase synchronization circuit shown in FIG. 4 is a circuit for obtaining an output signal phase-synchronized with an input signal, and is used for frequency conversion and the like.

An outline of its operation will be explained below. That is, in FIG. 4, a digital signal (its frequency is, for example, f 1n = 64 KHz) is input to one input terminal of the PCI,
The output signal of the frequency divider circuit 4 is input to the other input terminal.

Then, the PCI compares the phases of the two and outputs a voltage corresponding to the phase difference.

The output voltage of the PCI is input to a low pass filter (hereinafter referred to as LPF) 2, which outputs a DC voltage component included in the digital input voltage. The DC output voltage of the LPF 2 is input to a voltage controlled crystal oscillator (hereinafter referred to as VCXO) 3, and the oscillation frequency f0□ of the VCXO 3 is changed according to the DC voltage. (For example, f. uL = t.

xft). The output of VCXO3 is branched and applied to frequency divider circuit 4. The frequency division ratio of frequency divider circuit 4 is 1/10 in this case
becomes. Then, the output of the frequency dividing circuit 4 is applied to the other input terminal of the PCI.

Conventionally, Pct is configured as shown in FIG. 5, for example. The input signal (ftj) is input to the differentiating circuit 5, and the rising portion of the pulse is differentiated.

Then, the differential output is input to a reset terminal of a flip-flop (hereinafter referred to as FF) 6 to perform a reset. (
Figure 6 ■).

On the other hand, the output pulse (fout XI/n) of the frequency dividing circuit 4 is applied to the set terminal C of the FF6. As a result, r is applied to the set terminal of FF6, as shown in Figure 6 (■). utX
When a 1/n pulse is input, "1" is output, and when the output of the differentiator circuit 5 is input to the reset terminal, "0" is output, and a voltage with a pulse width proportional to the phase difference between the two is output from FF6.
is output from. By adding the output of FF6 to LPF 2, a DC component proportional to the pulse width is output.

In this way, the output is synchronized with the phase of the input signal and has a predetermined frequency.

[Problem to be solved by the invention]

However, in the above-mentioned phase-locked circuit, by utilizing the fact that FF6 is a 1/2 frequency dividing circuit when the input signal is interrupted, the output frequency of VCXO3 is set to 50% duty. It was set as the center frequency. However, in this case, the output frequency is limited, so
There was a problem that the scope of application was limited.

Therefore, an object of the present invention is to provide a phase locked circuit that can output a signal of any frequency in free-running oscillation mode.

[Means to solve the problem]

The above problem is solved by the circuit configuration shown in FIG.

That is, in FIG. 1, 100 has two input terminals and a resistor R and a capacitor C, each of which has an adjustable value.
A digital signal is applied to one of the input terminals, the output of the frequency dividing circuit 400 is applied to the other, the phases of the two are compared, and a pulse with a pulse width corresponding to the phase difference is output. When the digital signal is interrupted, the resistor R and This is a phase comparator that outputs a pulse with a pulse width given by a time constant determined by the value of capacitor C.

200 is a low-pass filter that is connected to the phase comparator, receives the output of the phase comparator, and outputs the DC voltage component included in the input.

300 is a crystal oscillator that is connected to the low-pass filter and changes its output frequency according to the output voltage of the low-pass filter.

A frequency dividing circuit 400 is connected to the crystal oscillator and divides the output frequency of the crystal oscillator into a predetermined frequency.

[For production]

In FIG. 1, when the input signal is disconnected, the phase comparator 100
outputs a pulse with a pulse width given by a time constant determined by the values of the resistor R and capacitor C. By applying the DC component obtained by passing the pulse of the output of the phase comparator 100 through the low-pass filter 200 to the crystal oscillator 300, it is possible to output a signal with a frequency corresponding to the pulse width.

As a result, a signal of any desired frequency can be output in the free-running oscillation mode when the input signal is disconnected.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a PC circuit used in an embodiment of the present invention.

FIG. 3 is a time chart explaining the operation of the embodiment.

The same reference numerals refer to the same objects throughout the design.

In FIG. 2, an input digital signal (fi,) is applied to an input disconnection detection circuit 7. On the other hand, the frequency dividing circuit 4 shown in FIG.
The output (f out X 1 / n ) is applied to contact 8 of the switch. The contact 8 of the switch is normally set to the a side. The outputs of the input disconnection detection circuit 7 and the switch contact 8 are applied to a known phase comparator 9, their phases are compared, and the phase comparator 9 outputs a voltage pulse with a pulse width proportional to the phase difference between the two.

The output of the phase comparator 9 is connected to the VCX shown in FIG. 4 via the switch contact 11 (usually set to the a' side) and the LPF 2.
In addition to O3, a pulse signal with a frequency corresponding to the output DC voltage of LPF2 (7) is output from VCXO3.

Now, when the input signal is disconnected, the input disconnection detection circuit 7 detects this, applies a control signal to the switch contacts 8 and 11, and switches the switch contacts 8 and 11 to A and B'', respectively.

As a result, the output of frequency dividing circuit 4 is Cf0ut
is applied to a known mono-multi vibrator circuit (hereinafter referred to as mono-multi vibrator circuit) 10 via a switch contact 8. Then, the above signal (foutXl/n) acts as a trigger, and as shown in Figure 3 (■), from the mono multi circuit 10, due to the characteristics of the mono multi circuit 7, the time constant of the resistor R and capacitor C of the mono multi circuit 7 A voltage with a determined pulse width will be output.

In this way, it is possible to output signal pulses of any frequency in the free-running oscillation mode.

〔Effect of the invention〕

As explained above, according to the present invention, a signal of any frequency can be output in the free-running oscillation mode.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block diagram showing the configuration of a PC circuit used in an embodiment of the present invention, Fig. 3 is a time chart explaining the operation of the embodiment, and Fig. 4. 5 is a block diagram showing the configuration of an example of a phase synchronized circuit; FIG. 5 is a block diagram showing the configuration of a PC circuit used in the conventional example; and FIG. 6 is a time chart illustrating the operation of the conventional example. In the figure, 100 is a phase comparator, 200 is a low-pass filter, 300 is a crystal oscillator, and 400 is a frequency dividing circuit. Time chart No. 3 explaining the operation of Fig. 5']
figure

Claims (1)

[Claims] Two input terminals and a resistor (R
) and a capacitor (C), a digital signal is applied to one of the input terminals, the output of the frequency divider circuit (400) is applied to the other, the phases of the two are compared, and the pulse width corresponding to the phase difference is determined. a phase comparator (100) that outputs a pulse and outputs a pulse with a pulse width given by a time constant determined by the values of the resistor and capacitor when the digital signal is interrupted; a low-pass filter (200) that inputs the output of the comparator and outputs a DC voltage component included in the input; Crystal oscillator that changes frequency (3
00); and a frequency dividing circuit (400) connected to the crystal oscillator and dividing the output frequency of the crystal oscillator into a predetermined frequency.