JPH01202028A - Frequency signal device - Google Patents

Abstract

PURPOSE:To highly stably and accurately obtain various frequency monitoring/ selecting signals by only one circuit by obtaining plural kinds of monitoring/ selecting signals from a reference signal by a PLL means. CONSTITUTION:A phase locked loop(PLL) part 2 is provided with a frequency dividing circuit 21, a phase comparator 22 for comparing the phase of a signal applied to the circuit 21 with that of an output signal of a frequency dividing circuit 25, a low pass filter(LPF) 23 for forming a DC voltage corresponding to the frequency deviation between the two input signals of the comparator 22, a voltage control oscillator 24 for oscillating a signal with frequency corresponding to the DC voltage value applied from the LPF 23, and a frequency dividing circuit 25 for dividing the frequency of an output from the oscillator 24 in accordance with the set contents of a switch part 3. When the PLL part changes the frequency dividing ratio of the circuit 25 connected between the voltage control oscillator(VCO) 24 and the phase comparator 22, the output of the VCO can be set up as a signal corresponding to a required monitoring/ selecting signal and the output can be highly stably and accurately held.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a monitoring/selection signal used in a telephone line for monitoring the status of incoming calls, answering calls, ending calls, talking, etc., and as a call number 4 and selection signal. The present invention relates to a frequency signal device for generating.

2. Description of the Related Art Conventionally, this type of frequency signal device has been configured as a replaceable unit using an analog oscillator that generates only the required frequency.

In response to different monitoring/selection signal requirements, the oscillator unit that generates the corresponding signal can be replaced, or multiple oscillator units can be set and the desired frequency signal can be obtained by switching between them. has been done.

Problems to be Solved by the Invention However, in the conventional configuration as described above, one oscillator unit corresponds to only one frequency;
If signals of multiple frequencies were required, the required number of oscillator units had to be prepared. Furthermore, because of the analog configuration, it was difficult to set the frequency with high precision.

The present invention solves the conventional problems as described above.
It is an object of the present invention to provide a frequency signal device that can obtain a plurality of highly stable and highly accurate monitoring/selection frequency signals with one circuit.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention includes an oscillation section that generates a reference signal, a switch section that sets a monitoring/selection signal, and a phase shifter for the reference signal given by the oscillation section. The device is equipped with a PLL section that outputs a signal with a frequency set by the switch section using locked loop means, and an output section that obtains a monitoring/selection signal from the signal output from the PLL section.

Effects The present invention has the above configuration (secondarily, it has the following effects;
That is, the PLL section converts the VCO output into a signal corresponding to the desired monitoring/selection signal by changing the frequency division ratio of the frequency divider circuit provided between the voltage controlled oscillator (VCO) and the phase comparator. By performing frequency division and filtering processing on this signal, a monitoring/selection signal can be obtained.

Since the PLL output depends on the oscillation accuracy of the clock, the output is held highly stable and highly accurate.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

The figure is a block diagram of a frequency signal device in an embodiment of the present invention. 1 is a tarokk signal (for example, P of an electronic exchange
An oscillation unit 2 generates a high frequency signal (for example, 2,048 ?V1) output from the oscillation unit 1 (CM clock signal).
This is a PLL (phase-locked loop) section that outputs a frequency signal that is highly stable and highly accurate. 3 is a switch unit that is connected to the PLL unit 2 and sets a frequency division ratio corresponding to the monitoring/selection signal to be obtained; 4 is a frequency divider circuit that divides and outputs the output signal of the PLL unit 2; and 5 is a divider unit. A band pass filter (B, P, F
). The frequency dividing circuit 4 and the bandpass filter 5 constitute an output section.

The PLL unit 2 divides the frequency of the clock signal (for example, 1/20
48) A phase comparator 22 that compares the phase of a signal given from the frequency divider circuit 21 and an output signal of the frequency divider circuit 25, which will be described later, and a frequency deviation between the two input signals of the phase comparator 22. a low-pass filter 23 that generates a corresponding DC voltage, and a voltage-controlled oscillator 2 that oscillates a signal with a frequency that corresponds to the DC voltage value provided by the low-pass filter 23.
4 and a frequency dividing circuit 25 that frequency divides the output of the voltage controlled oscillator 24 according to the settings of the switch section 3.

Next, the operation of the embodiment of the present invention having the above configuration will be explained.

When the frequency divider circuit 25 outputs 1 KHz reference signal from the frequency divider circuit 21, no output signal is generated from the phase comparator 22, and therefore the output voltage of the low-pass filter 23 is If the division ratio of the frequency dividing circuit 25 is N, the voltage controlled oscillator 24 has a division ratio of (NX 100OH
A signal near the frequency of 2) is self-oscillated. In addition,
Since the oscillation section 1 is an oscillation circuit using a crystal resonator, it is possible to oscillate at a stable frequency, and an extremely stable and highly accurate clock signal is provided to the frequency dividing circuit 21.

Here, the frequency dividing circuit 25 is 1/100 f 1.1/
100 f2° 1/100 fa and l/100 f4 are frequency-divided and output as fl, f2. fa, f4
can output an output signal. Frequency dividing circuit 25
When outputting fl, the phase of this fl and the reference signal fO from the frequency dividing circuit 21 is compared in the phase comparator 22, a pulse signal corresponding to the phase difference is output, and the low-pass filter 23 outputs the phase. Generates a DC voltage according to the phase difference.
When fl has a higher frequency than the reference signal fO, a positive DC voltage is output from the low-pass filter 23, and conversely, f
When l has a lower frequency than the reference signal fO, a negative DC voltage is output from the low-pass filter 23.

When fl)fo, the voltage controlled oscillator 24 oscillates a signal with a frequency of 100f using the DC voltage output from the low-pass filter 23 according to the phase difference of (ft-fo). This oscillation frequency 100 fl is divided by the frequency dividing circuit 25 and then fed back to the phase comparator 22 and also supplied to the frequency dividing circuit 3. Frequency divider circuit 3 is 100f
Divide the frequency of the x signal to 1/100 to obtain the frequency-divided output of fl. The output of the frequency dividing circuit 3 is a rectangular wave signal which is shaped into a sine wave by a band pass filter 5, and this becomes a monitoring/selection signal f1. Since the output of the voltage controlled oscillator 24 is fed back to the PLL section 2, it is always locked to the set frequency, and the output signal of the PLL section 2 does not fluctuate. In the above explanation, fl was used as an example, but f2
~f4, a DC voltage corresponding to the phase difference according to the frequency change is output from the low-pass filter 23, and the voltage controlled oscillator 24 is outputted at a frequency corresponding to this voltage value.
oscillates. Further, in the above embodiment, an example was shown in which four types of frequencies (fx to f4) are set by the frequency dividing circuit 25, but any number N of frequencies can be set by using a dip switch within the range in which the voltage controlled oscillator 24 can operate. It can be set using, etc.

As described above, according to the embodiment of the present invention, N types of monitoring/selection signals can be generated based on one clock frequency, so there is no need to prepare multiple oscillator units as in the conventional case. .

In addition, when a PCM clock used in electronic exchanges is used as an oscillation source, there is no need to separately provide an oscillator such as a crystal oscillator, and it is possible to use an integrated circuit, resulting in miniaturization and a reduction in the number of parts. This also makes it possible to reduce costs.

Furthermore, when a high precision frequency is required, a digital configuration using a PLL allows for easier integration than an analog configuration.

Effects of the Invention As described above, according to the present invention, since a plurality of types of monitoring/selection signals can be obtained from a reference signal by the PLL means, one circuit can generate monitoring/selection signals of various frequencies with high stability. High accuracy can be obtained.

[Brief explanation of the drawing]

The figure is a block diagram showing a frequency signal device in one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Oscillation part, 2... PLL part, 3... Switch part, 4... Frequency division circuit, 5... Band pass filter (
B, P, F).

Claims (1)

[Claims] an oscillation section that generates a reference signal, a switch section that sets a monitoring/selection signal, and a signal with a frequency set by the switch section using a phase-locked loop (PLL) means to convert the reference signal given from the oscillation section into a signal with a frequency set by the switch section. PLL that outputs
A frequency signal device comprising: a PLL section; and an output section that obtains a monitoring/selection signal from a signal output from the PLL section.